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PEP8 formatting

This commit is contained in:
mrg 2020-09-29 16:52:27 -07:00
parent 066570bfeb
commit b147e8485c
6 changed files with 34 additions and 27 deletions
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7
compiler/modules/bank.py
View File

@ -8,8 +8,8 @@
import debug
import design
from sram_factory import factory
from math import log, ceil, floor
from tech import drc, layer
from math import log, ceil, floor, sqrt
from tech import drc
from vector import vector
from globals import OPTS
@ -377,7 +377,8 @@ class bank(design.design):
try:
local_array_size = OPTS.local_array_size
except AttributeError:
local_array_size = 0
#local_array_size = ceil(sqrt(self.num_cols + self.num_spare_cols))
local_array_size = ceil(sqrt(self.num_cols + self.num_spare_cols))
if local_array_size > 0:
# Find the even multiple that satisfies the fanout with equal sized local arrays

3
compiler/options.py
View File

@ -30,9 +30,6 @@ class options(optparse.Values):
num_r_ports = 0
num_w_ports = 0
# By default, use local arrays with a max fanout of 16
#local_array_size = 16
# Write mask size, default will be overwritten with word_size if not user specified
write_size = None

35
compiler/sram/sram_base.py
View File

@ -87,8 +87,8 @@ class sram_base(design, verilog, lef):
for bit in range(self.word_size + self.num_spare_cols):
self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT")
self.add_pin("vdd","POWER")
self.add_pin("gnd","GROUND")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_global_pex_labels(self):
"""
@ -118,8 +118,19 @@ class sram_base(design, verilog, lef):
Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]]
Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]]
OPTS.words_per_row = self.words_per_row
self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))), storage_layer_name, Q_bar)
row = int(cell % (OPTS.num_words / self.words_per_row))
col = int(cell / (OPTS.num_words))
self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num,
row,
col,
storage_layer_name,
Q))
self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num,
row,
col,
storage_layer_name,
Q_bar))
for cell in range(len(bl_offsets)):
col = bl_meta[cell][0][2]
@ -131,27 +142,23 @@ class sram_base(design, verilog, lef):
col = br_meta[cell][0][2]
for bitline in range(len(br_offsets[cell])):
bitline_location = [float(bank_offset[cell][0]) + br_offsets[cell][bitline][0], float(bank_offset[cell][1]) + br_offsets[cell][bitline][1]]
br.append([bitline_location, br_meta[cell][bitline][3], col])
br.append([bitline_location, br_meta[cell][bitline][3], col])
for i in range(len(bl)):
self.add_layout_pin_rect_center("bl{0}_{1}".format(bl[i][1], bl[i][2]), bitline_layer_name, bl[i][0])
self.add_layout_pin_rect_center("bl{0}_{1}".format(bl[i][1], bl[i][2]), bitline_layer_name, bl[i][0])
for i in range(len(br)):
self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0])
self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0])
# add pex labels for control logic
for i in range (len(self.control_logic_insts)):
for i in range(len(self.control_logic_insts)):
instance = self.control_logic_insts[i]
control_logic_offset = instance.offset
for output in instance.mod.output_list:
pin = instance.mod.get_pin(output)
pin.transform([0,0], instance.mirror, instance.rotate)
pin.transform([0, 0], instance.mirror, instance.rotate)
offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]]
self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), storage_layer_name, offset)
self.add_layout_pin_rect_center("{0}{1}".format(pin.name, i), storage_layer_name, offset)
def create_netlist(self):
""" Netlist creation """

2
compiler/sram/sram_config.py
View File

@ -25,7 +25,7 @@ class sram_config:
# This will get over-written when we determine the organization
self.words_per_row = words_per_row
self.compute_sizes()
self.compute_sizes()
def set_local_config(self, module):
""" Copy all of the member variables to the given module for convenience """

9
compiler/tests/50_riscv_func_test.py
View File

@ -8,14 +8,15 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 50_riscv_func_test")
# @unittest.skip("SKIPPING 50_riscv_func_test")
class riscv_func_test(openram_test):
def runTest(self):
@ -33,7 +34,7 @@ class riscv_func_test(openram_test):
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import functional, delay
from characterizer import functional
from sram_config import sram_config
c = sram_config(word_size=32,
write_size=8,
@ -53,7 +54,7 @@ class riscv_func_test(openram_test):
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
(fail, error) = f.run()
self.assertTrue(fail,error)
self.assertTrue(fail, error)
globals.end_openram()

5
compiler/tests/50_riscv_phys_test.py
View File

@ -8,14 +8,15 @@
#
import unittest
from testutils import *
import sys,os
import sys, os
sys.path.append(os.getenv("OPENRAM_HOME"))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 50_riscv_phys_test")
# @unittest.skip("SKIPPING 50_riscv_phys_test")
class riscv_phys_test(openram_test):
def runTest(self):