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Make global bitline only as wide as needed rather than whole array

This commit is contained in:
mrg 2020-09-15 13:24:38 -07:00
parent aff3cd2aab
commit 5e94d76127
1 changed files with 2 additions and 2 deletions
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4
compiler/modules/local_bitcell_array.py
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@ -213,8 +213,8 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
self.add_layout_pin_segment_center(text=wl_name,
layer="m3",
start=vector(0, y_offset),
end=vector(self.width, y_offset))
start=vector(self.wl_insts[port].lx(), y_offset),
end=vector(self.wl_insts[port].lx() + self.wl_array.width, y_offset))
mid = vector(in_pin.cx(), y_offset)
self.add_path("m2", [in_pin.center(), mid])