mirror of https://github.com/VLSIDA/OpenRAM.git
Fix wire width bug in short jogs. PEP8 cleanup.
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0941ebc3da
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@ -74,7 +74,7 @@ class design(hierarchy_design):
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return pitch
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def setup_drc_constants(self):
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"""
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"""
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These are some DRC constants used in many places
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in the compiler.
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"""
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@ -6,18 +6,18 @@
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# All rights reserved.
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#
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from tech import drc
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import debug
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from wire_path import wire_path
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from sram_factory import factory
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class wire(wire_path):
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"""
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"""
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Object metal wire; given the layer type
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Add a wire of minimium metal width between a set of points.
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Add a wire of minimium metal width between a set of points.
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The points should be rectilinear to control the bend points. If
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not, it will always go down first.
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The points are the center of the wire.
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The layer stack is the vertical, contact/via, and horizontal layers, respectively.
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The layer stack is the vertical, contact/via, and horizontal layers, respectively.
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"""
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def __init__(self, obj, layer_stack, position_list):
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self.obj = obj
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@ -36,6 +36,7 @@ class wire(wire_path):
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# wires and wire_paths should not be offset to (0,0)
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def setup_layers(self):
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(horiz_layer, via_layer, vert_layer) = self.layer_stack
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self.via_layer_name = via_layer
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@ -47,8 +48,16 @@ class wire(wire_path):
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via_connect = factory.create(module_type="contact",
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layer_stack=self.layer_stack,
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dimensions=(1, 1))
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# This is used for short connections to avoid via-to-via spacing errors
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self.vert_layer_contact_width = max(via_connect.second_layer_width,
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via_connect.first_layer_width)
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self.horiz_layer_contact_width = max(via_connect.second_layer_height,
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via_connect.first_layer_height)
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self.node_to_node = [drc("minwidth_" + str(self.horiz_layer_name)) + via_connect.width,
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drc("minwidth_" + str(self.horiz_layer_name)) + via_connect.height]
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self.pitch = max(self.node_to_node)
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# create a 1x1 contact
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def create_vias(self):
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@ -56,12 +65,9 @@ class wire(wire_path):
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self.c=factory.create(module_type="contact",
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layer_stack=self.layer_stack,
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dimensions=(1, 1))
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c_width = self.c.width
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c_height = self.c.height
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from itertools import tee,islice
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nwise = lambda g,n=2: zip(*(islice(g,i,None) for i,g in enumerate(tee(g,n))))
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threewise=nwise(self.position_list,3)
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from itertools import tee, islice
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nwise = lambda g, n=2: zip(*(islice(g, i, None) for i, g in enumerate(tee(g, n))))
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threewise = nwise(self.position_list, 3)
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for (a, offset, c) in list(threewise):
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# add a exceptions to prevent a via when we don't change directions
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@ -72,18 +78,23 @@ class wire(wire_path):
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self.obj.add_via_center(layers=self.layer_stack,
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offset=offset)
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def create_rectangles(self):
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"""
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"""
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Create the actual rectangles on the appropriate layers
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using the position list of the corners.
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using the position list of the corners.
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"""
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pl = self.position_list # position list
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for index in range(len(pl) - 1):
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# Horizontal wire segment
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if pl[index][0] != pl[index + 1][0]:
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line_length = pl[index + 1][0] - pl[index][0]
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if abs(line_length) < self.pitch:
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width = self.horiz_layer_contact_width
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else:
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width = self.horiz_layer_width
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temp_offset = [pl[index][0],
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pl[index][1] - 0.5*self.horiz_layer_width]
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pl[index][1] - 0.5 * width]
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# If we go in the negative direction, move the offset
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if line_length < 0:
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temp_offset = [temp_offset[0] + line_length,
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temp_offset[1]]
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@ -91,10 +102,15 @@ class wire(wire_path):
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length=abs(line_length),
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offset=temp_offset,
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orientation="horizontal",
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layer_width=self.horiz_layer_width)
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layer_width=width)
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# Vertical wire segment
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elif pl[index][1] != pl[index + 1][1]:
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line_length = pl[index + 1][1] - pl[index][1]
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temp_offset = [pl[index][0] - 0.5 * self.vert_layer_width,
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if abs(line_length) < self.pitch:
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width = self.vert_layer_contact_width
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else:
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width = self.vert_layer_width
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temp_offset = [pl[index][0] - 0.5 * width,
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pl[index][1]]
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if line_length < 0:
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temp_offset = [temp_offset[0],
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@ -103,11 +119,13 @@ class wire(wire_path):
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length=abs(line_length),
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offset=temp_offset,
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orientation="vertical",
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layer_width=self.vert_layer_width)
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layer_width=width)
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def assert_node(self, A, B):
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""" Check if the node movements are not big enough for the
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technology sizes."""
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"""
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Check if the node movements are not big enough for the
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technology sizes.
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"""
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X_diff = abs(A[0] - B[0])
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Y_diff = abs(A[1] - B[1])
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[minX, minY] = self.node_to_node
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@ -33,7 +33,6 @@ class hierarchical_decoder(design.design):
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except AttributeError:
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self.cell_multiple = 1
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# For debugging
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# self.cell_multiple = 2
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self.cell_height = self.cell_multiple * b.height
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self.num_outputs = num_outputs
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