Remove RBL label at top level of SRAM

compiler/modules/bank.py

@@ -68,7 +68,7 @@ class bank(design.design):
         self.route_layout()
         
         # Can remove the following, but it helps for debug!
-        self.add_lvs_correspondence_points()
+        # self.add_lvs_correspondence_points()
 
         # Remember the bank center for further placement
         self.bank_array_ll = self.offset_all_coordinates().scale(-1, -1)

compiler/sram/sram_1bank.py

@@ -260,6 +260,8 @@ class sram_1bank(sram_base):
             for signal in self.control_logic_inputs[port]:
                 if signal == "clk":
                     continue
+                if signal.startswith("rbl"):
+                    continue
                 if OPTS.perimeter_pins:
                     self.add_perimeter_pin(name=signal + "{}".format(port),
                                            pin=self.control_logic_insts[port].get_pin(signal),
@@ -590,7 +592,7 @@ class sram_1bank(sram_base):
         These should probably be turned off by default though, since extraction
         will show these as ports in the extracted netlist.
         """
-        
+        return
         for n in self.control_logic_outputs[0]:
             pin = self.control_logic_insts[0].get_pin(n)
             self.add_label(text=n,