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879 Commits

Author SHA1 Message Date
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
Bin Wu c9c839ca46 fix the delay measure bug in pex tests 2019-07-10 04:39:40 -07:00
Bin Wu e4070ddad8 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2 2019-07-10 03:09:12 -07:00
jsowash 24bfaa3b76 Added write_size to test 16 and added a newline to Verilog with no wmask for test 25. 2019-07-05 15:55:03 -07:00
jsowash ad9193ad5a Verified 1rw mask writing and changed verilog.py accordingly. 2019-07-05 15:08:59 -07:00
mrg 9dab0be737 Single bank working with replica array. 2019-07-05 13:44:29 -07:00
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
mrg c0f9cdbc12 Create port address module 2019-07-05 09:03:52 -07:00
Matt Guthaus f914ab0ece Re-enable replica tests 2019-07-03 14:57:47 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
mrg 70c83f20b6 Fixes to pass unit tests. 
Skip replica tests until freepdk45 cells are made.
Revert to previous control and row addr dff placement.
 2019-07-03 13:37:56 -07:00
mrg bc4a3ee2b7 New port_data module works in SCMOS 2019-07-03 13:17:12 -07:00
mrg 244604fb0d Data port module working by itself. 2019-07-02 15:35:53 -07:00
Bin Wu 9ce968b446 megre with dev changes 2019-06-30 00:50:18 -07:00
Bin Wu 1fcb20f846 clean pex test based on feedback 2019-06-30 00:16:04 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 04ce3d5f45 Split control logic into different tests to avoid factory errors. 2019-06-25 14:55:28 -07:00
Bin Wu 3f3ee9b885 add pex function for magic and openram test 2019-06-25 11:24:25 -07:00
Bin Wu 91febec3a2 add hspice and ngspice pex tests 2019-06-25 09:19:37 -07:00
Matt d22d7de195 Reapply jsowash update without spice model file 2019-06-24 08:59:58 -07:00
mrg 4523a7b9f6 Replica bitcell array working 2019-06-19 16:03:21 -07:00
Hunter Nichols 2b07db33c8 Added bitcell as input to array, but there are DRC errors now. 2019-06-17 15:31:16 -07:00
mrg d35f180609 Add dummy row 2019-06-14 15:05:14 -07:00
mrg 3c3456596a Add replica row with dummy cells. 2019-06-14 14:38:55 -07:00
mrg b67f06a65a Add replica column for inclusion in replica bitcell array 2019-06-14 12:15:16 -07:00
mrg d8baa5384d Remove useless comments. Add missing copyright. 2019-06-14 10:13:13 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg 7b8c2cac30 Starting single layer power router. 2019-06-03 15:28:55 -07:00
Matt Guthaus 7cca6b4f69 Add back scn3me_subm support 
Add back scn3me_subm tech files
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-06-03 15:27:37 -07:00
mrg d789f93743 Add debug runner during individual tests. 2019-05-31 10:51:42 -07:00
Hunter Nichols 099bc4e258 Added bitcell check to storage nodes. 2019-05-20 18:35:52 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Hunter Nichols a80698918b Fixed test issues, removed all bitcells not relevant for timing graph. 2019-05-15 17:17:26 -07:00
Hunter Nichols 178d3df5f5 Added graph to characterizer to get net names and perform s_en checks. Graph not working with column mux. 2019-05-14 14:44:49 -07:00
Hunter Nichols b30c20ffb5 Added graph creation to characterizer, re-arranged pin creation. 2019-05-14 01:15:50 -07:00
Hunter Nichols b4cce65889 Added incorrect read checking in characterizer. 2019-05-13 19:38:46 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Hunter Nichols 5bfc42fdbb Added quality improvements to graph: improved naming, auto vdd/gnd removal 2019-04-29 23:57:25 -07:00
Matt Guthaus 534c6b36df Use correct back end config file. 2019-04-29 10:20:27 -07:00
Matt Guthaus 8d8565bd9c Add inline_drclvs option for improved coverage 2019-04-29 09:15:46 -07:00
Matt Guthaus 51a97979b9 Add front and back-end test 30. 2019-04-26 15:17:19 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Hunter Nichols f35385f42a Cleaned up names, added exclusions to narrow paths for analysis. 2019-04-24 23:51:09 -07:00
Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules. 2019-04-24 14:23:22 -07:00
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts. 2019-04-03 16:45:01 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Matt Guthaus 74f904a509 Cleanup options for front-end. Improve info output. 2019-04-01 10:35:17 -07:00
Matt Guthaus c3e074c069 Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
Matt Guthaus 0354e2dfb7 Rename config_20 to config since it is used in all tests 2019-03-08 10:47:41 -08:00
Matt Guthaus 196710ec3e Remove factory from lef and verilog tests 2019-03-08 09:22:48 -08:00
Matt Guthaus bd256d33d6 Remove syntax error 2019-03-08 08:35:18 -08:00
Matt Guthaus 7129f79dc4 Merge remote-tracking branch 'origin' into tech_reorg 2019-03-08 08:33:46 -08:00
Matt Guthaus d8f64500e6 Remove factory create from lib tests so that we can give required name 2019-03-08 08:31:26 -08:00
Hunter Nichols 910878ed30 Removed bitline measures until hardcoded signal names are made dynamic 2019-03-07 12:30:27 -08:00
Matt Guthaus 95137a2c26 Wrap debug line 2019-03-06 14:24:24 -08:00
Matt Guthaus 09a429aef7 Update unit tests to all use the sram_factory 2019-03-06 14:12:24 -08:00
Matt Guthaus acf2798a18 Add link to presentation in README 2019-03-06 08:29:43 -08:00
Hunter Nichols ddeb40c9bf Added lib test which generates multiple corner models. Only does process currently. 2019-03-04 16:27:10 -08:00
Hunter Nichols 816669b9ca Merge branch 'dev' into multiport_characterization 2019-02-26 22:48:39 -08:00
Hunter Nichols ea51cfdbb4 Removed data collection script 2019-02-26 22:46:38 -08:00
Hunter Nichols 42bc6efb21 Added additional graphing and data collection to script 2019-02-26 20:06:35 -08:00
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
Matt Guthaus 4da56098e7 Merge branch 'magic_lvs_ports' into dev 2019-02-22 19:02:43 -08:00
Matt Guthaus 599e5457a0 Fix all libs to have pin indices 2019-02-22 17:40:49 -08:00
Matt Guthaus 583dc4410b Revert bus bits back into pins 2019-02-22 16:22:27 -08:00
Matt Guthaus 9459839c06 Clean up output file names for lvs. Update lvs script in magic. 2019-02-22 14:38:00 -08:00
Hunter Nichols 8c1fe253d5 Added variable fanouts to delay testing. 2019-02-13 22:24:58 -08:00
Hunter Nichols 4faec52409 Allowed data collection and analysis to run independently. 2019-02-12 20:58:50 -08:00
Hunter Nichols a4bb481612 Added tracking for available data. 2019-02-12 16:28:37 -08:00
Hunter Nichols 9e23e6584a Made variance plot look slightly better. 2019-02-07 15:30:47 -08:00
Hunter Nichols 5e9851c5f1 Merge branch 'dev' into multiport_characterization 2019-02-07 14:31:26 -08:00
Hunter Nichols ebf43298c0 Added mean/variance plotting 2019-02-07 14:26:48 -08:00
Matt Guthaus d9efb682dd Do not clean up if preserve temp in local_drc_check 2019-02-07 11:08:34 -08:00
Hunter Nichols d0edda93ad Added more variance analysis for the delay data 2019-02-07 02:27:22 -08:00
Hunter Nichols 690055174d Fixed bug in control logic test with port configs. 2019-02-06 20:09:01 -08:00
Hunter Nichols 56e79c050b Changed test values to fix tests. 2019-02-06 15:27:29 -08:00
Hunter Nichols e3d003d410 Adjusted test values to account for recent changes. 2019-02-05 00:43:16 -08:00
Hunter Nichols 12723adb0c Modified some testing and initial delay chain sizes. 2019-02-04 23:38:26 -08:00
Hunter Nichols 8d7823e4dd Added delay ratio comparisons between model and measurements 2019-01-31 00:26:27 -08:00
Hunter Nichols 45fceb1f4e Added word per row to sram config with a default arguement to fix test. 2019-01-30 11:43:47 -08:00
Hunter Nichols d1218778b1 Fixed merge conflicts 2019-01-28 22:33:08 -08:00
Matt Guthaus f84dc3cadc Fix hspice delay golden results 2019-01-28 10:39:09 -08:00
Matt Guthaus d77bba3af2 Fix clock fanout to include internal FF. Update delays in golden tests. 2019-01-28 08:48:32 -08:00
Matt Guthaus 09d6a63861 Change path to wire_path for Anaconda package conflict 2019-01-25 15:07:56 -08:00
Matt Guthaus 8f56953af0 Convert wordline driver to use sized pdriver 2019-01-24 10:20:23 -08:00
Hunter Nichols ee03b4ecb8 Added some data variation checking 2019-01-24 09:25:09 -08:00
Hunter Nichols d527b7da62 Added delay error calculations 2019-01-23 13:19:35 -08:00
Matt Guthaus b58fd03083 Change pbuf/pinv to pdriver in control logic. 2019-01-23 12:03:52 -08:00
Hunter Nichols 6d3884d60d Added corner data collection. 2019-01-22 16:40:46 -08:00
Matt Guthaus 23718b952f Check for print statements in more files since we now use print_raw 2019-01-18 10:16:55 -08:00
Hunter Nichols 5885e3b635 Removed carriage returns, adjusted signal names generation for variable delay chain size. 2019-01-18 00:23:50 -08:00
Hunter Nichols 4ced6be6bd Added data collection and some initial data 2019-01-17 09:54:34 -08:00
Hunter Nichols 5bbc43d0a0 Added data collection of wordline and s_en measurements. 2019-01-17 01:59:41 -08:00
Matt Guthaus 9ecfaf16ea Add the factory class 2019-01-16 17:04:28 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Hunter Nichols cc0be510c7 Added some data scaling and error calculation in model check. 2019-01-16 00:46:24 -08:00
Hunter Nichols 6152ec7ec5 Merge branch 'dev' into multiport_characterization 2019-01-15 16:33:39 -08:00
Matt Guthaus e210ef2a41 Add assert to lef and verilog unit test. Fix verilog files in golden results. 2019-01-11 16:42:50 -08:00
Matt Guthaus a7dd62b0e5 falling_edge not negative_edge 2019-01-11 15:17:27 -08:00
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
Matt Guthaus 49d0b9d69c Remove old scn3me golden results. Remove indices from new golden results. 2019-01-09 12:04:17 -08:00
Matt Guthaus 4d0a8b9c8a Check for coverage executable and run without if not found. 2019-01-09 08:24:20 -08:00
Hunter Nichols 272267358f Moved all bitline delay measurements to delay class. Added measurements to check delay model. 2019-01-03 05:51:28 -08:00
Hunter Nichols dc20bf9e11 Added bitline measurements to ngspice delay test. 2018-12-13 22:31:08 -08:00
Hunter Nichols e4065929c2 Added bitline threshold delay checks to delay tests. 2018-12-13 22:21:30 -08:00
Jennifer Eve Sowash 4a5c18b6cc Removed line to skip pdriver_test 2018-12-13 19:10:38 -08:00
Hunter Nichols 0510aeb3ec Merged with dev, removed commented out code. 2018-12-12 16:02:16 -08:00
Hunter Nichols 0a26e40022 Attempts to fix failing tests. Random seed differences between mada and pipeline. 2018-12-12 13:12:26 -08:00
Hunter Nichols 6ac474d642 Added bitline measures with hardcoded names. 2018-12-12 00:43:08 -08:00
Jennifer Eve Sowash a51aacfa90 Added corner case for 1 inv pos polarity and renamed variables. 2018-12-07 19:42:11 -08:00
Jesse Cirimelli-Low 3d9203a7ea Merge branch 'dev' into datasheet_gen 2018-12-07 04:29:07 -08:00
Matt Guthaus 5319107afa Skip pdriver test until LVS fix 2018-12-07 07:41:35 -08:00
Jennifer Eve Sowash 653ab3eda4 Changed method of determining number of inverters. 2018-12-06 19:34:19 -08:00
Jennifer Eve Sowash 8ea85e3e65 Merge branch 'dev' into pdriver 2018-12-06 14:38:08 -08:00
Jennifer Eve Sowash 5e19cf1e24 Updated naming, added compute_sizes(), and fixed sizing function. 2018-12-06 14:36:01 -08:00
Matt Guthaus 46d3068821 Output number of words per row before SRAM creation. Recompute words per row in unit tests. 2018-12-06 13:11:47 -08:00
Jesse Cirimelli-Low 02b4b13cc4 fixed config file path 2018-12-06 09:26:38 -08:00
Jesse Cirimelli-Low e41b90449d specify config file abs path 2018-12-06 05:34:05 -08:00
Hunter Nichols b157fc58a1 Moved feasible period search from functional.py to tests. 2018-12-05 23:23:40 -08:00
Hunter Nichols 448e8f4cfd Merged with dev 2018-12-05 17:49:42 -08:00
Hunter Nichols ea55bda493 Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
Hunter Nichols 0c3c58011b Fixed delay test values. 2018-12-05 00:13:23 -08:00
Matt Guthaus f1c74d6bfb Merge branch 'dev' into supply_routing 2018-12-04 17:57:18 -08:00
Matt Guthaus e750d446dc Fix syntax error. Enable skipped test. 2018-12-04 17:08:22 -08:00
Jesse Cirimelli-Low b6e7ddd023 Merge branch 'dev' into datasheet_gen 2018-12-04 16:27:04 -08:00
Matt Guthaus 2a68b57215 Changed psram info to sram 2018-12-03 15:59:31 -08:00
Jesse Cirimelli-Low 2c12ef2161 added warning to test 30 coverage is not installed 2018-12-03 13:24:22 -08:00
Jennifer Eve Sowash 2534a32e20 pdriver.py passes resgression tests. Size and number of inverters has been added. 2018-12-03 12:55:48 -08:00
Jesse Cirimelli-Low 71bb1bb9f1 updated test 30 to dev version 2018-12-03 11:09:45 -08:00
Jesse Cirimelli-Low 9501b99df7 merged branch wtih dev 2018-12-03 09:47:34 -08:00
Matt Guthaus bcc6b95564 Add coverage exclusions. Add subprocess coverage. 2018-12-03 09:13:57 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 49f7022416 Skip failing tests with comments for bugs. 2018-11-30 12:33:43 -08:00
Matt Guthaus 0af4263edb Remove extra rotated vias in bitcell array to simplify power routing 2018-11-29 18:13:15 -08:00
Matt Guthaus 0e7301fff8 Update unit test golden results. Skip two tests. 2018-11-29 17:28:57 -08:00
Matt Guthaus 0a16d83181 Add more layout and functional port tests. 2018-11-29 10:28:43 -08:00
Matt Guthaus 14fa33e21d Remove 4 bank code and test for now. 2018-11-29 10:28:09 -08:00
Matt Guthaus 25611fcbc1 Remove dff_inv since we can just use dff_buf 2018-11-28 10:42:22 -08:00
Jesse Cirimelli-Low 5aa8c46c16 Merge branch 'dev' into datasheet_gen 2018-11-27 13:54:21 -08:00
Matt Guthaus 8fba32ca12 Add pand2 draft 2018-11-26 13:45:22 -08:00
Jennifer Eve Sowash 524334d24d Merge branch 'dev' into pdriver 2018-11-26 13:15:47 -08:00
Jennifer Eve Sowash bb7773ca7f Editted pbuf.py to pass regression. 2018-11-20 14:39:11 -08:00
Hunter Nichols 67977bab3e Fixed port issue in bank. Changed golden data due to netlist change. 2018-11-20 11:39:14 -08:00
Jesse Cirimelli-Low 1942ef33ac Merge branch 'dev' into datasheet_gen 2018-11-20 11:23:42 -08:00
Hunter Nichols 62cbbca852 Merged, fixed conflict bt matching control logic creation to dev. 2018-11-19 22:20:20 -08:00
Hunter Nichols 8257e4fe8c Changed syntax in replica_bl tests, golden data to fit new values in delay tests. 2018-11-19 16:51:43 -08:00
Matt Guthaus b89c011e41 Add psram 1w/1r test. Fix bl/br port naming errors in bank. 2018-11-16 15:31:22 -08:00
Jennifer Eve Sowash c73004de35 Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver 2018-11-15 14:06:38 -08:00
Jesse Cirimelli-Low 59c0421804 merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py 2018-11-15 10:45:33 -08:00
Matt Guthaus 3221d3e744 Add initial support and unit tests for 2 port SRAM 2018-11-14 17:05:23 -08:00
Matt Guthaus 6ac5adaeca Separate multiport replica bitline from regular replica bitline test 2018-11-14 11:41:09 -08:00
Matt Guthaus bc7e74f571 Add multiport bank test 2018-11-13 16:06:21 -08:00
Jennifer Sowash b6f1409fb9 Testing to ensure branch is up to date with dev. Added 04_pbuf_test.py and made changes to pbuf.py to align with comments. 2018-11-12 13:24:27 -08:00
Matt Guthaus 5cbbd5e4ca Comment out regress CI debug code 2018-11-10 13:44:36 -08:00
Matt Guthaus 6c17734712 Add testutil archive on failed tests for debug 2018-11-10 11:54:28 -08:00
Jesse Cirimelli-Low 62f8d26ec6 Merge branch 'dev' into datasheet_gen 2018-11-10 10:58:35 -08:00
Matt Guthaus 65b6bfd5e7 Change os to shutils 2018-11-10 10:06:33 -08:00
Matt Guthaus 3b6b93e2ca Save gds file in testutils when fail to figure out randomness in regression CI 2018-11-10 10:05:27 -08:00
Matt Guthaus 550d5cc729 Fix path to config file in test 30 2018-11-09 16:33:08 -08:00
Matt Guthaus cc619084c7 Clean up psingle_bank_test 2018-11-09 09:34:34 -08:00
Matt Guthaus 21f5fb0870 precharge bl is on metal2 only. simplify via position code. 2018-11-09 09:11:00 -08:00
Matt Guthaus 5d684b02e0 Leakage changed in ngspice test. 2018-11-08 18:00:09 -08:00
Matt Guthaus b25650eb07 Netlist only mode for ngspice delay test 2018-11-08 12:19:06 -08:00
Matt Guthaus dd5b2a5b59 Fix missing fail when non-list item doesn't match. 2018-11-08 12:16:59 -08:00
Matt Guthaus 4e232c49ad Update precharge cell for multiport. 
Comment out pbitcell tests.
Add bitcell_1rw_1r test.
Move bitcell horizontal routing to metal1.
Extend precharge height for stacking.
 2018-11-07 14:46:51 -08:00
Matt Guthaus 2e5ae70391 Enable psram 1rw 2mux layout test. 2018-11-07 13:37:08 -08:00
Matt Guthaus 1fe767343e Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
Jesse Cirimelli-Low 781bd13cc1 Merge branch 'dev' into datasheet_gen 2018-11-07 10:08:45 -08:00
Hunter Nichols 4c26dede23 Unskipped functional tests and increases the number of ports on pbitcell functional tests. 2018-11-05 14:56:22 -08:00
Hunter Nichols 9744bc516a Merge branch 'dev' into multiport_characterization 2018-11-05 10:40:29 -08:00
Matt Guthaus ce94366a1d Skip all 4mux and 8mux tests until we solve teh simulation timing bug. 2018-11-05 09:50:44 -08:00
Matt Guthaus 38dab77bfc Add fixed seed to functional test during unit tests. Skip non-working tests after fixed seed. 2018-11-03 10:53:09 -07:00
Matt Guthaus 5d2df76ef5 Skip 4mux test 2018-11-03 10:16:22 -07:00
Hunter Nichols 7461f2b1bf Merged with dev. 2018-11-02 17:22:09 -07:00
Matt Guthaus 6dd959b638 Fix error in 8mux test. Fix comment in all tests. 2018-11-02 16:34:26 -07:00
Matt Guthaus ac203d987c Merge branch 'supply_routing' into dev 2018-11-02 11:50:46 -07:00
Hunter Nichols 642dc8517c Added no mux functional test for 1rw+1r. Delay characterization also works for the custom cell as well. 2018-11-01 14:05:55 -07:00
Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos. 2018-11-01 12:29:49 -07:00
Matt Guthaus 673027ac8c Moved assert to check out_path earlier. 
Preserve temporary output directory with -d option.
 2018-10-31 09:37:47 -07:00
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. 2018-10-31 00:06:34 -07:00
Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass. 2018-10-30 22:19:26 -07:00
Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Matt Guthaus 3f17679000 Merge remote-tracking branch 'origin' into supply_routing 2018-10-25 09:36:03 -07:00
Matt Guthaus 3d8aeaa732 Run delay and setup/hold tests in netlist_only mode 2018-10-25 09:07:00 -07:00
Matt Guthaus 58de655aac Split functional tests 2018-10-25 08:56:23 -07:00
Michael Timothy Grimes 40450ac0f5 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-25 00:36:46 -07:00
Michael Timothy Grimes ceab1a5daf Adding debug comments to stim file for functional test and cleaning up comment code in simulation.py. Adding multiple tests for different mux configurations to functional unit tests. 2018-10-25 00:11:00 -07:00
Matt Guthaus b1f3bd97e5 Enable all the 1bank tests. Mostly work in SCMOS. 2018-10-24 17:01:00 -07:00
Hunter Nichols a711a5823d Merged dev and fix conflicts in geometry.py 2018-10-24 10:52:22 -07:00
Matt Guthaus 33c716eda8 Rename psram bank test like sram bank testss 2018-10-24 09:08:54 -07:00
Hunter Nichols 5c8a00ea1d Fixed pruned golden lib file from error in last commit. 2018-10-24 00:55:55 -07:00
Hunter Nichols da1b003d10 Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 00:17:08 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols 53cb4e7f5e Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Michael Timothy Grimes cda2e93cd7 Adding fix to netlist_only mode in geometry.py. Uncommenting functional tests and running both tests in netlist_only mode. 2018-10-22 09:17:03 -07:00
Matt Guthaus e48e12e8cd Skip non-working 1bank tests for now. 2018-10-20 14:55:11 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Michael Timothy Grimes d6a9ea48ac Working out bugs in psram functional test for SCMOS. Commenting out for now. 2018-10-17 07:45:24 -07:00
Michael Timothy Grimes a27cdb4fbc Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-17 07:32:03 -07:00
Matt Guthaus e2cfd382b9 Fix print check regression 2018-10-15 13:23:31 -07:00
Matt Guthaus d60986e590 Don't skip grid format checks 2018-10-15 11:21:07 -07:00
Matt Guthaus 1c426aad29 Merge remote-tracking branch 'origin/datasheet_gen' into supply_routing 2018-10-12 20:55:57 -07:00
Jesse Cirimelli-Low afba54a22d added analytical model support, added proper output with sram.py 2018-10-12 13:22:12 -07:00
Michael Timothy Grimes d1701b8a2a Removing extra functional test and changing name to a more general form. Spice exe can just be selected from the command line with -s. 2018-10-12 06:29:59 -07:00
Jesse Cirimelli-Low cfb5921d98 reorganized code structure 2018-10-11 15:59:06 -07:00
Jesse Cirimelli-Low bc54bc238f removed tabs and fixed bug in which datasheets generated without the characterizer running 2018-10-11 11:18:40 -07:00
Matt Guthaus e759c9350b Skip psram 1 bank 2018-10-11 10:17:50 -07:00
Matt Guthaus 3f2b7b837d Skip multibank for now too 2018-10-10 16:57:42 -07:00
Matt Guthaus 22b5010734 Skip pmulti which has LVS fail 2018-10-10 16:01:55 -07:00
Matt Guthaus 96d3cacb9c Skip func tests that are failing 2018-10-10 16:00:21 -07:00
Matt Guthaus 13e83e0f1a Separate 1bank tests 2018-10-10 15:58:00 -07:00
Matt Guthaus 6bbf66d55b Rewrote pin enclosure code to better address off grid pins. 
Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.
 2018-10-10 15:15:58 -07:00
Hunter Nichols 3ac2d29940 Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation 2018-10-09 17:44:28 -07:00
Hunter Nichols a3bec5518c Put worst case test under the hierarchy of a delay test. Added option for pex option to worst case test. 2018-10-09 00:36:14 -07:00
Hunter Nichols fd806077d2 Added class and test for testing the delay of several bitcells. 2018-10-08 15:50:52 -07:00
Matt Guthaus a2b1d025ab Merge multiport 2018-10-08 11:45:50 -07:00
Michael Timothy Grimes 6ef1a3c755 Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail. 2018-10-08 06:34:36 -07:00
Jesse Cirimelli-Low fa979e2d34 initial stages of html documentation generation 2018-10-06 21:15:54 -07:00
Matt Guthaus 06dc910390 Route supply after moving origin 2018-10-06 14:03:00 -07:00
Hunter Nichols 7b4e001885 Altered web to only be generated for rw ports. 2018-10-04 15:08:12 -07:00
Hunter Nichols 371a57339f Fixed bugs to allow characterization of multiple read ports. Improved some debug messages. 2018-10-04 14:09:09 -07:00
Hunter Nichols 65edc70cfd Made global names for pins types. Fixed bugs in tests. 2018-10-04 14:06:43 -07:00
Hunter Nichols 4586ed343f Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay. 2018-10-04 14:04:08 -07:00
Michael Timothy Grimes e258199fa3 Removing we_b signal from write ports since it is redundant. 2018-10-04 09:31:04 -07:00
Michael Timothy Grimes 34d8a19871 Adding simulation.py for common functions between functional and delay tests. Updating functional test. 2018-10-04 09:29:44 -07:00
Michael Timothy Grimes bea6b0b5dc Renaming functional tests to include spice exe used. Renaming pex test to separate functional tests from pex test. 2018-09-30 22:39:37 -07:00
Michael Timothy Grimes 6d83ebf50f updating debug messages in functional test 2018-09-30 22:10:11 -07:00
Michael Timothy Grimes 8a56dd2ac9 Finished functional test 2018-09-30 21:20:01 -07:00
Michael Timothy Grimes 26c6232564 Updating functional test. Test can now run a spice simulation and read the dout values from the timing files. 2018-09-28 23:38:48 -07:00
Michael Timothy Grimes 66933ed922 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-27 02:02:24 -07:00
Michael Timothy Grimes 19d68f613e Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport. 2018-09-27 02:01:32 -07:00
Michael Timothy Grimes 648e57d195 Altering bank select for port specific use. Altering bank select test to test different port types. Altering bank for control signal changes. 2018-09-26 14:53:55 -07:00
Michael Timothy Grimes f1560375fc Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport 2018-09-25 20:00:25 -07:00
Matt Guthaus a3f13d6eab Remove banks from test configs 2018-09-24 11:41:51 -07:00
Michael Timothy Grimes 934959952b Corrections to functional test that adds multiple cs_b signals per port 2018-09-21 09:59:44 -07:00
Michael Timothy Grimes 938ded3dd6 Adding functional test to characterizer and unit tests in both single and multiport 2018-09-20 15:04:59 -07:00
Michael Timothy Grimes fc5f163828 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
Matt Guthaus a58b1906ad Convert unit tests to scn4m_subm 
Also, fixed isdiff for python3.
 2018-09-17 11:13:46 -07:00
Michael Timothy Grimes 9acc8a9532 Altering multiport checks across several unit tests. 2018-09-13 18:49:20 -07:00
Michael Timothy Grimes 5fd484ee5a Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode. 2018-09-13 16:53:24 -07:00
Matt Guthaus 93ae7ebd00 Specify DRC,LVS,PEX tool for scn4m 2018-09-13 15:18:30 -07:00
Matt Guthaus 4d328c5768 Fix hspice setuphold golden results 2018-09-13 14:41:15 -07:00
Matt Guthaus 63d0523228 Added scn4m_subm. 
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
 2018-09-13 12:53:35 -07:00
Matt Guthaus 3539887ee4 Updating ms_flop removal. 
Updated characterizer for dff.
Added new setup/hold results for dff instead of ms_flop.
Removed ms_flop references in sram-base.
Fixed syntax errors in SCN3ME tech file.
 2018-09-13 11:40:24 -07:00
Matt Guthaus 66cbe0966c Removed old ms_flop unit test 2018-09-13 11:15:33 -07:00
Michael Timothy Grimes e0b9989d85 Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate. 2018-09-13 01:42:06 -07:00
Michael Timothy Grimes f03cd7c3ba Removing multiport_check option that diabled multiport portion of unit tests. Adding multiport checks to several other modules. 2018-09-12 20:22:12 -07:00
Michael Timothy Grimes 42719b8ec2 Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check. 2018-09-12 01:53:41 -07:00
Michael Timothy Grimes bfc855b8b1 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-11 17:33:17 -07:00
Hunter Nichols da6843af5b Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done. 2018-09-10 19:33:59 -07:00
Michael Timothy Grimes 38a1f35ff0 Correcting format of file (removing tabs) 2018-09-10 03:44:08 -07:00
Michael Timothy Grimes a7f03858e8 Adding 'multiport_check' option to OPTS. All of the unit tests that have multiport checks in them are now under this conditional. If you want to remove the multiport drc/lvs checks, you can set the option to False, and it will skip those portions. 2018-09-09 23:25:29 -07:00
Michael Timothy Grimes 5af56e5a3a Adding layout check for sram (1 bank) using pbitcell and 1RW port 2018-09-09 22:45:25 -07:00
Michael Timothy Grimes 586c72e4f7 Altering certain tests to include multiport checks. 2018-09-09 22:08:03 -07:00
Michael Timothy Grimes 1429b9ab1a Commiting working version of multi-port that can generate a netlist on the sram level. Changes that will clean up the code are forthcoming. 2018-09-09 14:00:51 -07:00
Hunter Nichols 8aaf1155d1 Fixed test 23_lib_sram_test. Fixed syntax in related golden lib files. 2018-09-06 22:51:34 -07:00
Hunter Nichols 0ff3b29b66 Fixed test 23_sram_prune test. Fixed syntax errors in golden lib files. 2018-09-06 22:06:23 -07:00
Michael Timothy Grimes 1a340c9c85 Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell. 2018-09-06 19:36:50 -07:00
Hunter Nichols bf34911f3f Test 21_ngspice now passing for scmos and freepdk45. 21_hspice has leakage power error (but it may be okay) 2018-09-06 18:40:21 -07:00
Hunter Nichols 1615de05e4 Fixed leakage power issue in test 21_hspice. Still requires more testing. 2018-09-06 18:26:08 -07:00
Hunter Nichols a2bc82fe71 Fixed test 21_hspice. Leakage power is off. 2018-09-06 17:34:22 -07:00
Hunter Nichols dd22f9acd5 Fixed issues with analytical sram test. Changed syntax errors in golden lib file. 2018-09-06 17:01:10 -07:00
Matt Guthaus ba651d53ae Change options in pbitcell test to be global again. 2018-09-05 10:59:41 -07:00
Matt Guthaus 6963a1092f Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00
Matt Guthaus de6f22aa3c Fix unit test permissions 2018-09-04 10:48:37 -07:00
Matt Guthaus 19c0e1638b Merge remote-tracking branch 'origin/multiport' into multiport 2018-09-04 10:47:55 -07:00
Matt Guthaus a346bddd88 Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
Michael Timothy Grimes af0756382f Merging changes and updating multiport syntax across several tests 2018-09-03 19:36:20 -07:00
Michael Timothy Grimes 774c14ad75 changing 19_psingle_bank_test to test layout for a single bank using pbitcell with 1 RW port (equivalent to using 6T cell) 2018-09-03 17:47:29 -07:00
Michael Timothy Grimes d3441c7ba4 Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers 2018-09-03 17:31:12 -07:00
Michael Timothy Grimes f3cca7eea0 Altering sense amp array and write driver array so spacing between amps/drivers accomodates multiport. Also altering sense amp array and write driver array tests to include multiport cases. 2018-08-31 23:28:06 -07:00
Matt Guthaus 9d8d2b65e4 Fix delay test with new sram_config. Merge dev changes. 2018-08-31 13:01:17 -07:00
Matt Guthaus 563ff77d44 Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
Michael Timothy Grimes e118cc2d5c Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-29 16:06:50 -07:00
Michael Timothy Grimes aeaab13d28 Unit tests for pbitcell now passing, so commenting out skip line. Also gave pbitcell_array useful names in unit test for easier debugging 2018-08-29 16:05:13 -07:00
Matt Guthaus 27bb1d2ee7 Rewrite blockage routines in router. Clean up GdsMill code. 2018-08-29 15:34:45 -07:00
Matt Guthaus 19d14e39ce Remove extraneous files 2018-08-29 15:34:45 -07:00
Matt Guthaus 41fba9d27c Add sketch for power grid routing code 2018-08-29 15:34:16 -07:00
Matt Guthaus 8752d799b4 Skip pbitcell tests for now 2018-08-28 10:45:50 -07:00
Matt Guthaus ac8a16ebdf Fix permissions for unit tests to be run standalone. 2018-08-28 10:31:58 -07:00
Matt Guthaus e17c69be3e Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
Michael Timothy Grimes 0f8da1510e Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines. 2018-08-18 15:27:07 -07:00
Michael Timothy Grimes e147f807a5 adding a unit test for multiported bank, this test will skip in the regression testing because multiported bank does not pass drc yet 2018-08-15 04:32:56 -07:00
Michael Timothy Grimes e4a94e8597 Merging changes to bank. Bank has been altered to accommodate multiport. Single port still passes unit test, though some control signal names have been changed to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can accurately generate a spice netlist. 2018-08-15 04:00:48 -07:00
Michael Timothy Grimes e592d95146 Altered bank to accommodate multiport. Single port still works, though some of the control signal names have been changes to have a following 0 (e.g. s_en to s_en0). Multiport does not pass drc yet, but can generate an accurate spice netlist. 2018-08-15 03:36:40 -07:00
Michael Timothy Grimes a5af4a2b9c resolved variable name error in 00_code_format test 2018-08-15 03:33:33 -07:00
Michael Timothy Grimes 8d97862f6e altered precharge array and precharge unit tests to accommodate multiport 2018-08-15 00:55:23 -07:00
Matt Guthaus 36bfd2932a Update delay results with new clock routing 2018-08-14 10:51:02 -07:00
Matt Guthaus 3420b1002c Connect data and column DFF clocks in 1 bank. 2018-08-14 10:09:41 -07:00
Matt Guthaus f7f318d72e Remove tri_en signals from bank control logic. 2018-08-13 14:47:03 -07:00
Matt Guthaus 49bee6a96e Remove OEB signal since we split DIN/DOUT ports 2018-08-13 14:09:49 -07:00
Matt Guthaus 9ffba4b052 Add +x permissions on precharge and pbitcell tests 2018-08-13 09:57:10 -07:00
Matt Guthaus 34736b7b3f Remove carriage returns form python files 2018-08-07 09:44:01 -07:00
Matt Guthaus abacf6a2d0 Add carriage return check for python files 2018-08-07 09:40:45 -07:00
Michael Timothy Grimes c2a9e91dba Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-05 19:53:28 -07:00
Michael Timothy Grimes 5666ee6635 altered precharge module to accomodate bitlines from pbitcell, and altered unit test to test both bitcell and pbitcell configurations 2018-08-05 19:46:05 -07:00
Michael Timothy Grimes ecd4612167 altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions 2018-08-05 19:43:59 -07:00
Matt Guthaus d739c17b8d Fix delay numbers in hspice delay unit test. 2018-07-27 14:43:52 -07:00
Matt Guthaus d75d17bc8a Update golden results for FreePDK45 tests. 2018-07-27 14:25:52 -07:00
Matt Guthaus 71606e1097 Add read cycle to clear DOUT bus before each read measure. 2018-07-27 14:06:59 -07:00
Matt Guthaus 5b2cb6a95e Update remaining SCMOS golden lib files. 2018-07-27 09:44:12 -07:00
Matt Guthaus 6b967c08dd Updated output messages in timing test comparisons. 
Added output to show which lines differ and what their line numbers are..
Added output to show relative difference of approximate compares.
Added output to include file names that mismatch.
 2018-07-27 09:34:44 -07:00
Matt Guthaus 0e0516c4a6 Fix delay test unit test results. 2018-07-26 16:45:09 -07:00
Matt Guthaus 85595b0f6f Update format of delay test output during an error to directly 
copy into unit test. Factor function into testutils.py for comparison.
 2018-07-26 16:05:24 -07:00
Matt Guthaus 5088487cf7 Update delay tests to output useful information for debug. 2018-07-26 15:45:17 -07:00
Matt Guthaus f098b995f0 Fix pinvbuf test to use new interface with only driver size. 2018-07-26 14:20:00 -07:00
Matt Guthaus c8808c268a Close output log in test 30 to avoid warning 2018-07-26 14:01:40 -07:00
Michael Timothy Grimes fb0de710ec Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-07-26 09:04:59 -07:00
Michael Timothy Grimes 27ab411146 fixed error I missed in pbitcell_array test 2018-07-26 09:02:52 -07:00
Matt Guthaus b88947ef5c Pass the sram design to lib instead of the sram wrapper 2018-07-18 11:51:42 -07:00
Matt Guthaus 1130062343 Fix syntax error in delay test to use new sram wrapper module 2018-07-18 10:33:18 -07:00
Matt Guthaus b8e3629923 Fix syntax error in unit test 2018-07-17 15:14:22 -07:00
Matt Guthaus 01655b1d54 Clean up tests. Enable 8-way tests. Some tests still have channel route conflicts. 2018-07-17 15:13:00 -07:00
Matt Guthaus f3ae29fe0b Getting single bank to work reliably. Removed tri_gate from bank 
for now. Will add it in multibank arrays only. Not needed for
separate DIN and DOUT ports.
 2018-07-13 14:45:46 -07:00
Matt Guthaus 834fbac8de Remove extra print statements. 
Add wrappers for file generation in sram wrapper class.
 2018-07-13 09:38:43 -07:00
Michael Timothy Grimes 2388ddbfb0 deleting code added in error to pbitcell_array_test during previous commit 2018-07-12 23:55:54 -07:00
Michael Timothy Grimes ba43b986ae merging changes with pbitcell_array test 2018-07-12 23:51:44 -07:00
Michael Timothy Grimes a64ca423c6 changing pbitcell_array test to include an important permutation of the design 2018-07-12 23:45:47 -07:00
Matt Guthaus c71ea51e2e Merge branch 'multiport_cleanup' of github.com:VLSIDA/PrivateRAM into multiport_cleanup 2018-07-11 14:27:41 -07:00
Matt Guthaus 22d40364ec Merge branch 'multiport_cleanup' of https://github.com/VLSIDA/PrivateRAM into multiport_cleanup 2018-07-11 14:27:06 -07:00
Matt Guthaus 33bb98894f Disable LEF test until supplies fixed. 2018-07-11 14:18:53 -07:00
Matt Guthaus 8be88d14a7 Disable banner output during gitlab runner 2018-07-11 14:18:36 -07:00
Matt Guthaus 8a530da2cc Remove extra conversion to list 2018-07-11 12:07:37 -07:00
Matt Guthaus 265b5d977a Fix option reload problems and checkpointing so that it works properly. 2018-07-11 12:00:15 -07:00
Matt Guthaus 58646ab8e6 Add DRC/LVS/PEX statistics in verbose=1 mode 2018-07-11 11:59:24 -07:00
Matt Guthaus f894ef47af Fix missing list conversion to run drc library tests. 2018-07-11 11:58:22 -07:00
Matt Guthaus b3732f4fcf Output debug warnings and errors to stderr. Clean up regress script a bit. 2018-07-11 09:51:28 -07:00
Matt Guthaus f82591dd6f Remove outdated README 2018-07-11 09:12:20 -07:00
Matt Guthaus c6503dd771 Modify unit tests to reset options during init_openram so 
that they don't use old parameters after a failure.
 2018-07-10 16:39:32 -07:00
Matt Guthaus 19c53cd50c Do not fail assertion in exception code. 2018-07-10 14:16:18 -07:00
Matt Guthaus 019512bc25 Fix python3 module reference in functional test 2018-07-09 16:07:53 -07:00
Matt Guthaus f234e43241 Reset new hierarchy_design instead of design for duplicate GDS name checker 2018-07-09 16:07:30 -07:00
Matt Guthaus bbc98097ac Add getpass include to unit test 30 2018-07-09 15:53:37 -07:00
Matt Guthaus 7bf271fd63 Skip pex and functional tests which are not working. 2018-07-09 15:52:07 -07:00
Matt Guthaus 5cf62e82cf Merge branch 'dev' into multiport_cleanup 2018-07-09 09:58:13 -07:00
Matt Guthaus a9a95ebf7c Fix pex test permissions 2018-07-09 09:11:14 -07:00
Matt Guthaus 5d32a426c4 Change test sram path so jobs can be simultaneously run. 2018-07-06 07:34:38 -07:00
Matt Guthaus 733be110a2 Add negation to return code so tests fail or pass properly. 2018-07-06 07:27:26 -07:00
Matt Guthaus 3260468477 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2018-07-05 16:27:49 -07:00
Matt Guthaus 077f3f20ec Add return code for regression test 2018-07-05 16:27:47 -07:00
Matt Guthaus 99fe3b87fe Remove temp file. Fixing indexing of sense amp outputs. 2018-06-29 15:22:58 -07:00
Matt Guthaus 6ac24dbf0c Fix module name for python3 2018-06-29 15:12:15 -07:00
Matt Guthaus 8d61ccbc6f Convert byte string to string. 2018-06-29 15:11:14 -07:00
Matt Guthaus 6cd1779f7b Rename pex test so that it ends with _test and will be run by regress.py. 2018-06-29 12:47:22 -07:00
Matt Guthaus 32099646cf Add back fix to revert bitcell from pbitcell. 2018-06-29 12:45:26 -07:00
Matt Guthaus a9849eff3a Merge in mtgrime's fix. 2018-06-29 12:44:26 -07:00
Michael Timothy Grimes 82eeb297dd Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-06-29 12:07:03 -07:00
Michael Timothy Grimes 721f935d66 changing pbitcell tests to revert OPTS.bitcell to bitcell after tests 2018-06-29 12:00:36 -07:00
Matt Guthaus ac7aa4537c Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell. 2018-06-29 11:49:02 -07:00
Matt Guthaus fa17d5e7f3 Change permissions of tests to be executable so you don't have to type python each time. 2018-06-29 11:36:30 -07:00
Matt Guthaus 3becf92e7c Combine pbitcell tests into one unit test 2018-06-29 10:00:23 -07:00
Matt Guthaus df2dce2439 Fix module import names for python3. Rename parse function to something meaningful. 2018-06-29 09:45:07 -07:00
Michael Timothy Grimes d7a024b8fc adding another important port combination to unit tests 2018-06-03 19:36:48 -07:00
Michael Timothy Grimes e19a422696 simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations 2018-05-31 17:39:51 -07:00
Michael Timothy Grimes 8f131ddb2f commiting changes from most recent pull from dev 2018-05-22 17:30:51 -07:00
Michael Timothy Grimes b5df0cc30a Merging branch with PrivateRAM dev 2018-05-18 15:15:31 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus b14bef3bcf Initial merge of incomplete multi-port clean with new supply routing. 2018-05-11 08:18:04 -07:00
Michael Timothy Grimes 3971835f24 changed pbitcell_array tests in regards to addition of read/write ports in pbitcell 2018-05-10 09:40:43 -07:00
Michael Timothy Grimes 7af95e4723 adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports. 2018-05-10 09:38:02 -07:00
Matt Guthaus 7b5791b0e9 Change tolerance of tests to a big value. Update tests. 2018-05-09 08:29:23 -07:00
Matt Guthaus 929122b6dc Change default to scmos. Refactor add column mux. 2018-04-20 12:52:41 -07:00
Matt Guthaus a6c2e77bcf Move precharge and column mux cells to pgate directory. 
Move gnd to M3 in column mux.
Create column mux cell unit test.
 2018-04-06 17:15:14 -07:00
Michael Timothy Grimes 7f46a0dead merging changes in bitcell.py 2018-04-03 09:46:12 -07:00
Matt Guthaus 696433b1ec Add bank_sel to bank_select module as input. 
Remove reference to control in sram.
Add dff_buf_array to options.
Added inverted DFF
Add variable height pinvbuf
 2018-03-23 08:13:39 -07:00
Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works. 2018-03-23 08:13:20 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Michael Timothy Grimes 65735c08e2 fixed bitcell_array to work with different sized pbitcells, changed sizing in pbitcell to minimize space between inverters 2018-03-08 16:39:26 -08:00
Michael Timothy Grimes 820a8440c9 adding unit test for bitcell array using pbitcell 2018-03-06 16:36:11 -08:00
Matt Guthaus 6e9437356a Fix LEF tests with new power supplies. 2018-03-05 13:55:02 -08:00
Matt Guthaus 98fb1173df Move bank select logic to a self contained module. 2018-03-05 10:22:51 -08:00
Matt Guthaus 8d9b79dfd8 Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
mguthaus 04ed3792c7 Fix analytical lib tests with new power numbers. 2018-03-02 18:13:06 -08:00
Michael Timothy Grimes 4d3f01ff2f The bitcell currently passes DRC and LVS for FreePDK45 and SCMOS 
There are 2 benchtests for the bitcell:
1) one with 2 write ports and 2 read ports
2) one with 2 write ports and 0 read ports
The second test is meant to show how the bitcell functions when read/write ports are
used instead of separate ports for read and write
The bitcell currently passes both tests in both technologies
Certain sizing optimizations still need to be done on the bitcell
 2018-02-28 11:14:53 -08:00
Michael Timothy Grimes bf7d846e5f Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-02-28 04:29:38 -08:00
Matt Guthaus a732405836 Add utility script gen_stimulus.py to help create simulations for debugging. 2018-02-26 08:54:35 -08:00
mguthaus f3efb5fb50 Fixed leakage and power unit test results. 2018-02-23 15:20:52 -08:00
Matt Guthaus e3e7a31c6b Fix syntax error in functional test. 2018-02-23 07:47:01 -08:00
mguthaus fbc2d772be Fix index order of golden tests. 2018-02-21 19:37:10 -08:00
mguthaus a22badeeb5 Fix pruned results 2018-02-21 17:48:46 -08:00
Matt Guthaus cf5f1e94b9 Update hspice results 2018-02-21 16:12:20 -08:00
Matt Guthaus 4e414b6c15 Fix unintended unmerge of changes. Bad bad. 2018-02-21 16:03:49 -08:00
Matt Guthaus a44346110b Fix merge of results. 2018-02-21 15:47:07 -08:00
Matt Guthaus fcacd46866 UPdate tests with new delay and slew names and leakage power. 2018-02-21 15:45:49 -08:00
mguthaus b8b2375346 Updated golden tests with new leakage aware power numbers. 2018-02-21 15:44:52 -08:00
Michael Timothy Grimes 4ea2a70a1b removing unnecessary unit test for pbitcell 2018-02-19 10:58:08 -08:00
mguthaus 5e8dff1e90 Fix unit tests with newest RBL delays. Fix tech problem with new spice models. 2018-02-16 13:54:05 -08:00
mguthaus c1c1ba38a3 Fix unit test to have fanout. 2018-02-16 11:53:38 -08:00
Matt Guthaus 9559421ca8 Connect dff array clk in rows and columns. 2018-02-14 16:46:26 -08:00
Matt Guthaus 2d87dcda46 dff array done except for clock net 2018-02-14 16:03:29 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
mguthaus 767990ca3b Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
Matt Guthaus a12ebeed9f Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken. 2018-02-12 09:33:23 -08:00
mguthaus 1795dc5677 Fix three unit tests to work with new lib corner files. 2018-02-11 20:43:41 -08:00