mirror of https://github.com/VLSIDA/OpenRAM.git
Fix hspice delay golden results
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@ -64,16 +64,16 @@ class timing_sram_test(openram_test):
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'write0_power': [0.40809259999999997],
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'write1_power': [0.4078904]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl': [1.3911],
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'delay_lh': [1.3911],
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'leakage_power': 0.0278488,
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'min_period': 2.812,
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'read0_power': [22.1183],
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'read1_power': [21.4388],
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'slew_hl': [0.7397553],
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'slew_lh': [0.7397553],
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'write0_power': [19.4103],
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'write1_power': [20.1167]}
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golden_data = {'delay_hl': [1.4333000000000002],
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'delay_lh': [1.4333000000000002],
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'leakage_power': 0.0271847,
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'min_period': 2.891,
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'read0_power': [15.714200000000002],
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'read1_power': [14.9848],
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'slew_hl': [0.6819276999999999],
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'slew_lh': [0.6819276999999999],
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'write0_power': [13.9658],
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'write1_power': [14.8422]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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