mirror of https://github.com/VLSIDA/OpenRAM.git
fix the delay measure bug in pex tests
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e4070ddad8
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@ -24,8 +24,13 @@ class hspice_pex_pinv_test(openram_test):
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import pinv
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# load the hspice
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OPTS.spice_name = "hspice"
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OPTS.spice_exe = "hspice"
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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# generate the pinv
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prev_purge_value = OPTS.purge_temp
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@ -111,7 +116,8 @@ class hspice_pex_pinv_test(openram_test):
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trig_name = "input",
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targ_name = "output",
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trig_dir_str = "FALL",
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targ_dir_str = "RISE")
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targ_dir_str = "RISE",
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has_port = False)
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trig_td = trag_td = 0.01 * run_time
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rest_info = trig_td,trag_td,tech.spice["nom_supply_voltage"]
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delay_measure.write_measure(simulation, rest_info)
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@ -22,9 +22,14 @@ class ngspice_pex_pinv_test(openram_test):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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import pinv
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# load the hspice
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OPTS.spice_name = "ngspice"
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OPTS.spice_exe = "ngspice"
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# load the ngspice
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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# generate the pinv module
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prev_purge_value = OPTS.purge_temp
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@ -114,7 +119,8 @@ class ngspice_pex_pinv_test(openram_test):
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trig_name = "input",
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targ_name = "output",
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trig_dir_str = "FALL",
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targ_dir_str = "RISE")
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targ_dir_str = "RISE",
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has_port = False)
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trig_td = trag_td = 0.01 * run_time
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rest_info = trig_td,trag_td,tech.spice["nom_supply_voltage"]
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delay_measure.write_measure(simulation, rest_info)
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