mirror of https://github.com/VLSIDA/OpenRAM.git
clean pex test based on feedback
This commit is contained in:
Bin Wu
parent
8e5fa7c7ae
commit
1fcb20f846
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@ -21,43 +21,40 @@ class hspice_pex_pinv_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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import pinv
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# generate the pinv module
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OPTS.purge_temp = False
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debug.info(2, "Checking 1x size inverter")
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tx = pinv.pinv(name="pinv", size=1)
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self.local_check(tx)
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# generate its pex file
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pex_file = self.run_pex(tx)
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OPTS.purge_temp = True
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OPTS.analytical_delay = False
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# load the hspice
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OPTS.spice_name = "hspice"
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OPTS.spice_exe = "hspice"
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import os
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from characterizer import charutils
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from charutils import parse_spice_list
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# setup simulation
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sim_file = OPTS.openram_temp + "stim.sp"
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log_file_name = "timing"
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# make sure that the library simulation is successful
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# generate the pinv
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prev_purge_value = OPTS.purge_temp
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OPTS.purge_temp = False # force set purge to false to save the sp file
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debug.info(2, "Checking 1x size inverter")
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tx = pinv.pinv(name="pinv", size=1)
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tempgds = "{0}{1}.gds".format(OPTS.openram_temp,tx.name)
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tx.gds_write(tempgds)
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tempsp = "{0}{1}.sp".format(OPTS.openram_temp,tx.name)
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self.write_simulaton(sim_file, tempsp, tx.name)
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sp_delay = parse_spice_list(log_file_name, "pinv_delay")
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assert sp_delay is not "Failed"
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tx.sp_write(tempsp)
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# make sure that the library simulation is successful\
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sp_delay = self.simulate_delay(test_module = tempsp,
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top_level_name = tx.name)
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if sp_delay is "Failed":
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self.fail('Library Spice module did not behave as expected')
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# now generate its pex file
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pex_file = self.run_pex(tx)
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OPTS.purge_temp = prev_purge_value # restore the old purge value
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# generate simulation for pex, make sure the simulation is successful
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self.write_simulaton(sim_file, pex_file, tx.name)
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pex_delay = parse_spice_list(log_file_name, "pinv_delay")
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pex_delay = self.simulate_delay(test_module = pex_file,
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top_level_name = tx.name)
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# make sure the extracted spice simulated
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assert pex_delay is not "Failed"
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if pex_delay is "Failed":
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self.fail('Pex file did not behave as expected')
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# if pex data is bigger than original spice file then result is ok
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# actually this may not always be true depending on the netlist provided
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# However this may not always be true depending on the netlist provided
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# comment out for now
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#debug.info(2,"pex_delay: {0}".format(pex_delay))
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#debug.info(2,"sp_delay: {0}".format(sp_delay))
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@ -67,35 +64,46 @@ class hspice_pex_pinv_test(openram_test):
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globals.end_openram()
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def write_simulaton(self, sim_file, cir_file, top_module_name):
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def simulate_delay(self, test_module, top_level_name):
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from characterizer import charutils
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from charutils import parse_spice_list
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# setup simulation
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sim_file = OPTS.openram_temp + "stim.sp"
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log_file_name = "timing"
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test_sim = self.write_simulation(sim_file, test_module, top_level_name)
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test_sim.run_sim()
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delay = parse_spice_list(log_file_name, "pinv_delay")
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return delay
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def write_simulation(self, sim_file, cir_file, top_module_name):
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""" write pex spice simulation for a pinv test"""
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import tech
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from characterizer import measurements, stimuli
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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sim_file = open(sim_file, "w")
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simulaton = stimuli(sim_file,corner)
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simulation = stimuli(sim_file,corner)
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# library files
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simulaton.write_include(cir_file)
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simulation.write_include(cir_file)
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# supply voltages
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simulaton.gen_constant(sig_name ="vdd",
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v_val = tech.spice["nom_supply_voltage"])
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simulaton.gen_constant(sig_name = "gnd",
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v_val = "0v")
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simulation.gen_constant(sig_name ="vdd",
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v_val = tech.spice["nom_supply_voltage"])
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simulation.gen_constant(sig_name = "gnd",
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v_val = "0v")
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run_time = tech.spice["feasible_period"] * 2
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run_time = tech.spice["feasible_period"] * 4
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# input voltage
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simulaton.gen_pwl(sig_name ="input",
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clk_times = [1,1],
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data_values = [1,0],
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period=1e9,
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slew=0.000002,
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setup=0)
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clk_period = tech.spice["feasible_period"]
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simulation.gen_pwl(sig_name ="input",
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clk_times = [clk_period,clk_period],
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data_values = [1,0],
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period = clk_period,
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slew = 0.001*tech.spice["feasible_period"],
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setup = 0)
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# instantiation of simulated pinv
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simulaton.inst_model(pins = ["input", "output", "vdd", "gnd"],
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simulation.inst_model(pins = ["input", "output", "vdd", "gnd"],
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model_name = top_module_name)
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# delay measurement
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@ -106,11 +114,11 @@ class hspice_pex_pinv_test(openram_test):
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targ_dir_str = "RISE")
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trig_td = trag_td = 0.01 * run_time
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rest_info = trig_td,trag_td,tech.spice["nom_supply_voltage"]
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delay_measure.write_measure(simulaton, rest_info)
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delay_measure.write_measure(simulation, rest_info)
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simulaton.write_control(end_time = run_time)
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simulation.write_control(end_time = run_time)
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sim_file.close()
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simulaton.run_sim()
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return simulation
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# run the test from the command line
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@ -18,46 +18,42 @@ import debug
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class ngspice_pex_pinv_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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import pinv
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# generate the pinv module
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OPTS.purge_temp = False
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debug.info(2, "Checking 1x size inverter")
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tx = pinv.pinv(name="pinv", size=1)
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self.local_check(tx)
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# generate its pex file
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pex_file = self.run_pex(tx)
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OPTS.purge_temp = True
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OPTS.analytical_delay = False
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# load the ngspice
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# load the hspice
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OPTS.spice_name = "ngspice"
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OPTS.spice_exe = "ngspice"
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import os
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from characterizer import charutils
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from charutils import parse_spice_list
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# setup simulaton
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sim_file = OPTS.openram_temp + "stim.sp"
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log_file_name = "timing"
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# generate the pinv module
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prev_purge_value = OPTS.purge_temp
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OPTS.purge_temp = False # force set purge to false to save the sp file
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debug.info(2, "Checking 1x size inverter")
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tx = pinv.pinv(name="pinv", size=1)
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tempgds = "{0}{1}.gds".format(OPTS.openram_temp,tx.name)
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tx.gds_write(tempgds)
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tempsp = "{0}{1}.sp".format(OPTS.openram_temp,tx.name)
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tx.sp_write(tempsp)
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# make sure that the library simulation is successful
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tempsp = "{0}{1}.sp".format(OPTS.openram_temp,tx.name)
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self.write_simulaton(sim_file, tempsp, tx.name)
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sp_delay = parse_spice_list(log_file_name, "pinv_delay")
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assert sp_delay is not "Failed"
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sp_delay = self.simulate_delay(test_module = tempsp,
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top_level_name = tx.name)
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if sp_delay is "Failed":
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self.fail('Library Spice module did not behave as expected')
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# now generate its pex file
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pex_file = self.run_pex(tx)
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OPTS.purge_temp = prev_purge_value # restore the old purge value
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# generate simulation for pex, make sure the simulation is successful
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self.write_simulaton(sim_file, pex_file, tx.name)
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pex_delay = parse_spice_list(log_file_name, "pinv_delay")
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pex_delay = self.simulate_delay(test_module = pex_file,
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top_level_name = tx.name)
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# make sure the extracted spice simulated
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assert pex_delay is not "Failed"
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if pex_delay is "Failed":
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self.fail('Pex file did not behave as expected')
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# if pex data is bigger than original spice file then result is ok
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# actually this may not always be true depending on the netlist provided
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# However this may not always be true depending on the netlist provided
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# comment out for now
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#debug.info(2,"pex_delay: {0}".format(pex_delay))
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#debug.info(2,"sp_delay: {0}".format(sp_delay))
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@ -67,38 +63,50 @@ class ngspice_pex_pinv_test(openram_test):
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globals.end_openram()
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def write_simulaton(self, sim_file, cir_file, top_module_name):
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def simulate_delay(self, test_module, top_level_name):
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from characterizer import charutils
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from charutils import parse_spice_list
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# setup simulation
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sim_file = OPTS.openram_temp + "stim.sp"
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log_file_name = "timing"
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test_sim = self.write_simulation(sim_file, test_module, top_level_name)
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test_sim.run_sim()
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delay = parse_spice_list(log_file_name, "pinv_delay")
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return delay
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def write_simulation(self, sim_file, cir_file, top_module_name):
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""" write pex spice simulation for a pinv test"""
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import tech
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from characterizer import measurements, stimuli
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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sim_file = open(sim_file, "w")
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simulaton = stimuli(sim_file,corner)
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simulation = stimuli(sim_file,corner)
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# library files
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simulaton.write_include(cir_file)
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simulation.write_include(cir_file)
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# supply voltages
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simulaton.gen_constant(sig_name ="vdd",
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simulation.gen_constant(sig_name ="vdd",
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v_val = tech.spice["nom_supply_voltage"])
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# The scn4m_subm and ngspice combination will have a gnd source error:
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# "Fatal error: instance vgnd is a shorted VSRC"
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# However, remove gnd power for all techa pass for this test
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# simulaton.gen_constant(sig_name = "gnd",
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# simulation.gen_constant(sig_name = "gnd",
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# v_val = "0v")
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run_time = tech.spice["feasible_period"] * 2
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run_time = tech.spice["feasible_period"] * 4
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# input voltage
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simulaton.gen_pwl(sig_name ="input",
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clk_times = [1,1],
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clk_period = tech.spice["feasible_period"]
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simulation.gen_pwl(sig_name ="input",
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clk_times = [clk_period,clk_period],
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data_values = [1,0],
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period=1e9,
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slew=0.000002,
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setup=0)
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period = clk_period,
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slew = 0.001*tech.spice["feasible_period"],
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setup = 0)
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# instantiation of simulated pinv
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simulaton.inst_model(pins = ["input", "output", "vdd", "gnd"],
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simulation.inst_model(pins = ["input", "output", "vdd", "gnd"],
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model_name = top_module_name)
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# delay measurement
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@ -109,12 +117,11 @@ class ngspice_pex_pinv_test(openram_test):
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targ_dir_str = "RISE")
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trig_td = trag_td = 0.01 * run_time
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rest_info = trig_td,trag_td,tech.spice["nom_supply_voltage"]
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delay_measure.write_measure(simulaton, rest_info)
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delay_measure.write_measure(simulation, rest_info)
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simulaton.write_control(end_time = run_time)
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simulation.write_control(end_time = run_time)
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sim_file.close()
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simulaton.run_sim()
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return simulation
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# run the test from the command line
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if __name__ == "__main__":
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