mirror of https://github.com/VLSIDA/OpenRAM.git
Added lib test which generates multiple corner models. Only does process currently.
This commit is contained in:
Hunter Nichols
parent
7e67b741f6
commit
ddeb40c9bf
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@ -483,17 +483,16 @@ class lib:
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self.lib.write(" }\n")
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def compute_delay(self):
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""" Do the analysis if we haven't characterized the SRAM yet """
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if not hasattr(self,"d"):
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self.d = delay(self.sram, self.sp_file, self.corner)
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if self.use_model:
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char_results = self.d.analytical_delay(self.slews,self.loads)
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self.char_sram_results, self.char_port_results = char_results
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else:
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probe_address = "1" * self.sram.addr_size
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probe_data = self.sram.word_size - 1
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char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
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self.char_sram_results, self.char_port_results = char_results
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"""Compute SRAM delays for current corner"""
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self.d = delay(self.sram, self.sp_file, self.corner)
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if self.use_model:
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char_results = self.d.analytical_delay(self.slews,self.loads)
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self.char_sram_results, self.char_port_results = char_results
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else:
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probe_address = "1" * self.sram.addr_size
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probe_data = self.sram.word_size - 1
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char_results = self.d.analyze(probe_address, probe_data, self.slews, self.loads)
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self.char_sram_results, self.char_port_results = char_results
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def compute_setup_hold(self):
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""" Do the analysis if we haven't characterized a FF yet """
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@ -0,0 +1,69 @@
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#!/usr/bin/env python3
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"""
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Check the .lib file for an SRAM
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os,re
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class model_corners_lib_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from characterizer import lib
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=2,
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num_words=16,
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num_banks=1)
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c.words_per_row=1
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c.recompute_sizes()
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debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank")
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s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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#Set the corners. Lib will create a power set of the lists.
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if OPTS.tech_name == "scn4m_subm":
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OPTS.process_corners = ["TT", "SS", "FF"]
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OPTS.supply_voltages = [5.0]
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OPTS.temperatures = [25]
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elif OPTS.tech_name == "freepdk45":
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OPTS.process_corners = ["TT", "SS", "FF"]
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OPTS.supply_voltages = [1.0]
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OPTS.temperatures = [25]
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lib(out_dir=OPTS.openram_temp, sram=s.s, sp_file=tempspice, use_model=True)
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# get all of the .lib files generated
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files = os.listdir(OPTS.openram_temp)
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nametest = re.compile("\.lib$", re.IGNORECASE)
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lib_files = filter(nametest.search, files)
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# and compare them with the golden model
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for filename in lib_files:
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newname = filename.replace(".lib","_analytical.lib")
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libname = "{0}/{1}".format(OPTS.openram_temp,filename)
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
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self.assertTrue(self.isapproxdiff(libname,golden,0.15))
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@ -0,0 +1,321 @@
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library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){
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delay_model : "table_lookup";
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time_unit : "1ns" ;
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voltage_unit : "1v" ;
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current_unit : "1mA" ;
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resistance_unit : "1kohm" ;
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capacitive_load_unit(1 ,fF) ;
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leakage_power_unit : "1mW" ;
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(OC){
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process : 1.0 ;
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voltage : 1.0 ;
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temperature : 25;
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}
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input_threshold_pct_fall : 50.0 ;
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output_threshold_pct_fall : 50.0 ;
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input_threshold_pct_rise : 50.0 ;
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output_threshold_pct_rise : 50.0 ;
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slew_lower_threshold_pct_fall : 10.0 ;
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slew_upper_threshold_pct_fall : 90.0 ;
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slew_lower_threshold_pct_rise : 10.0 ;
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slew_upper_threshold_pct_rise : 90.0 ;
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nom_voltage : 1.0;
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nom_temperature : 25;
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nom_process : 1.0;
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default_cell_leakage_power : 0.0 ;
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default_leakage_power_density : 0.0 ;
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default_input_pin_cap : 1.0 ;
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default_inout_pin_cap : 1.0 ;
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default_output_pin_cap : 0.0 ;
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default_max_transition : 0.5 ;
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default_fanout_load : 1.0 ;
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default_max_fanout : 4.0 ;
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default_connection_class : universal ;
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lu_table_template(CELL_TABLE){
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variable_1 : input_net_transition;
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variable_2 : total_output_net_capacitance;
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index_1("0.00125, 0.005, 0.04");
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index_2("0.052275, 0.2091, 1.6728");
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}
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lu_table_template(CONSTRAINT_TABLE){
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variable_1 : related_pin_transition;
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variable_2 : constrained_pin_transition;
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index_1("0.00125, 0.005, 0.04");
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index_2("0.00125, 0.005, 0.04");
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}
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default_operating_conditions : OC;
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type (DATA){
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base_type : array;
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data_type : bit;
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bit_width : 2;
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bit_from : 0;
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bit_to : 1;
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}
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type (ADDR){
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base_type : array;
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data_type : bit;
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bit_width : 4;
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bit_from : 0;
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bit_to : 3;
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}
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cell (sram_2_16_1_freepdk45){
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memory(){
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type : ram;
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address_width : 4;
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word_width : 2;
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}
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interface_timing : true;
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dont_use : true;
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map_only : true;
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dont_touch : true;
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area : 1124.88;
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leakage_power () {
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when : "CSb0";
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value : 0.000167;
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}
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cell_leakage_power : 0;
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bus(DIN0){
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bus_type : DATA;
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direction : input;
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capacitance : 0.2091;
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memory_write(){
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address : ADDR0;
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clocked_on : clk0;
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}
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pin(DIN0[1:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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}
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bus(DOUT0){
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bus_type : DATA;
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direction : output;
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max_capacitance : 1.6728;
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min_capacitance : 0.052275;
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memory_read(){
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address : ADDR0;
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}
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pin(DOUT0[1:0]){
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timing(){
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timing_sense : non_unate;
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related_pin : "clk0";
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timing_type : falling_edge;
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cell_rise(CELL_TABLE) {
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values("0.088, 0.088, 0.088",\
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"0.088, 0.088, 0.088",\
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"0.088, 0.088, 0.088");
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}
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cell_fall(CELL_TABLE) {
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values("0.088, 0.088, 0.088",\
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"0.088, 0.088, 0.088",\
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"0.088, 0.088, 0.088");
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}
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rise_transition(CELL_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_transition(CELL_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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}
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bus(ADDR0){
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bus_type : ADDR;
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direction : input;
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capacitance : 0.2091;
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max_transition : 0.04;
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pin(ADDR0[3:0]){
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timing(){
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timing_type : setup_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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}
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pin(CSb0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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pin(WEb0){
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direction : input;
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capacitance : 0.2091;
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timing(){
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timing_type : setup_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009",\
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"0.009, 0.009, 0.009");
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}
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}
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timing(){
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timing_type : hold_rising;
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related_pin : "clk0";
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rise_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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fall_constraint(CONSTRAINT_TABLE) {
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values("0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001",\
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"0.001, 0.001, 0.001");
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}
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}
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}
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pin(clk0){
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clock : true;
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direction : input;
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capacitance : 0.2091;
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internal_power(){
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when : "!CSb0 & clk0 & !WEb0";
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rise_power(scalar){
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values("0.033101244168888884");
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}
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fall_power(scalar){
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values("0.033101244168888884");
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}
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}
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internal_power(){
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when : "!CSb0 & !clk0 & WEb0";
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rise_power(scalar){
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values("0.033101244168888884");
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}
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fall_power(scalar){
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values("0.033101244168888884");
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}
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}
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internal_power(){
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when : "CSb0";
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rise_power(scalar){
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values("0");
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}
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fall_power(scalar){
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values("0");
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}
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}
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timing(){
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timing_type :"min_pulse_width";
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related_pin : clk0;
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rise_constraint(scalar) {
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values("0.009");
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}
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fall_constraint(scalar) {
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values("0.009");
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}
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}
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timing(){
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timing_type :"minimum_period";
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related_pin : clk0;
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rise_constraint(scalar) {
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values("0.018");
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}
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fall_constraint(scalar) {
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values("0.018");
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}
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}
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}
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}
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}
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@ -0,0 +1,321 @@
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library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){
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delay_model : "table_lookup";
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time_unit : "1ns" ;
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voltage_unit : "1v" ;
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current_unit : "1mA" ;
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resistance_unit : "1kohm" ;
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capacitive_load_unit(1 ,fF) ;
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leakage_power_unit : "1mW" ;
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pulling_resistance_unit :"1kohm" ;
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operating_conditions(OC){
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process : 1.0 ;
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voltage : 1.0 ;
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temperature : 25;
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}
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input_threshold_pct_fall : 50.0 ;
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output_threshold_pct_fall : 50.0 ;
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input_threshold_pct_rise : 50.0 ;
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output_threshold_pct_rise : 50.0 ;
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slew_lower_threshold_pct_fall : 10.0 ;
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slew_upper_threshold_pct_fall : 90.0 ;
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slew_lower_threshold_pct_rise : 10.0 ;
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slew_upper_threshold_pct_rise : 90.0 ;
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nom_voltage : 1.0;
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nom_temperature : 25;
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nom_process : 1.0;
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default_cell_leakage_power : 0.0 ;
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default_leakage_power_density : 0.0 ;
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default_input_pin_cap : 1.0 ;
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default_inout_pin_cap : 1.0 ;
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default_output_pin_cap : 0.0 ;
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default_max_transition : 0.5 ;
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default_fanout_load : 1.0 ;
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default_max_fanout : 4.0 ;
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default_connection_class : universal ;
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lu_table_template(CELL_TABLE){
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variable_1 : input_net_transition;
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variable_2 : total_output_net_capacitance;
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index_1("0.00125, 0.005, 0.04");
|
||||
index_2("0.052275, 0.2091, 1.6728");
|
||||
}
|
||||
|
||||
lu_table_template(CONSTRAINT_TABLE){
|
||||
variable_1 : related_pin_transition;
|
||||
variable_2 : constrained_pin_transition;
|
||||
index_1("0.00125, 0.005, 0.04");
|
||||
index_2("0.00125, 0.005, 0.04");
|
||||
}
|
||||
|
||||
default_operating_conditions : OC;
|
||||
|
||||
|
||||
type (DATA){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 2;
|
||||
bit_from : 0;
|
||||
bit_to : 1;
|
||||
}
|
||||
|
||||
type (ADDR){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 4;
|
||||
bit_from : 0;
|
||||
bit_to : 3;
|
||||
}
|
||||
|
||||
cell (sram_2_16_1_freepdk45){
|
||||
memory(){
|
||||
type : ram;
|
||||
address_width : 4;
|
||||
word_width : 2;
|
||||
}
|
||||
interface_timing : true;
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 1124.88;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.000167;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 1.6728;
|
||||
min_capacitance : 0.052275;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk0";
|
||||
timing_type : falling_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.107, 0.107, 0.107",\
|
||||
"0.107, 0.107, 0.107",\
|
||||
"0.107, 0.107, 0.107");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.107, 0.107, 0.107",\
|
||||
"0.107, 0.107, 0.107",\
|
||||
"0.107, 0.107, 0.107");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
max_transition : 0.04;
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 0.2091;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.033101244168888884");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.033101244168888884");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("0.033101244168888884");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0.033101244168888884");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0105");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0105");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.021");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.021");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,321 @@
|
|||
library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(OC){
|
||||
process : 1.0 ;
|
||||
voltage : 5.0 ;
|
||||
temperature : 25;
|
||||
}
|
||||
|
||||
input_threshold_pct_fall : 50.0 ;
|
||||
output_threshold_pct_fall : 50.0 ;
|
||||
input_threshold_pct_rise : 50.0 ;
|
||||
output_threshold_pct_rise : 50.0 ;
|
||||
slew_lower_threshold_pct_fall : 10.0 ;
|
||||
slew_upper_threshold_pct_fall : 90.0 ;
|
||||
slew_lower_threshold_pct_rise : 10.0 ;
|
||||
slew_upper_threshold_pct_rise : 90.0 ;
|
||||
|
||||
nom_voltage : 5.0;
|
||||
nom_temperature : 25;
|
||||
nom_process : 1.0;
|
||||
default_cell_leakage_power : 0.0 ;
|
||||
default_leakage_power_density : 0.0 ;
|
||||
default_input_pin_cap : 1.0 ;
|
||||
default_inout_pin_cap : 1.0 ;
|
||||
default_output_pin_cap : 0.0 ;
|
||||
default_max_transition : 0.5 ;
|
||||
default_fanout_load : 1.0 ;
|
||||
default_max_fanout : 4.0 ;
|
||||
default_connection_class : universal ;
|
||||
|
||||
lu_table_template(CELL_TABLE){
|
||||
variable_1 : input_net_transition;
|
||||
variable_2 : total_output_net_capacitance;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("2.45605, 9.8242, 78.5936");
|
||||
}
|
||||
|
||||
lu_table_template(CONSTRAINT_TABLE){
|
||||
variable_1 : related_pin_transition;
|
||||
variable_2 : constrained_pin_transition;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("0.0125, 0.05, 0.4");
|
||||
}
|
||||
|
||||
default_operating_conditions : OC;
|
||||
|
||||
|
||||
type (DATA){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 2;
|
||||
bit_from : 0;
|
||||
bit_to : 1;
|
||||
}
|
||||
|
||||
type (ADDR){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 4;
|
||||
bit_from : 0;
|
||||
bit_to : 3;
|
||||
}
|
||||
|
||||
cell (sram_2_16_1_scn4m_subm){
|
||||
memory(){
|
||||
type : ram;
|
||||
address_width : 4;
|
||||
word_width : 2;
|
||||
}
|
||||
interface_timing : true;
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 73068.14000000001;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.000167;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk0";
|
||||
timing_type : falling_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.241, 0.241, 0.241",\
|
||||
"0.241, 0.241, 0.241",\
|
||||
"0.241, 0.241, 0.241");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.241, 0.241, 0.241",\
|
||||
"0.241, 0.241, 0.241",\
|
||||
"0.241, 0.241, 0.241");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
max_transition : 0.4;
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.024");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.024");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.048");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.048");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,321 @@
|
|||
library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(OC){
|
||||
process : 1.0 ;
|
||||
voltage : 5.0 ;
|
||||
temperature : 25;
|
||||
}
|
||||
|
||||
input_threshold_pct_fall : 50.0 ;
|
||||
output_threshold_pct_fall : 50.0 ;
|
||||
input_threshold_pct_rise : 50.0 ;
|
||||
output_threshold_pct_rise : 50.0 ;
|
||||
slew_lower_threshold_pct_fall : 10.0 ;
|
||||
slew_upper_threshold_pct_fall : 90.0 ;
|
||||
slew_lower_threshold_pct_rise : 10.0 ;
|
||||
slew_upper_threshold_pct_rise : 90.0 ;
|
||||
|
||||
nom_voltage : 5.0;
|
||||
nom_temperature : 25;
|
||||
nom_process : 1.0;
|
||||
default_cell_leakage_power : 0.0 ;
|
||||
default_leakage_power_density : 0.0 ;
|
||||
default_input_pin_cap : 1.0 ;
|
||||
default_inout_pin_cap : 1.0 ;
|
||||
default_output_pin_cap : 0.0 ;
|
||||
default_max_transition : 0.5 ;
|
||||
default_fanout_load : 1.0 ;
|
||||
default_max_fanout : 4.0 ;
|
||||
default_connection_class : universal ;
|
||||
|
||||
lu_table_template(CELL_TABLE){
|
||||
variable_1 : input_net_transition;
|
||||
variable_2 : total_output_net_capacitance;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("2.45605, 9.8242, 78.5936");
|
||||
}
|
||||
|
||||
lu_table_template(CONSTRAINT_TABLE){
|
||||
variable_1 : related_pin_transition;
|
||||
variable_2 : constrained_pin_transition;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("0.0125, 0.05, 0.4");
|
||||
}
|
||||
|
||||
default_operating_conditions : OC;
|
||||
|
||||
|
||||
type (DATA){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 2;
|
||||
bit_from : 0;
|
||||
bit_to : 1;
|
||||
}
|
||||
|
||||
type (ADDR){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 4;
|
||||
bit_from : 0;
|
||||
bit_to : 3;
|
||||
}
|
||||
|
||||
cell (sram_2_16_1_scn4m_subm){
|
||||
memory(){
|
||||
type : ram;
|
||||
address_width : 4;
|
||||
word_width : 2;
|
||||
}
|
||||
interface_timing : true;
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 73068.14000000001;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.000167;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk0";
|
||||
timing_type : falling_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.294, 0.294, 0.294",\
|
||||
"0.294, 0.294, 0.294",\
|
||||
"0.294, 0.294, 0.294");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.294, 0.294, 0.294",\
|
||||
"0.294, 0.294, 0.294",\
|
||||
"0.294, 0.294, 0.294");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
max_transition : 0.4;
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("4.99880645");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0295");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0295");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.059");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.059");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue