mirror of https://github.com/VLSIDA/OpenRAM.git
Added delay ratio comparisons between model and measurements
This commit is contained in:
Hunter Nichols
parent
45fceb1f4e
commit
8d7823e4dd
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@ -133,6 +133,7 @@ class control_logic(design.design):
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if (self.port_type == "rw") or (self.port_type == "r"):
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from importlib import reload
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self.delay_chain_resized = False
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c = reload(__import__(OPTS.replica_bitline))
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replica_bitline = getattr(c, OPTS.replica_bitline)
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bitcell_loads = int(math.ceil(self.num_rows * parameter["rbl_height_percentage"]))
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@ -141,35 +142,36 @@ class control_logic(design.design):
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delay_stages = parameter["static_delay_stages"]
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delay_fanout = parameter["static_fanout_per_stage"]
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debug.info(1, "Using tech parameters to size delay chain: stages={}, fanout={}".format(delay_stages,delay_fanout))
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self.replica_bitline = replica_bitline("replica_bitline_"+self.port_type,
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[delay_fanout]*delay_stages,
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bitcell_loads)
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self.replica_bitline = factory.create(module_type="replica_bitline",
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delay_fanout_list=[delay_fanout]*delay_stages,
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bitcell_loads=bitcell_loads)
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if self.sram != None: #Calculate model value even for specified sizes
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self.set_sen_wl_delays()
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else: #Otherwise, use a heuristic and/or model based sizing.
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#First use a heuristic
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delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size()
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self.replica_bitline = replica_bitline("replica_bitline_"+self.port_type,
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[delay_fanout_heuristic]*delay_stages_heuristic,
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bitcell_loads)
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self.replica_bitline = factory.create(module_type="replica_bitline",
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delay_fanout_list=[delay_fanout_heuristic]*delay_stages_heuristic,
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bitcell_loads=bitcell_loads)
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if self.sram != None: #Calculate delays for potential re-sizing
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self.set_sen_wl_delays()
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#Resize if necessary, condition depends on resizing method
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if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match():
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#This resizes to match fall and rise delays, can make the delay chain weird sizes.
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# stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
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# self.replica_bitline = replica_bitline( "replica_bitline_resized_"+self.port_type
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# stage_list,
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# bitcell_loads)
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# self.replica_bitline = factory.create(module_type="replica_bitline",
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# delay_fanout_list=stage_list,
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# bitcell_loads=bitcell_loads)
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#This resizes based on total delay.
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delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic)
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self.replica_bitline = replica_bitline("replica_bitline_resized_"+self.port_type,
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[delay_fanout]*delay_stages,
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bitcell_loads)
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self.replica_bitline = factory.create(module_type="replica_bitline",
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delay_fanout_list=[delay_fanout]*delay_stages,
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bitcell_loads=bitcell_loads)
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self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
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self.delay_chain_resized = True
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self.add_mod(self.replica_bitline)
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@ -2,7 +2,8 @@ word_size = 1
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num_words = 16
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tech_name = "freepdk45"
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process_corners = ["TT", "FF", "SS", "SF", "FS"]
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#process_corners = ["TT", "FF", "SS", "SF", "FS"]
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process_corners = ["TT"]
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supply_voltages = [1.0]
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temperatures = [25]
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@ -28,12 +28,16 @@ class data_collection(openram_test):
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self.evaluate_data(wl_dataframe, sae_dataframe)
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#Run again but with different delay chain sizes
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self.init_data_gen()
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self.set_delay_chain(4,2)
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self.save_data_sram_corners(word_size, num_words, words_per_row)
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wl_dataframe, sae_dataframe = self.get_csv_data()
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self.evaluate_data(wl_dataframe, sae_dataframe)
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# self.init_data_gen()
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# self.set_delay_chain(4,2)
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# self.save_data_sram_corners(word_size, num_words, words_per_row)
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# wl_dataframe, sae_dataframe = self.get_csv_data()
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# self.evaluate_data(wl_dataframe, sae_dataframe)
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model_delay_ratios, meas_delay_ratios, ratio_error = self.compare_model_to_measure()
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debug.info(1, "model_delay_ratios={}".format(model_delay_ratios))
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debug.info(1, "meas_delay_ratios={}".format(meas_delay_ratios))
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debug.info(1, "ratio_error={}".format(ratio_error))
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globals.end_openram()
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def get_csv_data(self):
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@ -50,7 +54,36 @@ class data_collection(openram_test):
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debug.info(1, "Delay errors:{}".format(delay_error))
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variation_error = self.calculate_delay_variation_error(wl_dataframe, sae_dataframe)
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debug.info(1, "Variation errors:{}".format(variation_error))
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def compare_model_to_measure(self):
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"""Uses the last 4 recent data sets (wl_meas, sen_meas, wl_model, sen_model)
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and compare the wl-sen delay ratio between model and measured.
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"""
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model_delay_ratios = {}
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meas_delay_ratios = {}
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ratio_error = {}
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#The full file name contains unrelated portions, separate them into the four that are needed
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wl_meas_df = [pd.read_csv(file_name,encoding='utf-8') for file_name in self.file_names if "wl_measures" in file_name][0]
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sae_meas_df = [pd.read_csv(file_name,encoding='utf-8') for file_name in self.file_names if "sae_measures" in file_name][0]
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wl_model_df = [pd.read_csv(file_name,encoding='utf-8') for file_name in self.file_names if "wl_model" in file_name][0]
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sae_model_df = [pd.read_csv(file_name,encoding='utf-8') for file_name in self.file_names if "sae_model" in file_name][0]
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#Assume each csv has the same corners (and the same row order), use one of the dfs for corners
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proc_pos, volt_pos, temp_pos = wl_meas_df.columns.get_loc('process'), wl_meas_df.columns.get_loc('voltage'), wl_meas_df.columns.get_loc('temp')
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wl_sum_pos = wl_meas_df.columns.get_loc('sum')
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sae_sum_pos = sae_meas_df.columns.get_loc('sum')
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df_zip = zip(wl_meas_df.itertuples(),sae_meas_df.itertuples(),wl_model_df.itertuples(),sae_model_df.itertuples())
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for wl_meas,sae_meas,wl_model,sae_model in df_zip:
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#Use previously calculated position to index the df row.
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corner = (wl_meas[proc_pos+1], wl_meas[volt_pos+1], wl_meas[temp_pos+1])
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meas_delay_ratios[corner] = wl_meas[wl_sum_pos+1]/sae_meas[sae_sum_pos+1]
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model_delay_ratios[corner] = wl_model[wl_sum_pos+1]/sae_model[sae_sum_pos+1]
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debug.info(1,"wl_model sum={}, sae_model_sum={}".format(wl_model[wl_sum_pos+1], sae_model[sae_sum_pos+1]))
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ratio_error[corner] = 100*abs(model_delay_ratios[corner]-meas_delay_ratios[corner])/meas_delay_ratios[corner]
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return model_delay_ratios, meas_delay_ratios, ratio_error
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def calculate_delay_error(self, wl_dataframe, sae_dataframe):
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"""Calculates the percentage difference in delays between the wordline and sense amp enable"""
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start_data_pos = len(self.config_fields) #items before this point are configuration related
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@ -94,13 +127,14 @@ class data_collection(openram_test):
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corner_gen = self.corner_combination_generator()
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init_corner = next(corner_gen)
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sram_data = self.get_sram_data(init_corner)
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self.initialize_csv_file(sram_data, word_size, num_words, words_per_row)
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self.add_sram_data_to_csv(sram_data, word_size, num_words, words_per_row, init_corner)
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dc_resized = self.was_delay_chain_resized()
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self.initialize_csv_file(word_size, num_words, words_per_row)
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self.add_sram_data_to_csv(sram_data, word_size, num_words, words_per_row, dc_resized, init_corner)
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#Run openRAM for all corners
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for corner in corner_gen:
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sram_data = self.get_sram_data(corner)
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self.add_sram_data_to_csv(sram_data, word_size, num_words, words_per_row, corner)
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self.add_sram_data_to_csv(sram_data, word_size, num_words, words_per_row, dc_resized, corner)
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self.close_files()
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debug.info(1,"Data Generated")
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@ -133,10 +167,10 @@ class data_collection(openram_test):
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file.close()
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def corner_combination_generator(self):
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"""Generates corner using a combination of values from config file"""
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processes = OPTS.process_corners
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voltages = OPTS.supply_voltages
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temperatures = OPTS.temperatures
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"""Generates corner using a combination of values from config file"""
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for proc in processes:
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for volt in voltages:
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for temp in temperatures:
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@ -154,14 +188,21 @@ class data_collection(openram_test):
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words_per_row = [1]
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return word_sizes, num_words, words_per_row
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def add_sram_data_to_csv(self, sram_data, word_size, num_words, words_per_row, corner):
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"""Writes data to its respective CSV file. There is a CSV for each measurement target (wordline, sense amp enable, and models)"""
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sram_specs = [word_size,num_words,words_per_row,*corner]
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def add_sram_data_to_csv(self, sram_data, word_size, num_words, words_per_row, dc_resized, corner):
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"""Writes data to its respective CSV file. There is a CSV for each measurement target
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(wordline, sense amp enable, and models)"""
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sram_specs = [word_size,num_words,words_per_row,dc_resized,*corner]
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for data_name, data_values in sram_data.items():
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self.csv_writers[data_name].writerow(sram_specs+sram_data[data_name])
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other_values = self.calculate_other_data_values(data_values)
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self.csv_writers[data_name].writerow(sram_specs+sram_data[data_name]+other_values)
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debug.info(2,"Data Added to CSV file.")
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def initialize_csv_file(self, sram_data, word_size, num_words, words_per_row):
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def calculate_other_data_values(self, sram_data_list):
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"""A function to calculate extra values related to the data. Only does the sum for now"""
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data_sum = sum(sram_data_list)
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return [data_sum]
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def initialize_csv_file(self, word_size, num_words, words_per_row):
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"""Opens a CSV file and writer for every data set being written (wl/sae measurements and model values)"""
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#CSV File writing
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header_dict = self.delay_obj.get_all_signal_names()
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@ -178,8 +219,9 @@ class data_collection(openram_test):
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data_name)
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self.file_names.append(file_name)
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self.csv_files[data_name] = open(file_name, 'w')
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self.config_fields = ['word_size', 'num_words', 'words_per_row', 'process', 'voltage', 'temp']
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fields = (*self.config_fields, *header_list)
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self.config_fields = ['word_size', 'num_words', 'words_per_row', 'dc_resized', 'process', 'voltage', 'temp']
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self.other_data_fields = ['sum']
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fields = (*self.config_fields, *header_list, *self.other_data_fields)
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self.csv_writers[data_name] = csv.writer(self.csv_files[data_name], lineterminator = '\n')
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self.csv_writers[data_name].writerow(fields)
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@ -223,6 +265,11 @@ class data_collection(openram_test):
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dict[key] = dict[key][0]
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else:
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del dict[key]
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def was_delay_chain_resized(self):
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"""Accesses the dc resize boolean in the control logic module."""
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#FIXME:assumes read/write port only
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return self.sram.s.control_logic_rw.delay_chain_resized
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# instantiate a copdsay of the class to actually run the test
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if __name__ == "__main__":
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@ -1,6 +1,2 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0
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4,16,1,TT,1.0,25,0.020618,0.0062215,0.018563000000000003,0.017233000000000002,0.007710799999999999,0.0099965,0.045221000000000004
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4,16,1,FF,1.0,25,0.019135,0.0052523000000000005,0.017398,0.015280000000000002,0.0067718,0.009288300000000001,0.042180999999999996
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4,16,1,SS,1.0,25,0.022393999999999997,0.0074892,0.019906,0.019521999999999998,0.0087409,0.010967000000000001,0.04836
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4,16,1,SF,1.0,25,0.01874,0.007554100000000001,0.016919,0.018821,0.0086205,0.0094092,0.049122
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4,16,1,FS,1.0,25,0.022926,0.0046388,0.02054,0.015555000000000001,0.0067794,0.010772,0.041583
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0,sum
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4,16,1,False,TT,1.0,25,0.020618,0.0062215,0.018563000000000003,0.017233000000000002,0.007710799999999999,0.0099965,0.045221000000000004,0.12556380000000003
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@ -1,6 +1,2 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0
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4,16,1,TT,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15
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4,16,1,FF,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15
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4,16,1,SS,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15
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4,16,1,SF,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15
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4,16,1,FS,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0,sum
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4,16,1,False,TT,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15,42.949999999999996
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@ -1,6 +1,2 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,0.010512,0.0089216,0.014109,0.013643,0.014564,0.0086745
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4,16,1,FF,1.0,25,0.0096952,0.008041900000000001,0.013129,0.012268999999999999,0.013255999999999999,0.007759599999999999
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4,16,1,SS,1.0,25,0.011505,0.009873400000000001,0.015371,0.015194000000000001,0.016210000000000002,0.0097529
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4,16,1,SF,1.0,25,0.0097161,0.0096343,0.013210000000000001,0.014750000000000001,0.013464,0.0094366
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4,16,1,FS,1.0,25,0.011368999999999999,0.0082136,0.015231000000000001,0.012545,0.015907,0.0079376
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15,sum
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4,16,1,False,TT,1.0,25,0.010512,0.0089216,0.014109,0.013643,0.014564,0.0086745,0.0704241
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@ -1,6 +1,2 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
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4,16,1,FF,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
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4,16,1,SS,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
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4,16,1,SF,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
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4,16,1,FS,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15,sum
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4,16,1,False,TT,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4,32.13333333333334
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@ -1,6 +1,2 @@
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|||
word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0
|
||||
4,16,1,TT,1.0,25,0.020572,0.006256,0.015678,0.014110000000000001,0.017755,0.013415,0.0076344,0.010162,0.04153
|
||||
4,16,1,FF,1.0,25,0.01907,0.0052328,0.014619000000000002,0.0126,0.016572,0.011862,0.0067348,0.0093334,0.03898
|
||||
4,16,1,SS,1.0,25,0.022189,0.0074532999999999995,0.016968,0.015854,0.019286,0.015139,0.0087264,0.011029,0.04439
|
||||
4,16,1,SF,1.0,25,0.018689,0.007557800000000001,0.014395999999999999,0.015354,0.016425000000000002,0.014665,0.0084936,0.009411300000000001,0.044714000000000004
|
||||
4,16,1,FS,1.0,25,0.022942,0.0046639,0.017356,0.012745999999999999,0.01949,0.012069,0.006808099999999999,0.010822,0.038710999999999995
|
||||
word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0,sum
|
||||
4,16,1,False,TT,1.0,25,0.020572,0.006256,0.015678,0.014110000000000001,0.017755,0.013415,0.0076344,0.010162,0.04153,0.14711239999999998
|
||||
|
|
|
|||
|
|
|
@ -1,6 +1,2 @@
|
|||
word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0
|
||||
4,16,1,TT,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15
|
||||
4,16,1,FF,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15
|
||||
4,16,1,SS,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15
|
||||
4,16,1,SF,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15
|
||||
4,16,1,FS,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15
|
||||
word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0,sum
|
||||
4,16,1,False,TT,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15,51.74999999999999
|
||||
|
|
|
|||
|
|
|
@ -1,6 +1,2 @@
|
|||
word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
|
||||
4,16,1,TT,1.0,25,0.010463,0.0089004,0.014107,0.013630000000000001,0.0146,0.0086902
|
||||
4,16,1,FF,1.0,25,0.0096519,0.008039899999999999,0.013115,0.012295,0.013235,0.0077621
|
||||
4,16,1,SS,1.0,25,0.011424,0.0098775,0.015351999999999998,0.015194000000000001,0.016227,0.0097375
|
||||
4,16,1,SF,1.0,25,0.009697500000000001,0.009592,0.013206,0.014738000000000001,0.013432,0.0094217
|
||||
4,16,1,FS,1.0,25,0.011432000000000001,0.0081985,0.015220000000000001,0.012544,0.015973,0.0079455
|
||||
word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15,sum
|
||||
4,16,1,False,TT,1.0,25,0.010463,0.0089004,0.014107,0.013630000000000001,0.0146,0.0086902,0.0703906
|
||||
|
|
|
|||
|
|
|
@ -1,6 +1,2 @@
|
|||
word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
|
||||
4,16,1,TT,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
|
||||
4,16,1,FF,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
|
||||
4,16,1,SS,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
|
||||
4,16,1,SF,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
|
||||
4,16,1,FS,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
|
||||
word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15,sum
|
||||
4,16,1,False,TT,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4,32.13333333333334
|
||||
|
|
|
|||
|
Loading…
Reference in New Issue