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Update unit tests to all use the sram_factory

This commit is contained in:
Matt Guthaus 2019-03-06 14:12:24 -08:00
parent acf2798a18
commit 09a429aef7
79 changed files with 260 additions and 246 deletions
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2
compiler/modules/control_logic.py
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@ -14,7 +14,7 @@ class control_logic(design.design):
Dynamically generated Control logic for the total SRAM circuit.
"""
def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw"):
def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw", name=""):
""" Constructor """
name = "control_logic_" + port_type
design.design.__init__(self, name)

4
compiler/modules/tri_gate_array.py
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@ -10,9 +10,9 @@ class tri_gate_array(design.design):
Dynamically generated tri gate array of all bitlines. words_per_row
"""
def __init__(self, columns, word_size):
def __init__(self, columns, word_size, name):
"""Intial function of tri gate array """
design.design.__init__(self, "tri_gate_array")
design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name))
self.columns = columns

2
compiler/sram_factory.py
View File

@ -58,7 +58,7 @@ class sram_factory:
(obj_kwargs, obj_item) = obj
# Must have the same dictionary exactly (conservative)
if obj_kwargs == kwargs:
#debug.info(1, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs)))
debug.info(1, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs)))
return obj_item
# Use the default name if there are default arguments

1
compiler/tests/04_pand2_test.py
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@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pand2_test(openram_test):

21
compiler/tests/04_pbitcell_test.py
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@ -17,14 +17,13 @@ class pbitcell_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from pbitcell import pbitcell
OPTS.num_rw_ports=1
OPTS.num_w_ports=1
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=0
@ -32,7 +31,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 0 read/write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=1
@ -40,7 +39,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 0 write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=1
@ -48,7 +47,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=1
@ -56,7 +55,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
@ -64,7 +63,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=0
@ -72,7 +71,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 0 read/write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
@ -80,7 +79,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 0 write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
@ -88,7 +87,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
@ -96,7 +95,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
globals.end_openram()

7
compiler/tests/04_pbuf_test.py
View File

@ -9,19 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pbuf_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
import pbuf
debug.info(2, "Testing inverter/buffer 4x 8x")
a = pbuf.pbuf(name="pbufx8", size=8)
a = factory.create(module_type="pbuf", size=8)
self.local_check(a)
globals.end_openram()

15
compiler/tests/04_pdriver_test.py
View File

@ -9,35 +9,32 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pdriver_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
import pdriver
debug.info(2, "Testing inverter/buffer 4x 8x")
# a tests the error message for specifying conflicting conditions
#a = pdriver.pdriver(fanout = 4,size_list = [1,2,4,8])
#self.local_check(a)
b = pdriver.pdriver(name="pdriver1", size_list = [1,2,4,8])
b = factory.create(module_type="pdriver", size_list = [1,2,4,8])
self.local_check(b)
c = pdriver.pdriver(name="pdriver2", fanout = 50)
c = factory.create(module_type="pdriver", fanout = 50)
self.local_check(c)
d = pdriver.pdriver(name="pdriver3", fanout = 50, neg_polarity = True)
d = factory.create(module_type="pdriver", fanout = 50, neg_polarity = True)
self.local_check(d)
e = pdriver.pdriver(name="pdriver4", fanout = 64)
e = factory.create(module_type="pdriver", fanout = 64)
self.local_check(e)
f = pdriver.pdriver(name="pdriver5", fanout = 64, neg_polarity = True)
f = factory.create(module_type="pdriver", fanout = 64, neg_polarity = True)
self.local_check(f)
globals.end_openram()

7
compiler/tests/04_pinv_10x_test.py
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@ -9,17 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinv_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pinv
import tech
debug.info(2, "Checking 10x inverter")
tx = pinv.pinv(name="pinvx10",size=8)
debug.info(2, "Checking 8x inverter")
tx = factory.create(module_type="pinv", size=8)
self.local_check(tx)
globals.end_openram()

5
compiler/tests/04_pinv_1x_beta_test.py
View File

@ -9,17 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinv_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pinv
import tech
debug.info(2, "Checking 1x beta=3 size inverter")
tx = pinv.pinv(name="pinvx1b", size=1, beta=3)
tx = factory.create(module_type="pinv", size=1, beta=3)
self.local_check(tx)
globals.end_openram()

5
compiler/tests/04_pinv_1x_test.py
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@ -8,17 +8,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinv_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pinv
import tech
debug.info(2, "Checking 1x size inverter")
tx = pinv.pinv(name="pinvx1", size=1)
tx = factory.create(module_type="pinv", size=1)
self.local_check(tx)
globals.end_openram()

5
compiler/tests/04_pinv_2x_test.py
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@ -9,17 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinv_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pinv
import tech
debug.info(2, "Checking 2x size inverter")
tx = pinv.pinv(name="pinvx2", size=2)
tx = factory.create(module_type="pinv", size=2)
self.local_check(tx)
globals.end_openram()

4
compiler/tests/04_pinvbuf_test.py
View File

@ -9,16 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinvbuf_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pinvbuf
debug.info(2, "Testing inverter/buffer 4x 8x")
a = pinvbuf.pinvbuf(name="pinvufx8", size=8)
a = factory.create(module_type="pinvbuf", size=8)
self.local_check(a)
globals.end_openram()

5
compiler/tests/04_pnand2_test.py
View File

@ -11,17 +11,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pnand2_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pnand2
import tech
debug.info(2, "Checking 2-input nand gate")
tx = pnand2.pnand2(name="pnand2", size=1)
tx = factory.create(module_type="pnand2", size=1)
self.local_check(tx)
globals.end_openram()

5
compiler/tests/04_pnand3_test.py
View File

@ -11,17 +11,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pnand3_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pnand3
import tech
debug.info(2, "Checking 3-input nand gate")
tx = pnand3.pnand3(name="pnand3", size=1)
tx = factory.create(module_type="pnand3", size=1)
self.local_check(tx)
globals.end_openram()

5
compiler/tests/04_pnor2_test.py
View File

@ -11,17 +11,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pnor2_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pnor2
import tech
debug.info(2, "Checking 2-input nor gate")
tx = pnor2.pnor2(name="pnor2", size=1)
tx = factory.create(module_type="pnor2", size=1)
self.local_check(tx)
globals.end_openram()

14
compiler/tests/04_precharge_test.py
View File

@ -9,19 +9,17 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class precharge_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import precharge
import tech
# check precharge in single port
debug.info(2, "Checking precharge for handmade bitcell")
tx = precharge.precharge(name="precharge_driver", size=1)
tx = factory.create(module_type="precharge", size=1)
self.local_check(tx)
# check precharge in multi-port
@ -32,15 +30,17 @@ class precharge_test(openram_test):
factory.reset()
debug.info(2, "Checking precharge for pbitcell (innermost connections)")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for pbitcell (innermost connections)")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for pbitcell (outermost connections)")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(tx)
globals.end_openram()

2
compiler/tests/04_replica_pbitcell_test.py
View File

@ -9,8 +9,8 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class replica_pbitcell_test(openram_test):

10
compiler/tests/04_single_level_column_mux_test.py
View File

@ -9,8 +9,8 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 04_driver_test")
@ -18,12 +18,10 @@ class single_level_column_mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import single_level_column_mux
import tech
# check single level column mux in single port
debug.info(2, "Checking column mux")
tx = single_level_column_mux.single_level_column_mux(name="mux8", tx_size=8)
tx = factory.create(module_type="single_level_column_mux", tx_size=8)
self.local_check(tx)
# check single level column mux in multi-port
@ -34,12 +32,12 @@ class single_level_column_mux_test(openram_test):
factory.reset()
debug.info(2, "Checking column mux for pbitcell (innermost connections)")
tx = single_level_column_mux.single_level_column_mux(name="mux8_2", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking column mux for pbitcell (outermost connections)")
tx = single_level_column_mux.single_level_column_mux(name="mux8_3", tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(tx)
globals.end_openram()

4
compiler/tests/05_bitcell_1rw_1r_array_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
@ -17,14 +18,13 @@ class bitcell_1rw_1r_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
a = bitcell_array.bitcell_array(name="bitcell_1rw_1r_array", cols=4, rows=4)
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()

4
compiler/tests/05_bitcell_array_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 05_array_test")
@ -17,10 +18,9 @@ class array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
debug.info(2, "Testing 4x4 array for 6t_cell")
a = bitcell_array.bitcell_array(name="bitcell_array", cols=4, rows=4)
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()

8
compiler/tests/05_pbitcell_array_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 05_pbitcell_array_test")
@ -16,14 +17,13 @@ class pbitcell_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 2
OPTS.num_r_ports = 2
OPTS.num_w_ports = 2
a = bitcell_array.bitcell_array(name="pbitcell_array_Rport_edge", cols=4, rows=4)
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell")
@ -31,7 +31,7 @@ class pbitcell_array_test(openram_test):
OPTS.num_rw_ports = 2
OPTS.num_r_ports = 0
OPTS.num_w_ports = 2
a = bitcell_array.bitcell_array(name="pbitcell_array_Wport_edge", cols=4, rows=4)
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
@ -39,7 +39,7 @@ class pbitcell_array_test(openram_test):
OPTS.num_rw_ports = 2
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
a = bitcell_array.bitcell_array(name="pbitcell_array_RWport_edge", cols=4, rows=4)
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()

21
compiler/tests/06_hierarchical_decoder_test.py
View File

@ -9,16 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class hierarchical_decoder_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import hierarchical_decoder
import tech
# Doesn't require hierarchical decoder
# debug.info(1, "Testing 4 row sample for hierarchical_decoder")
# a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4)
@ -31,19 +28,19 @@ class hierarchical_decoder_test(openram_test):
# check hierarchical decoder for single port
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
a = hierarchical_decoder.hierarchical_decoder(name="hd3", rows=16)
a = factory.create(module_type="hierarchical_decoder", rows=16)
self.local_check(a)
debug.info(1, "Testing 32 row sample for hierarchical_decoder")
a = hierarchical_decoder.hierarchical_decoder(name="hd4", rows=32)
a = factory.create(module_type="hierarchical_decoder", rows=32)
self.local_check(a)
debug.info(1, "Testing 128 row sample for hierarchical_decoder")
a = hierarchical_decoder.hierarchical_decoder(name="hd5", rows=128)
a = factory.create(module_type="hierarchical_decoder", rows=128)
self.local_check(a)
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
a = hierarchical_decoder.hierarchical_decoder(name="hd6", rows=512)
a = factory.create(module_type="hierarchical_decoder", rows=512)
self.local_check(a)
# check hierarchical decoder for multi-port
@ -54,19 +51,19 @@ class hierarchical_decoder_test(openram_test):
factory.reset()
debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
a = hierarchical_decoder.hierarchical_decoder(name="hd7", rows=16)
a = factory.create(module_type="hierarchical_decoder", rows=16)
self.local_check(a)
debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)")
a = hierarchical_decoder.hierarchical_decoder(name="hd8", rows=32)
a = factory.create(module_type="hierarchical_decoder", rows=32)
self.local_check(a)
debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)")
a = hierarchical_decoder.hierarchical_decoder(name="hd9", rows=128)
a = factory.create(module_type="hierarchical_decoder", rows=128)
self.local_check(a)
debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)")
a = hierarchical_decoder.hierarchical_decoder(name="hd10", rows=512)
a = factory.create(module_type="hierarchical_decoder", rows=512)
self.local_check(a)
globals.end_openram()

7
compiler/tests/06_hierarchical_predecode2x4_test.py
View File

@ -9,18 +9,17 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class hierarchical_predecode2x4_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import hierarchical_predecode2x4 as pre
import tech
# checking hierarchical precode 2x4 for single port
debug.info(1, "Testing sample for hierarchy_predecode2x4")
a = pre.hierarchical_predecode2x4(name="pre1")
a = factory.create(module_type="hierarchical_predecode2x4")
self.local_check(a)
# checking hierarchical precode 2x4 for multi-port
@ -30,7 +29,7 @@ class hierarchical_predecode2x4_test(openram_test):
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
a = pre.hierarchical_predecode2x4(name="pre2")
a = factory.create(module_type="hierarchical_predecode2x4")
self.local_check(a)
globals.end_openram()

7
compiler/tests/06_hierarchical_predecode3x8_test.py
View File

@ -9,18 +9,17 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class hierarchical_predecode3x8_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import hierarchical_predecode3x8 as pre
import tech
# checking hierarchical precode 3x8 for single port
debug.info(1, "Testing sample for hierarchy_predecode3x8")
a = pre.hierarchical_predecode3x8(name="pre1")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
# checking hierarchical precode 3x8 for multi-port
@ -30,7 +29,7 @@ class hierarchical_predecode3x8_test(openram_test):
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
a = pre.hierarchical_predecode3x8(name="pre2")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
globals.end_openram()

16
compiler/tests/07_single_level_column_mux_array_test.py
View File

@ -8,8 +8,8 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class single_level_column_mux_test(openram_test):
@ -19,15 +19,15 @@ class single_level_column_mux_test(openram_test):
# check single level column mux array in single port
debug.info(1, "Testing sample for 2-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux1", columns=16, word_size=8)
a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8)
self.local_check(a)
debug.info(1, "Testing sample for 4-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux2", columns=16, word_size=4)
a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4)
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux3", columns=32, word_size=4)
a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4)
self.local_check(a)
# check single level column mux array in multi-port
@ -38,19 +38,19 @@ class single_level_column_mux_test(openram_test):
factory.reset()
debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux4", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 4-way column_mux_array in multi-port")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux5", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux6", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux7", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(a)
globals.end_openram()

7
compiler/tests/08_precharge_array_test.py
View File

@ -9,18 +9,17 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class precharge_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import precharge_array
# check precharge array in single port
debug.info(2, "Checking 3 column precharge")
pc = precharge_array.precharge_array(name="pre1", columns=3)
pc = factory.create(module_type="precharge_array", columns=3)
self.local_check(pc)
# check precharge array in multi-port
@ -31,7 +30,7 @@ class precharge_test(openram_test):
factory.reset()
debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
pc = precharge_array.precharge_array(name="pre2", columns=3, bitcell_bl="bl0", bitcell_br="br0")
pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(pc)
# debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")

7
compiler/tests/08_wordline_driver_test.py
View File

@ -9,8 +9,8 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 04_driver_test")
@ -18,11 +18,10 @@ class wordline_driver_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import wordline_driver
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = wordline_driver.wordline_driver(name="wld1", rows=8, cols=32)
tx = factory.create(module_type="wordline_driver", rows=8, cols=32)
self.local_check(tx)
# check wordline driver for multi-port
@ -33,7 +32,7 @@ class wordline_driver_test(openram_test):
factory.reset()
debug.info(2, "Checking driver (multi-port case)")
tx = wordline_driver.wordline_driver(name="wld2", rows=8, cols=64)
tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
self.local_check(tx)
globals.end_openram()

11
compiler/tests/09_sense_amp_array_test.py
View File

@ -9,22 +9,21 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class sense_amp_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import sense_amp_array
# check sense amp array for single port
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
a = sense_amp_array.sense_amp_array(name="sa1", word_size=4, words_per_row=2)
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
self.local_check(a)
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
a = sense_amp_array.sense_amp_array(name="sa2", word_size=4, words_per_row=4)
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
self.local_check(a)
# check sense amp array for multi-port
@ -35,11 +34,11 @@ class sense_amp_test(openram_test):
factory.reset()
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
a = sense_amp_array.sense_amp_array(name="sa3", word_size=4, words_per_row=2)
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
self.local_check(a)
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
a = sense_amp_array.sense_amp_array(name="sa4", word_size=4, words_per_row=4)
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
self.local_check(a)
globals.end_openram()

11
compiler/tests/10_write_driver_array_test.py
View File

@ -9,22 +9,21 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class write_driver_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import write_driver_array
# check write driver array for single port
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
a = write_driver_array.write_driver_array(name="wd1", columns=8, word_size=8)
a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
a = write_driver_array.write_driver_array(name="wd2", columns=16, word_size=8)
a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
self.local_check(a)
# check write driver array for multi-port
@ -35,11 +34,11 @@ class write_driver_test(openram_test):
factory.reset()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
a = write_driver_array.write_driver_array(name="wd3", columns=8, word_size=8)
a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
a = write_driver_array.write_driver_array(name="wd4", columns=16, word_size=8)
a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()

8
compiler/tests/11_dff_array_test.py
View File

@ -9,24 +9,24 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class dff_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import dff_array
debug.info(2, "Testing dff_array for 3x3")
a = dff_array.dff_array(rows=3, columns=3)
a = factory.create(module_type="dff_array", rows=3, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_array for 1x3")
a = dff_array.dff_array(rows=1, columns=3)
a = factory.create(module_type="dff_array", rows=1, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_array for 3x1")
a = dff_array.dff_array(rows=3, columns=1)
a = factory.create(module_type="dff_array", rows=3, columns=1)
self.local_check(a)
globals.end_openram()

8
compiler/tests/11_dff_buf_array_test.py
View File

@ -9,24 +9,24 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class dff_buf_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import dff_buf_array
debug.info(2, "Testing dff_buf_array for 3x3")
a = dff_buf_array.dff_buf_array(rows=3, columns=3)
a = factory.create(module_type="dff_buf_array", rows=3, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_buf_array for 1x3")
a = dff_buf_array.dff_buf_array(rows=1, columns=3)
a = factory.create(module_type="dff_buf_array", rows=1, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_buf_array for 3x1")
a = dff_buf_array.dff_buf_array(rows=3, columns=1)
a = factory.create(module_type="dff_buf_array", rows=3, columns=1)
self.local_check(a)
globals.end_openram()

4
compiler/tests/11_dff_buf_test.py
View File

@ -9,16 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class dff_buf_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import dff_buf
debug.info(2, "Testing dff_buf 4x 8x")
a = dff_buf.dff_buf(4, 8)
a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8)
self.local_check(a)
globals.end_openram()

6
compiler/tests/12_tri_gate_array_test.py
View File

@ -9,20 +9,20 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class tri_gate_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import tri_gate_array
debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")
a = tri_gate_array.tri_gate_array(columns=8, word_size=8)
a = factory.create(module_type="tri_gate_array", columns=8, word_size=8)
self.local_check(a)
debug.info(1, "Testing tri_gate_array for columns=16, word_size=8")
a = tri_gate_array.tri_gate_array(columns=16, word_size=8)
a = factory.create(module_type="tri_gate_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()

4
compiler/tests/13_delay_chain_test.py
View File

@ -9,16 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class delay_chain_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import delay_chain
debug.info(2, "Testing delay_chain")
a = delay_chain.delay_chain(name="dc", fanout_list=[4, 4, 4, 4])
a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4])
self.local_check(a)
globals.end_openram()

9
compiler/tests/14_replica_bitline_multiport_test.py
View File

@ -9,14 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class replica_bitline_multiport_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import replica_bitline
stages=4
fanout=4
@ -30,7 +29,7 @@ class replica_bitline_multiport_test(openram_test):
factory.reset()
debug.info(2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(name="rbl1", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
self.local_check(a)
# check replica bitline in pbitcell multi-port
@ -42,7 +41,7 @@ class replica_bitline_multiport_test(openram_test):
factory.reset()
debug.info(2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(name="rbl2", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
self.local_check(a)
OPTS.num_rw_ports = 1
@ -51,7 +50,7 @@ class replica_bitline_multiport_test(openram_test):
factory.reset()
debug.info(2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(name="rbl3", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
self.local_check(a)
globals.end_openram()

8
compiler/tests/14_replica_bitline_test.py
View File

@ -9,30 +9,28 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class replica_bitline_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import replica_bitline
# check replica bitline in single port
stages=4
fanout=4
rows=13
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(name="rbl1", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
self.local_check(a)
#debug.error("Exiting...", 1)
stages=8
rows=100
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(name="rbl2", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
self.local_check(a)
globals.end_openram()
# run the test from the command line

11
compiler/tests/16_control_logic_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class control_logic_test(openram_test):
@ -20,7 +21,7 @@ class control_logic_test(openram_test):
# check control logic for single port
debug.info(1, "Testing sample for control_logic")
a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=32)
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
self.local_check(a)
# check control logic for multi-port
@ -31,7 +32,7 @@ class control_logic_test(openram_test):
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for control_logic for multiport")
a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8)
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8)
self.local_check(a)
# Check port specific control logic
@ -40,19 +41,19 @@ class control_logic_test(openram_test):
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="rw")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
self.local_check(a)
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="w")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w")
self.local_check(a)
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
debug.info(1, "Testing sample for control_logic for multiport, only read control logic")
a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="r")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="r")
self.local_check(a)
globals.end_openram()

10
compiler/tests/19_bank_select_test.py
View File

@ -9,21 +9,21 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class bank_select_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bank_select
debug.info(1, "No column mux, rw control logic")
a = bank_select.bank_select(port="rw")
a = factory.create(module_type="bank_select", port="rw")
self.local_check(a)
OPTS.bitcell = "pbitcell"
debug.info(1, "No column mux, rw control logic")
a = bank_select.bank_select(port="rw")
a = factory.create(module_type="bank_select", port="rw")
self.local_check(a)
OPTS.num_rw_ports = 0
@ -31,11 +31,11 @@ class bank_select_test(openram_test):
OPTS.num_r_ports = 1
debug.info(1, "No column mux, w control logic")
a = bank_select.bank_select(port="w")
a = factory.create(module_type="bank_select", port="w")
self.local_check(a)
debug.info(1, "No column mux, r control logic")
a = bank_select.bank_select(port="r")
a = factory.create(module_type="bank_select", port="r")
self.local_check(a)
globals.end_openram()

14
compiler/tests/19_multi_bank_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 19_multi_bank_test")
@ -16,7 +17,6 @@ class multi_bank_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from bank import bank
from sram_config import sram_config
c = sram_config(word_size=4,
@ -24,31 +24,35 @@ class multi_bank_test(openram_test):
c.num_banks=2
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = bank(c, name="bank1_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = bank(c, name="bank2_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = bank(c, name="bank3_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = bank(c, name="bank4_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()

18
compiler/tests/19_pmulti_bank_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 19_pmulti_bank_test")
@ -16,7 +17,6 @@ class multi_bank_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from bank import bank
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
@ -29,27 +29,35 @@ class multi_bank_test(openram_test):
c.num_banks=2
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = bank(c, name="bank1_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = bank(c, name="bank2_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = bank(c, name="bank3_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = bank(c, name="bank4_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()

2
compiler/tests/19_psingle_bank_test.py
View File

@ -9,8 +9,8 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 19_psingle_bank_test")
class psingle_bank_test(openram_test):

18
compiler/tests/19_single_bank_1rw_1r_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class single_bank_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from bank import bank
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
@ -27,27 +27,35 @@ class single_bank_1rw_1r_test(openram_test):
num_words=16)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = bank(c, name="bank1_single")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = bank(c, name="bank2_single")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = bank(c, name="bank3_single")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = bank(c, name="bank4_single")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
globals.end_openram()

18
compiler/tests/19_single_bank_test.py
View File

@ -9,40 +9,48 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class single_bank_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from bank import bank
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=16)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = bank(c, name="bank1_single")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = bank(c, name="bank2_single")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = bank(c, name="bank3_single")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = bank(c, name="bank4_single")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()

4
compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
@ -16,7 +17,6 @@ class psram_1bank_2mux_1rw_1w_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@ -38,7 +38,7 @@ class psram_1bank_2mux_1rw_1w_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
@ -16,7 +17,6 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@ -38,7 +38,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_psram_1bank_2mux_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error")
@ -16,7 +17,6 @@ class psram_1bank_2mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@ -39,7 +39,7 @@ class psram_1bank_2mux_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class psram_1bank_4mux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@ -37,7 +37,7 @@ class psram_1bank_4mux_1rw_1r_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class sram_1bank_2mux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "bitcell_1rw_1r"
@ -37,7 +37,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
@ -16,7 +17,6 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "bitcell_1w_1r"
OPTS.replica_bitcell="replica_bitcell_1w_1r"
@ -38,7 +38,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_sram_1bank_2mux_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_sram_1bank_2mux_test")
@ -16,7 +17,6 @@ class sram_1bank_2mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
@ -31,7 +31,7 @@ class sram_1bank_2mux_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_sram_1bank_4mux_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_sram_1bank_4mux_test")
@ -16,7 +17,6 @@ class sram_1bank_4mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=64,
@ -31,7 +31,7 @@ class sram_1bank_4mux_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class sram_1bank_8mux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "bitcell_1rw_1r"
@ -37,7 +37,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_sram_1bank_8mux_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_sram_1bank_8mux_test")
@ -16,7 +17,6 @@ class sram_1bank_8mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=128,
@ -31,7 +31,7 @@ class sram_1bank_8mux_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class sram_1bank_nomux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
OPTS.bitcell = "bitcell_1rw_1r"
@ -37,7 +37,7 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/20_sram_1bank_nomux_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_sram_1bank_nomux_test")
@ -16,7 +17,6 @@ class sram_1bank_nomux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=16,
@ -31,7 +31,7 @@ class sram_1bank_nomux_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

14
compiler/tests/20_sram_2bank_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("Multibank is not working yet.")
@ -16,7 +17,6 @@ class sram_2bank_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=16,
num_words=32,
@ -25,21 +25,24 @@ class sram_2bank_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Two bank, no column mux with control logic")
a = sram(c, "sram1")
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
c.num_words=64
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Two bank two way column mux with control logic")
a = sram(c, "sram2")
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
c.num_words=128
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Two bank, four way column mux with control logic")
a = sram(c, "sram3")
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
c.word_size=2
@ -47,7 +50,8 @@ class sram_2bank_test(openram_test):
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Two bank, eight way column mux with control logic")
a = sram(c, "sram4")
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

4
compiler/tests/21_hspice_delay_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class timing_sram_test(openram_test):
@ -24,7 +25,6 @@ class timing_sram_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1,
num_words=16,
@ -32,7 +32,7 @@ class timing_sram_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

1
compiler/tests/21_hspice_setuphold_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class timing_setup_test(openram_test):

4
compiler/tests/21_ngspice_delay_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class timing_sram_test(openram_test):
@ -24,7 +25,6 @@ class timing_sram_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1,
num_words=16,
@ -32,7 +32,7 @@ class timing_sram_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

1
compiler/tests/21_ngspice_setuphold_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class timing_setup_test(openram_test):

4
compiler/tests/22_psram_1bank_2mux_func_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_2mux_1rw_1r_1w_func_test, third port reads are broken?")
@ -30,7 +31,6 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=64,
@ -44,7 +44,7 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

4
compiler/tests/22_psram_1bank_4mux_func_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test, third port reads are broken?")
@ -30,7 +31,6 @@ class psram_1bank_4mux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=256,
@ -44,7 +44,7 @@ class psram_1bank_4mux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

4
compiler/tests/22_psram_1bank_8mux_func_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_8mux_func_test")
@ -30,7 +31,6 @@ class psram_1bank_8mux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=256,
@ -44,7 +44,7 @@ class psram_1bank_8mux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

4
compiler/tests/22_psram_1bank_nomux_func_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_nomux_func_test")
@ -30,7 +31,6 @@ class psram_1bank_nomux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
@ -44,7 +44,7 @@ class psram_1bank_nomux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

4
compiler/tests/22_sram_1bank_2mux_func_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_1bank_2mux_func_test")
@ -25,7 +26,6 @@ class sram_1bank_2mux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=64,
@ -36,7 +36,7 @@ class sram_1bank_2mux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

4
compiler/tests/22_sram_1bank_4mux_func_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_1bank_4mux_func_test")
@ -25,7 +26,6 @@ class sram_1bank_4mux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=256,
@ -36,7 +36,7 @@ class sram_1bank_4mux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

4
compiler/tests/22_sram_1bank_8mux_func_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_1bank_8mux_func_test")
@ -28,7 +29,6 @@ class sram_1bank_8mux_func_test(openram_test):
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=256,
@ -39,7 +39,7 @@ class sram_1bank_8mux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

4
compiler/tests/22_sram_1bank_nomux_func_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_func_test")
@ -24,7 +25,6 @@ class sram_1bank_nomux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
@ -35,7 +35,7 @@ class sram_1bank_nomux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

4
compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test")
@ -30,7 +31,6 @@ class psram_1bank_nomux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
@ -41,7 +41,7 @@ class psram_1bank_nomux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

5
compiler/tests/23_lib_sram_model_corners_test.py
View File

@ -9,6 +9,7 @@ import sys,os,re
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class model_corners_lib_test(openram_test):
@ -17,7 +18,6 @@ class model_corners_lib_test(openram_test):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from characterizer import lib
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
@ -25,7 +25,8 @@ class model_corners_lib_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

5
compiler/tests/23_lib_sram_model_test.py
View File

@ -9,6 +9,7 @@ import sys,os,re
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class lib_test(openram_test):
@ -17,7 +18,6 @@ class lib_test(openram_test):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from characterizer import lib
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
@ -25,7 +25,8 @@ class lib_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

5
compiler/tests/23_lib_sram_prune_test.py
View File

@ -9,6 +9,7 @@ import sys,os,re
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class lib_test(openram_test):
@ -26,7 +27,6 @@ class lib_test(openram_test):
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
@ -34,7 +34,8 @@ class lib_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing pruned timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

5
compiler/tests/23_lib_sram_test.py
View File

@ -9,6 +9,7 @@ import sys,os,re
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class lib_test(openram_test):
@ -26,7 +27,6 @@ class lib_test(openram_test):
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
@ -34,7 +34,8 @@ class lib_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

4
compiler/tests/24_lef_sram_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 24_lef_sram_test")
@ -17,7 +18,6 @@ class lef_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
@ -25,7 +25,7 @@ class lef_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
gdsfile = s.name + ".gds"
leffile = s.name + ".lef"

4
compiler/tests/25_verilog_sram_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class verilog_test(openram_test):
@ -16,7 +17,6 @@ class verilog_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
@ -24,7 +24,7 @@ class verilog_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
vfile = s.name + ".v"
vname = OPTS.openram_temp + vfile

1
compiler/tests/26_pex_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 26_pex_test")

4
compiler/tests/27_worst_case_delay_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 27_worst_case_delay_test")
@ -33,7 +34,6 @@ class worst_case_timing_sram_test(openram_test):
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
word_size, num_words, num_banks = 2, 16, 1
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=word_size,
num_words=num_words,
@ -42,7 +42,7 @@ class worst_case_timing_sram_test(openram_test):
c.recompute_sizes()
debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format(
word_size, num_words, num_banks))
s = sram(c, name="sram1")
s = factory.create(module_type="sram", sram_config=c)
sp_netlist_file = OPTS.openram_temp + "temp.sp"
s.sp_write(sp_netlist_file)

4
compiler/tests/28_delay_model_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class delay_model_test(openram_test):
@ -27,7 +28,6 @@ class delay_model_test(openram_test):
reload(characterizer)
from characterizer import model_check
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=16,
@ -35,7 +35,7 @@ class delay_model_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

1
compiler/tests/30_openram_test.py
View File

@ -11,6 +11,7 @@ import sys,os,re,shutil
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
import getpass