mirror of https://github.com/VLSIDA/OpenRAM.git
Added word per row to sram config with a default arguement to fix test.
This commit is contained in:
Hunter Nichols
parent
c10c9e4009
commit
45fceb1f4e
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@ -317,6 +317,15 @@ class model_check(delay):
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return data_dict
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def get_all_signal_names(self):
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"""Returns all signals names as a dict indexed by hardcoded names. Useful for writing the head of the CSV."""
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name_dict = {}
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#Signal names are more descriptive than the measurement names, first value trimmed to match size of measurements names.
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name_dict[self.wl_meas_name] = self.wl_signal_names[1:]
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name_dict[self.wl_model_name] = name_dict["wl_measures"] #model uses same names as measured.
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name_dict[self.sae_meas_name] = self.rbl_en_signal_names[1:]+self.sae_signal_names[1:]
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name_dict[self.sae_model_name] = name_dict["sae_measures"]
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return name_dict
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@ -141,9 +141,9 @@ class control_logic(design.design):
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delay_stages = parameter["static_delay_stages"]
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delay_fanout = parameter["static_fanout_per_stage"]
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debug.info(1, "Using tech parameters to size delay chain: stages={}, fanout={}".format(delay_stages,delay_fanout))
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self.replica_bitline = replica_bitline([delay_fanout]*delay_stages,
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bitcell_loads,
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name="replica_bitline_"+self.port_type)
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self.replica_bitline = replica_bitline("replica_bitline_"+self.port_type,
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[delay_fanout]*delay_stages,
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bitcell_loads)
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if self.sram != None: #Calculate model value even for specified sizes
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self.set_sen_wl_delays()
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@ -159,15 +159,15 @@ class control_logic(design.design):
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if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match():
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#This resizes to match fall and rise delays, can make the delay chain weird sizes.
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# stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
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# self.replica_bitline = replica_bitline(stage_list,
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# bitcell_loads,
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# name="replica_bitline_resized_"+self.port_type)
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# self.replica_bitline = replica_bitline( "replica_bitline_resized_"+self.port_type
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# stage_list,
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# bitcell_loads)
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#This resizes based on total delay.
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delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic)
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self.replica_bitline = replica_bitline([delay_fanout]*delay_stages,
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bitcell_loads,
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name="replica_bitline_resized_"+self.port_type)
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self.replica_bitline = replica_bitline("replica_bitline_resized_"+self.port_type,
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[delay_fanout]*delay_stages,
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bitcell_loads)
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self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
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@ -7,13 +7,13 @@ from sram_factory import factory
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class sram_config:
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""" This is a structure that is used to hold the SRAM configuration options. """
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def __init__(self, word_size, num_words, num_banks=1):
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def __init__(self, word_size, num_words, num_banks=1, words_per_row=None):
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self.word_size = word_size
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self.num_words = num_words
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self.num_banks = num_banks
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# This will get over-written when we determine the organization
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self.words_per_row = None
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self.words_per_row = words_per_row
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self.compute_sizes()
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@ -187,10 +187,8 @@ class data_collection(openram_test):
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"""Generates the SRAM based on input configuration."""
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c = sram_config(word_size=word_size,
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num_words=num_words,
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num_banks=1)
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#minimum 16 rows. Most sizes below 16*16 will try to automatically use less rows unless enforced.
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#if word_size*num_words < 256:
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c.words_per_row=words_per_row #Force no column mux until incorporated into analytical delay.
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num_banks=1,
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words_per_row=words_per_row)
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debug.info(1, "Creating SRAM: {} bit, {} words, with 1 bank".format(word_size, num_words))
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self.sram = sram(c, name="sram_{}ws_{}words".format(word_size, num_words))
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@ -198,6 +196,8 @@ class data_collection(openram_test):
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self.sram_spice = OPTS.openram_temp + "temp.sp"
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self.sram.sp_write(self.sram_spice)
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debug.info(1, "SRAM column address size={}".format(self.sram.s.col_addr_size))
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def get_sram_data(self, corner):
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"""Generates the delay object using the corner and runs a simulation for data."""
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from characterizer import model_check
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@ -1,6 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
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4,16,1,TT,1.0,25,0.021103999999999998,0.0061908,0.018439,0.017329999999999998,0.0094258,0.018392000000000002,0.011755000000000002
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4,16,1,FF,1.0,25,0.019583,0.005128,0.017439,0.015281,0.008443599999999999,0.017213000000000003,0.010389
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4,16,1,SS,1.0,25,0.022932,0.0074386999999999995,0.019891000000000002,0.019466,0.010501,0.019849,0.013432
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4,16,1,SF,1.0,25,0.019301,0.007507700000000001,0.016878999999999998,0.018834,0.010293,0.017156,0.01299
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4,16,1,FS,1.0,25,0.023601,0.0045925,0.020515,0.015586,0.0085521,0.019967,0.010449
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0
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4,16,1,TT,1.0,25,0.020618,0.0062215,0.018563000000000003,0.017233000000000002,0.007710799999999999,0.0099965,0.045221000000000004
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4,16,1,FF,1.0,25,0.019135,0.0052523000000000005,0.017398,0.015280000000000002,0.0067718,0.009288300000000001,0.042180999999999996
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4,16,1,SS,1.0,25,0.022393999999999997,0.0074892,0.019906,0.019521999999999998,0.0087409,0.010967000000000001,0.04836
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4,16,1,SF,1.0,25,0.01874,0.007554100000000001,0.016919,0.018821,0.0086205,0.0094092,0.049122
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4,16,1,FS,1.0,25,0.022926,0.0046388,0.02054,0.015555000000000001,0.0067794,0.010772,0.041583
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@ -1,6 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
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4,16,1,TT,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
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4,16,1,FF,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
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4,16,1,SS,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
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4,16,1,SF,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
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4,16,1,FS,1.0,25,8.8,2.65,6.4,7.4,4.4,6.4,2.99375
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0
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4,16,1,TT,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15
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4,16,1,FF,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15
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4,16,1,SS,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15
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4,16,1,SF,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15
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4,16,1,FS,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15
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@ -1,6 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,0.018438,0.0092547,0.013922,0.008679300000000001
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4,16,1,FF,1.0,25,0.017261,0.008002500000000001,0.012757,0.0077545
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4,16,1,SS,1.0,25,0.019962,0.010683,0.015394,0.009734999999999999
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4,16,1,SF,1.0,25,0.017044,0.010483999999999999,0.012825,0.0094333
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4,16,1,FS,1.0,25,0.020398,0.0078018,0.015243999999999999,0.0079892
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,0.010512,0.0089216,0.014109,0.013643,0.014564,0.0086745
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4,16,1,FF,1.0,25,0.0096952,0.008041900000000001,0.013129,0.012268999999999999,0.013255999999999999,0.007759599999999999
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4,16,1,SS,1.0,25,0.011505,0.009873400000000001,0.015371,0.015194000000000001,0.016210000000000002,0.0097529
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4,16,1,SF,1.0,25,0.0097161,0.0096343,0.013210000000000001,0.014750000000000001,0.013464,0.0094366
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4,16,1,FS,1.0,25,0.011368999999999999,0.0082136,0.015231000000000001,0.012545,0.015907,0.0079376
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@ -1,6 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,FF,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,SS,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,SF,1.0,25,4.4,12.4,5.8,5.4
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4,16,1,FS,1.0,25,4.4,12.4,5.8,5.4
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
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4,16,1,FF,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
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4,16,1,SS,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
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4,16,1,SF,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
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4,16,1,FS,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
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@ -1,6 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
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4,16,1,TT,1.0,25,0.021141999999999998,0.006257400000000001,0.015622,0.014144,0.017741,0.013434,0.009287,0.018439999999999998,0.011276
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4,16,1,FF,1.0,25,0.019646,0.0052736,0.014601,0.012589,0.016537,0.011916999999999999,0.0083483,0.017246,0.0099574
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4,16,1,SS,1.0,25,0.022917,0.0074182,0.016901,0.015895,0.019267,0.015147,0.010306000000000001,0.01986,0.012834
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4,16,1,SF,1.0,25,0.019208,0.007500799999999999,0.014421999999999999,0.015359999999999999,0.016408,0.014695999999999999,0.010128,0.017086999999999998,0.012516000000000001
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4,16,1,FS,1.0,25,0.023644000000000002,0.0046118,0.017239,0.01283,0.019428,0.012081999999999999,0.0085141,0.020073,0.009944
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0
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4,16,1,TT,1.0,25,0.020572,0.006256,0.015678,0.014110000000000001,0.017755,0.013415,0.0076344,0.010162,0.04153
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4,16,1,FF,1.0,25,0.01907,0.0052328,0.014619000000000002,0.0126,0.016572,0.011862,0.0067348,0.0093334,0.03898
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4,16,1,SS,1.0,25,0.022189,0.0074532999999999995,0.016968,0.015854,0.019286,0.015139,0.0087264,0.011029,0.04439
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4,16,1,SF,1.0,25,0.018689,0.007557800000000001,0.014395999999999999,0.015354,0.016425000000000002,0.014665,0.0084936,0.009411300000000001,0.044714000000000004
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4,16,1,FS,1.0,25,0.022942,0.0046639,0.017356,0.012745999999999999,0.01949,0.012069,0.006808099999999999,0.010822,0.038710999999999995
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@ -1,6 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.zb_int,Xsram.s_en0
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4,16,1,TT,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
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4,16,1,FF,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
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4,16,1,SS,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
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4,16,1,SF,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
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4,16,1,FS,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,4.4,6.4,2.99375
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0
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4,16,1,TT,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15
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4,16,1,FF,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15
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4,16,1,SS,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15
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4,16,1,SF,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15
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4,16,1,FS,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15
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@ -1,6 +1,6 @@
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
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4,16,1,TT,1.0,25,0.018481,0.0093054,0.013848,0.008683999999999999
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4,16,1,FF,1.0,25,0.017331,0.0080465,0.012700999999999999,0.0077613000000000005
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4,16,1,SS,1.0,25,0.019895,0.010660000000000001,0.015356999999999999,0.009745
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4,16,1,SF,1.0,25,0.016984000000000003,0.010501,0.012796,0.009405700000000001
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4,16,1,FS,1.0,25,0.020445,0.007772300000000001,0.015284,0.0079428
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word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
|
||||
4,16,1,TT,1.0,25,0.010463,0.0089004,0.014107,0.013630000000000001,0.0146,0.0086902
|
||||
4,16,1,FF,1.0,25,0.0096519,0.008039899999999999,0.013115,0.012295,0.013235,0.0077621
|
||||
4,16,1,SS,1.0,25,0.011424,0.0098775,0.015351999999999998,0.015194000000000001,0.016227,0.0097375
|
||||
4,16,1,SF,1.0,25,0.009697500000000001,0.009592,0.013206,0.014738000000000001,0.013432,0.0094217
|
||||
4,16,1,FS,1.0,25,0.011432000000000001,0.0081985,0.015220000000000001,0.012544,0.015973,0.0079455
|
||||
|
|
|
|||
|
|
|
@ -1,6 +1,6 @@
|
|||
word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.zb_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
|
||||
4,16,1,TT,1.0,25,4.4,12.4,5.8,5.4
|
||||
4,16,1,FF,1.0,25,4.4,12.4,5.8,5.4
|
||||
4,16,1,SS,1.0,25,4.4,12.4,5.8,5.4
|
||||
4,16,1,SF,1.0,25,4.4,12.4,5.8,5.4
|
||||
4,16,1,FS,1.0,25,4.4,12.4,5.8,5.4
|
||||
word_size,num_words,words_per_row,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15
|
||||
4,16,1,TT,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
|
||||
4,16,1,FF,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
|
||||
4,16,1,SS,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
|
||||
4,16,1,SF,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
|
||||
4,16,1,FS,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4
|
||||
|
|
|
|||
|
Loading…
Reference in New Issue