mirror of https://github.com/VLSIDA/OpenRAM.git
Added graph creation to characterizer, re-arranged pin creation.
This commit is contained in:
Hunter Nichols
parent
b4cce65889
commit
b30c20ffb5
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@ -10,6 +10,7 @@ from globals import OPTS
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from .simulation import simulation
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from .measurements import *
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import logical_effort
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import graph_util
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class delay(simulation):
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"""Functions to measure the delay and power of an SRAM at a given address and
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@ -37,6 +38,8 @@ class delay(simulation):
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self.period = 0
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self.set_load_slew(0,0)
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self.set_corner(corner)
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self.create_signal_names()
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self.add_graph_exclusions()
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def create_measurement_names(self):
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"""Create measurement names. The names themselves currently define the type of measurement"""
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@ -157,19 +160,31 @@ class delay(simulation):
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self.debug_volt_meas[-1].meta_str = debug_meas.meta_str
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return self.debug_delay_meas+self.debug_volt_meas
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def create_signal_names(self):
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self.addr_name = "A"
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self.din_name = "DIN"
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self.dout_name = "DOUT"
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#This is TODO once multiport control has been finalized.
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#self.control_name = "CSB"
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def set_load_slew(self,load,slew):
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""" Set the load and slew """
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self.load = load
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self.slew = slew
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def add_graph_exclusions(self):
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"""Exclude portions of SRAM from timing graph which are not relevant"""
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#other initializations can only be done during analysis when a bit has been selected
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#for testing.
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self.sram.bank.graph_exclude_precharge()
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self.sram.graph_exclude_addr_dff()
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self.sram.graph_exclude_data_dff()
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self.sram.graph_exclude_ctrl_dffs()
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def create_graph(self):
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"""Creates timing graph to generate the timing paths for the SRAM output."""
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self.sram.bank.bitcell_array.init_graph_params() #Removes previous bit exclusions
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self.sram.bank.bitcell_array.graph_exclude_bits(self.wordline_row, self.bitline_column)
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#Generate new graph every analysis as edges might change depending on test bit
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self.graph = graph_util.timing_graph()
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self.sram.build_graph(self.graph,"X{}".format(self.sram.name),self.pins)
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#debug.info(1,"{}".format(graph))
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#graph.print_all_paths('clk0', 'DOUT0[0]')
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def check_arguments(self):
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"""Checks if arguments given for write_stimulus() meets requirements"""
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try:
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@ -198,12 +213,8 @@ class delay(simulation):
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# instantiate the sram
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self.sf.write("\n* Instantiation of the SRAM\n")
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self.stim.inst_sram(sram=self.sram,
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port_signal_names=(self.addr_name,self.din_name,self.dout_name),
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port_info=(len(self.all_ports),self.write_ports,self.read_ports),
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abits=self.addr_size,
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dbits=self.word_size,
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sram_name=self.name)
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self.stim.inst_model(pins=self.pins,
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model_name=self.sram.name)
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self.sf.write("\n* SRAM output loads\n")
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for port in self.read_ports:
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for i in range(self.word_size):
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@ -812,7 +823,7 @@ class delay(simulation):
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char_sram_data = {}
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self.set_probe(probe_address, probe_data)
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self.create_signal_names()
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self.create_graph()
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self.create_measurement_names()
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self.create_measurement_objects()
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@ -998,7 +1009,6 @@ class delay(simulation):
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"""
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if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
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debug.warning("Analytical characterization results are not supported for multiport.")
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self.create_signal_names()
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self.create_measurement_names()
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power = self.analytical_power(slews, loads)
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port_data = self.get_empty_measure_data_dict()
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@ -194,12 +194,7 @@ class functional(simulation):
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new_value = "0" + new_value
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#print("Binary Conversion: {} to {}".format(value, new_value))
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return new_value
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def create_signal_names(self):
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self.addr_name = "A"
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self.din_name = "DIN"
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self.dout_name = "DOUT"
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return new_value
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def write_functional_stimulus(self):
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""" Writes SPICE stimulus. """
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@ -219,12 +214,8 @@ class functional(simulation):
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#Instantiate the SRAM
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self.sf.write("\n* Instantiation of the SRAM\n")
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self.stim.inst_sram(sram=self.sram,
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port_signal_names=(self.addr_name,self.din_name,self.dout_name),
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port_info=(len(self.all_ports), self.write_ports, self.read_ports),
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abits=self.addr_size,
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dbits=self.word_size,
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sram_name=self.name)
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self.stim.inst_model(pins=self.pins,
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model_name=self.sram.name)
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# Add load capacitance to each of the read ports
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self.sf.write("\n* SRAM output loads\n")
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@ -42,6 +42,19 @@ class simulation():
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self.v_low = tech.spice["v_threshold_typical"]
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self.gnd_voltage = 0
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def create_signal_names(self):
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self.addr_name = "A"
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self.din_name = "DIN"
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self.dout_name = "DOUT"
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self.pins = self.gen_pin_names(port_signal_names=(self.addr_name,self.din_name,self.dout_name),
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port_info=(len(self.all_ports),self.write_ports,self.read_ports),
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abits=self.addr_size,
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dbits=self.word_size)
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debug.check(len(self.sram.pins) == len(self.pins), "Number of pins generated for characterization \
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do match pins of SRAM\nsram.pins = {0}\npin_names = {1}".format(self.sram.pins,self.pins))
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#This is TODO once multiport control has been finalized.
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#self.control_name = "CSB"
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def set_stimulus_variables(self):
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# Clock signals
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self.cycle_times = []
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@ -223,3 +236,38 @@ class simulation():
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t_current+self.period)
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return comment
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def gen_pin_names(self, port_signal_names, port_info, abits, dbits):
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"""Creates the pins names of the SRAM based on the no. of ports."""
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#This may seem redundant as the pin names are already defined in the sram. However, it is difficult
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#to extract the functionality from the names, so they are recreated. As the order is static, changing
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#the order of the pin names will cause issues here.
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pin_names = []
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(addr_name, din_name, dout_name) = port_signal_names
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(total_ports, write_index, read_index) = port_info
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for write_input in write_index:
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for i in range(dbits):
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pin_names.append("{0}{1}_{2}".format(din_name,write_input, i))
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for port in range(total_ports):
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for i in range(abits):
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pin_names.append("{0}{1}_{2}".format(addr_name,port,i))
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#Control signals not finalized.
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for port in range(total_ports):
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pin_names.append("CSB{0}".format(port))
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for port in range(total_ports):
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if (port in read_index) and (port in write_index):
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pin_names.append("WEB{0}".format(port))
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for port in range(total_ports):
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pin_names.append("{0}{1}".format(tech.spice["clk"], port))
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for read_output in read_index:
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for i in range(dbits):
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pin_names.append("{0}{1}_{2}".format(dout_name,read_output, i))
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pin_names.append("{0}".format(tech.spice["vdd_name"]))
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pin_names.append("{0}".format(tech.spice["gnd_name"]))
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return pin_names
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@ -29,51 +29,15 @@ class stimuli():
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(self.process, self.voltage, self.temperature) = corner
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self.device_models = tech.spice["fet_models"][self.process]
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def inst_sram(self, sram, port_signal_names, port_info, abits, dbits, sram_name):
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self.sram_name = "Xsram"
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def inst_sram(self, pins, inst_name):
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""" Function to instatiate an SRAM subckt. """
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pin_names = self.gen_pin_names(port_signal_names, port_info, abits, dbits)
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#Only checking length. This should check functionality as well (TODO) and/or import that information from the SRAM
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debug.check(len(sram.pins) == len(pin_names), "Number of pins generated for characterization do match pins of SRAM\nsram.pins = {0}\npin_names = {1}".format(sram.pins,pin_names))
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self.sf.write("Xsram ")
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for pin in pin_names:
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self.sf.write("{} ".format(self.sram_name))
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for pin in self.sram_pins:
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self.sf.write("{0} ".format(pin))
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self.sf.write("{0}\n".format(sram_name))
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def gen_pin_names(self, port_signal_names, port_info, abits, dbits):
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"""Creates the pins names of the SRAM based on the no. of ports."""
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#This may seem redundant as the pin names are already defined in the sram. However, it is difficult to extract the
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#functionality from the names, so they are recreated. As the order is static, changing the order of the pin names
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#will cause issues here.
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pin_names = []
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(addr_name, din_name, dout_name) = port_signal_names
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(total_ports, write_index, read_index) = port_info
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for write_input in write_index:
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for i in range(dbits):
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pin_names.append("{0}{1}_{2}".format(din_name,write_input, i))
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for port in range(total_ports):
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for i in range(abits):
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pin_names.append("{0}{1}_{2}".format(addr_name,port,i))
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#Control signals not finalized.
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for port in range(total_ports):
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pin_names.append("CSB{0}".format(port))
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for port in range(total_ports):
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if (port in read_index) and (port in write_index):
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pin_names.append("WEB{0}".format(port))
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for port in range(total_ports):
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pin_names.append("{0}{1}".format(tech.spice["clk"], port))
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for read_output in read_index:
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for i in range(dbits):
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pin_names.append("{0}{1}_{2}".format(dout_name,read_output, i))
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pin_names.append("{0}".format(self.vdd_name))
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pin_names.append("{0}".format(self.gnd_name))
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return pin_names
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self.sf.write("{0}\n".format(inst_name))
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def inst_model(self, pins, model_name):
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""" Function to instantiate a generic model with a set of pins """
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@ -26,26 +26,26 @@ class timing_sram_test(openram_test):
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reload(characterizer)
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from characterizer import delay
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from sram_config import sram_config
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# c = sram_config(word_size=1,
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# num_words=16,
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# num_banks=1)
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# c.words_per_row=1
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c = sram_config(word_size=32,
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num_words=256,
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c = sram_config(word_size=1,
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num_words=16,
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num_banks=1)
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c.words_per_row=2
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OPTS.use_tech_delay_chain_size = True
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c.words_per_row=1
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# c = sram_config(word_size=32,
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# num_words=256,
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# num_banks=1)
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# c.words_per_row=2
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#OPTS.use_tech_delay_chain_size = True
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c.recompute_sizes()
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debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
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s = factory.create(module_type="sram", sram_config=c)
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#Exclude things known not to be in critical path.
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#Intended for characterizing read paths. Somewhat hacky implementation
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s.s.bank.bitcell_array.graph_exclude_bits(15,0)
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s.s.bank.graph_exclude_precharge()
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s.s.graph_exclude_addr_dff()
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s.s.graph_exclude_data_dff()
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s.s.graph_exclude_ctrl_dffs()
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# s.s.bank.bitcell_array.graph_exclude_bits(15,0)
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# s.s.bank.graph_exclude_precharge()
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# s.s.graph_exclude_addr_dff()
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# s.s.graph_exclude_data_dff()
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# s.s.graph_exclude_ctrl_dffs()
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# debug.info(1,'pins={}'.format(s.s.pins))
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# import graph_util
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