mirror of https://github.com/VLSIDA/OpenRAM.git
Added analyical model test which compares measured delay to model delay.
This commit is contained in:
Hunter Nichols
parent
f6eefc1728
commit
cc5b347f42
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@ -24,19 +24,7 @@ class bitcell(design.design):
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self.width = bitcell.width
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self.height = bitcell.height
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self.pin_map = bitcell.pin_map
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# def analytical_delay(self, corner, slew, load=0, swing = 0.5):
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# # delay of bit cell is not like a driver(from WL)
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# # so the slew used should be 0
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# # it should not be slew dependent?
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# # because the value is there
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# # the delay is only over half transsmission gate
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# from tech import spice
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# r = spice["min_tx_r"]*3
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# c_para = spice["min_tx_drain_c"]
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# result = self.cal_delay_with_rc(corner, r = r, c = c_para+load, slew = slew, swing = swing)
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# return result
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def analytical_delay(self, corner, slew, load=0, swing = 0.5):
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parasitic_delay = 1
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size = 0.5 #This accounts for bitline being drained thought the access TX and internal node
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@ -9,6 +9,7 @@ import utils
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from globals import OPTS
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from .simulation import simulation
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from .measurements import *
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import logical_effort
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class delay(simulation):
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"""Functions to measure the delay and power of an SRAM at a given address and
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@ -904,8 +905,9 @@ class delay(simulation):
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self.create_measurement_names()
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power = self.analytical_power(slews, loads)
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port_data = self.get_empty_measure_data_dict()
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relative_loads = [logical_effort.convert_farad_to_relative_c(c_farad) for c_farad in loads]
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for slew in slews:
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for load in loads:
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for load in relative_loads:
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self.set_load_slew(load,slew)
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bank_delay = self.sram.analytical_delay(self.corner, self.slew,self.load)
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for port in self.all_ports:
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@ -67,4 +67,8 @@ def calculate_relative_rise_fall_delays(stage_effort_list):
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else:
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total_fall_delay += stage.get_stage_delay()
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return total_rise_delay, total_fall_delay
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def convert_farad_to_relative_c(c_farad):
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"""Converts capacitance in Femto-Farads to relative capacitance."""
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return c_farad*parameter['cap_relative_per_ff']
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@ -1215,37 +1215,6 @@ class bank(design.design):
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offset=control_pos,
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rotate=90)
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# def analytical_delay(self, corner, slew, load):
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# """ return analytical delay of the bank"""
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# results = []
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# decoder_delay = self.row_decoder.analytical_delay(corner, slew, self.wordline_driver.input_load())
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# word_driver_delay = self.wordline_driver.analytical_delay(corner,
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# decoder_delay.slew,
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# self.bitcell_array.input_load())
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# #FIXME: Array delay is the same for every port.
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# bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_delay.slew)
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# #This also essentially creates the same delay for each port. Good structure, no substance
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# for port in self.all_ports:
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# if self.words_per_row > 1:
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# column_mux_delay = self.column_mux_array[port].analytical_delay(corner,
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# bitcell_array_delay.slew,
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# self.sense_amp_array.input_load())
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# else:
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# column_mux_delay = self.return_delay(delay = 0.0, slew=word_driver_delay.slew)
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# bl_t_data_out_delay = self.sense_amp_array.analytical_delay(corner,
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# column_mux_delay.slew,
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# self.bitcell_array.output_load())
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# # output load of bitcell_array is set to be only small part of bl for sense amp.
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# results.append(decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay)
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# return results
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def analytical_delay(self, corner, slew, load):
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""" return analytical delay of the bank. This will track the clock to output path"""
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#FIXME: This delay is determined in the control logic. Should be moved here.
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@ -1255,20 +1224,27 @@ class bank(design.design):
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#FIXME: Array delay is the same for every port.
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word_driver_slew = 0
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bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_slew)
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if self.words_per_row > 1:
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bitline_ext_load = self.column_mux_array[port].get_drain_cin()
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else:
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bitline_ext_load = self.sense_amp_array.get_drain_cin()
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bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_slew, bitline_ext_load)
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bitcell_array_slew = 0
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#This also essentially creates the same delay for each port. Good structure, no substance
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if self.words_per_row > 1:
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sa_load = self.sense_amp_array.get_drain_load()
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column_mux_delay = self.column_mux_array[port].analytical_delay(corner,
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bitcell_array_delay.slew,
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self.sense_amp_array.input_load())
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bitcell_array_slew,
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sa_load)
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else:
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column_mux_delay = []
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column_mux_slew = 0
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sense_amp_delay = self.sense_amp_array.analytical_delay(corner,
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column_mux_slew,
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self.bitcell_array.output_load())
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column_mux_slew,
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load)
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# output load of bitcell_array is set to be only small part of bl for sense amp.
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return bitcell_array_delay + column_mux_delay + sense_amp_delay
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@ -128,27 +128,9 @@ class bitcell_array(design.design):
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inst = self.cell_inst[row,col]
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_power_pin(pin_name, pin.center(), 0, pin.layer)
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# def analytical_delay(self, corner, slew, load=0):
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# from tech import drc
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# wl_wire = self.gen_wl_wire()
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# wl_wire.return_delay_over_wire(slew)
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# wl_to_cell_delay = wl_wire.return_delay_over_wire(slew)
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# # hypothetical delay from cell to bl end without sense amp
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# bl_wire = self.gen_bl_wire()
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# cell_load = 2 * bl_wire.return_input_cap() # we ingore the wire r
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# # hence just use the whole c
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# bl_swing = 0.1
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# cell_delay = self.cell.analytical_delay(corner, wl_to_cell_delay.slew, cell_load, swing = bl_swing)
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# #we do not consider the delay over the wire for now
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# return self.return_delay(cell_delay.delay+wl_to_cell_delay.delay,
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# wl_to_cell_delay.slew)
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self.add_power_pin(pin_name, pin.center(), 0, pin.layer)
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def analytical_delay(self, corner, slew, load=0):
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def analytical_delay(self, corner, slew, load):
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"""Returns relative delay of the bitline in the bitcell array"""
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#The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
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#The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
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@ -4,6 +4,7 @@ from vector import vector
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from sram_factory import factory
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import debug
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from globals import OPTS
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import logical_effort
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class sense_amp_array(design.design):
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"""
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@ -143,3 +144,9 @@ class sense_amp_array(design.design):
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"""Get the relative capacitance of all the sense amp enable connections in the array"""
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sense_amp_en_cin = self.amp.get_en_cin()
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return sense_amp_en_cin * self.word_size
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def get_drain_cin(self):
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"""Get the relative capacitance of the drain of the PMOS isolation TX"""
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#Estimated as half a parasitic delay.
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drain_parasitics = .5
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return drain_parasitics * logical_effort.logical_effort.pinv
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@ -7,6 +7,7 @@ import math
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from vector import vector
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from sram_factory import factory
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from globals import OPTS
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import logical_effort
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class single_level_column_mux_array(design.design):
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"""
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@ -232,5 +233,11 @@ class single_level_column_mux_array(design.design):
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"""Returns relative delay that the column mux adds"""
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#Single level column mux will add parasitic loads from other mux pass transistors and the sense amp.
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drain_parasitics = .5 #Assumed parasitics from unused TXs
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array_load = drain_parasitics*self.words_per_row*logical_effort.pinv
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return [self.mux.analytical_delay(corner, slew, load+array_load)]
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array_load = drain_parasitics*self.words_per_row*logical_effort.logical_effort.pinv
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return [self.mux.analytical_delay(corner, slew, load+array_load)]
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def get_drain_cin(self):
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"""Get the relative capacitance of the drain of the NMOS pass TX"""
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#Estimated as half a parasitic delay.
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drain_parasitics = .5
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return drain_parasitics * logical_effort.logical_effort.pinv
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@ -11,25 +11,22 @@ import globals
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from globals import OPTS
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import debug
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class delay_model_test(openram_test):
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class model_delay_sram_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.spice_name="hspice"
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#OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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debug.info(1, "Trimming disabled for this test. Simulation could be slow.")
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import model_check
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from characterizer import delay
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=4,
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c = sram_config(word_size=1,
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num_words=16,
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num_banks=1)
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c.words_per_row=1
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@ -45,15 +42,32 @@ class delay_model_test(openram_test):
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debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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mc = model_check(s.s, tempspice, corner)
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d = delay(s.s, tempspice, corner)
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import tech
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loads = [tech.spice["msflop_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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sram_data = mc.analyze(probe_address, probe_data, slews, loads)
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#Combine info about port into all data
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#debug.info(1,"Data:\n{}".format(wl_data))
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spice_data, port_data = d.analyze(probe_address, probe_data, slews, loads)
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spice_data.update(port_data[0])
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model_data, port_data = d.analytical_delay(slews, loads)
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model_data.update(port_data[0])
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#Only compare the delays
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spice_delays = {key:value for key, value in spice_data.items() if 'delay' in key}
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model_delays = {key:value for key, value in model_data.items() if 'delay' in key}
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debug.info(1,"Spice Delays={}".format(spice_delays))
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debug.info(1,"Model Delays={}".format(model_delays))
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if OPTS.tech_name == "freepdk45":
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error_tolerance = .25
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elif OPTS.tech_name == "scn4m_subm":
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error_tolerance = .25
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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self.assertTrue(len(spice_delays.keys())==len(model_delays.keys()))
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self.assertTrue(self.check_golden_data(spice_delays,model_delays,error_tolerance))
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globals.end_openram()
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# run the test from the command line
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@ -1,81 +0,0 @@
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#!/usr/bin/env python3
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"""
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Run a regression test on various srams
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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@unittest.skip("SKIPPING 27_worst_case_delay_test")
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class worst_case_timing_sram_test(openram_test):
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def runTest(self):
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OPTS.tech_name = "freepdk45"
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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OPTS.check_lvsdrc = True
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import worst_case
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if not OPTS.spice_exe:
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debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
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word_size, num_words, num_banks = 2, 16, 1
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=word_size,
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num_words=num_words,
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num_banks=num_banks)
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c.words_per_row=1
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c.recompute_sizes()
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debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format(
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word_size, num_words, num_banks))
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s = sram(c, name="sram1")
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sp_netlist_file = OPTS.openram_temp + "temp.sp"
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s.sp_write(sp_netlist_file)
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if OPTS.use_pex:
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gdsname = OPTS.output_path + s.name + ".gds"
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s.gds_write(gdsname)
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import verify
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reload(verify)
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# Output the extracted design if requested
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sp_pex_file = OPTS.output_path + s.name + "_pex.sp"
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verify.run_pex(s.name, gdsname, sp_netlist_file, output=sp_pex_file)
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sp_sim_file = sp_pex_file
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debug.info(1, "Performing spice simulations with backannotated spice file.")
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else:
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sp_sim_file = sp_netlist_file
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debug.info(1, "Performing spice simulations with spice netlist.")
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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wc = worst_case(s.s, sp_sim_file, corner)
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import tech
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loads = [tech.spice["msflop_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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probe_address = "1" * s.s.addr_size
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probe_data = s.s.word_size - 1
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wc.analyze(probe_address, probe_data, slews, loads)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@ -336,7 +336,8 @@ spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input na
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spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor.
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#Parameters related to sense amp enable timing and delay chain/RBL sizing
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parameter['le_tau'] = 8 #In pico-seconds. FIXME:This is an assumed value, not measured.
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parameter['le_tau'] = 2.25 #In pico-seconds.
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parameter['cap_relative_per_ff'] = 7.5 #Units of Relative Capacitance/ Femto-Farad
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parameter["static_delay_stages"] = 4
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parameter["static_fanout_per_stage"] = 3
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parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]]
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@ -302,13 +302,14 @@ spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input na
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spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor.
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#Logical Effort relative values for the Handmade cells
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parameter['le_tau'] = 40 #In pico-seconds. FIXME:This is an assumed value, not measured.
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parameter['le_tau'] = 23 #In pico-seconds.
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parameter["min_inv_para_delay"] = .73 #In relative delay units
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parameter['cap_relative_per_ff'] = .91 #Units of Relative Capacitance/ Femto-Farad
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parameter["static_delay_stages"] = 4
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parameter["static_fanout_per_stage"] = 3
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parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]]
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parameter["dff_clk_cin"] = 27.5
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parameter["6tcell_wl_cin"] = 2
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parameter["min_inv_para_delay"] = .5
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parameter["dff_clk_cin"] = 27.5 #In relative capacitance units
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parameter["6tcell_wl_cin"] = 2 #In relative capacitance units
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parameter["sa_en_pmos_size"] = 24*_lambda_
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parameter["sa_en_nmos_size"] = 9*_lambda_
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parameter["sa_inv_pmos_size"] = 18*_lambda_
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