Rename config_20 to config since it is used in all tests

compiler/tests/01_library_drc_test.py

@@ -12,7 +12,7 @@ import debug
 class library_drc_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import verify
 
         (gds_dir, gds_files) = setup_files()

compiler/tests/02_library_lvs_test.py

@@ -12,7 +12,7 @@ import debug
 class library_lvs_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import verify
 
         (gds_dir, sp_dir, allnames) = setup_files()

compiler/tests/03_contact_test.py

@@ -12,7 +12,7 @@ import debug
 class contact_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import contact
 
 

compiler/tests/03_path_test.py

@@ -12,7 +12,7 @@ import debug
 class path_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import wire_path
         import tech
         import design

compiler/tests/03_ptx_1finger_nmos_test.py

@@ -13,7 +13,7 @@ import debug
 class ptx_1finger_nmos_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import tech
 
         debug.info(2, "Checking min size NMOS with 1 finger")

compiler/tests/03_ptx_1finger_pmos_test.py

@@ -13,7 +13,7 @@ import debug
 class ptx_1finger_pmos_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import tech
 
         debug.info(2, "Checking min size PMOS with 1 finger")

compiler/tests/03_ptx_3finger_nmos_test.py

@@ -13,7 +13,7 @@ import debug
 class ptx_3finger_nmos_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import tech
 
         debug.info(2, "Checking three fingers NMOS")

compiler/tests/03_ptx_3finger_pmos_test.py

@@ -13,7 +13,7 @@ import debug
 class ptx_3finger_pmos_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import tech
 
         debug.info(2, "Checking three fingers PMOS")

compiler/tests/03_ptx_4finger_nmos_test.py

@@ -13,7 +13,7 @@ import debug
 class ptx_4finger_nmos_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import tech
 
         debug.info(2, "Checking three fingers NMOS")

compiler/tests/03_ptx_4finger_pmos_test.py

@@ -13,7 +13,7 @@ import debug
 class ptx_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import tech
 
         debug.info(2, "Checking three fingers PMOS")

compiler/tests/03_wire_test.py

@@ -12,7 +12,7 @@ import debug
 class wire_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import wire
         import tech
         import design

compiler/tests/04_pand2_test.py

@@ -15,7 +15,7 @@ import debug
 class pand2_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         global verify
         import verify
 

compiler/tests/04_pbitcell_test.py

@@ -16,7 +16,7 @@ from sram_factory import factory
 class pbitcell_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         OPTS.num_rw_ports=1
         OPTS.num_w_ports=1

compiler/tests/04_pbuf_test.py

@@ -15,7 +15,7 @@ import debug
 class pbuf_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
         a = factory.create(module_type="pbuf", size=8)

compiler/tests/04_pdriver_test.py

@@ -15,7 +15,7 @@ import debug
 class pdriver_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
         # a tests the error message for specifying conflicting conditions

compiler/tests/04_pinv_10x_test.py

@@ -15,7 +15,7 @@ import debug
 class pinv_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Checking 8x inverter")
         tx = factory.create(module_type="pinv", size=8)

compiler/tests/04_pinv_1x_beta_test.py

@@ -15,7 +15,7 @@ import debug
 class pinv_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Checking 1x beta=3 size inverter")
         tx = factory.create(module_type="pinv", size=1, beta=3)

compiler/tests/04_pinv_1x_test.py

@@ -14,7 +14,7 @@ import debug
 class pinv_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Checking 1x size inverter")
         tx = factory.create(module_type="pinv", size=1)

compiler/tests/04_pinv_2x_test.py

@@ -15,7 +15,7 @@ import debug
 class pinv_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Checking 2x size inverter")
         tx = factory.create(module_type="pinv", size=2)

compiler/tests/04_pinvbuf_test.py

@@ -15,7 +15,7 @@ import debug
 class pinvbuf_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
         a = factory.create(module_type="pinvbuf", size=8)

compiler/tests/04_pnand2_test.py

@@ -17,7 +17,7 @@ import debug
 class pnand2_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Checking 2-input nand gate")
         tx = factory.create(module_type="pnand2", size=1)

compiler/tests/04_pnand3_test.py

@@ -17,7 +17,7 @@ import debug
 class pnand3_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Checking 3-input nand gate")
         tx = factory.create(module_type="pnand3", size=1)

compiler/tests/04_pnor2_test.py

@@ -17,7 +17,7 @@ import debug
 class pnor2_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Checking 2-input nor gate")
         tx = factory.create(module_type="pnor2", size=1)

compiler/tests/04_precharge_test.py

@@ -15,7 +15,7 @@ import debug
 class precharge_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         
         # check precharge in single port
         debug.info(2, "Checking precharge for handmade bitcell")

compiler/tests/04_replica_pbitcell_test.py

@@ -15,7 +15,7 @@ import debug
 class replica_pbitcell_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import replica_pbitcell
         
         OPTS.bitcell = "pbitcell"

compiler/tests/04_single_level_column_mux_test.py

@@ -17,7 +17,7 @@ import debug
 class single_level_column_mux_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         
         # check single level column mux in single port
         debug.info(2, "Checking column mux")

compiler/tests/05_bitcell_1rw_1r_array_test.py

@@ -17,7 +17,7 @@ import debug
 class bitcell_1rw_1r_array_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Testing 4x4 array for cell_1rw_1r")
         OPTS.bitcell = "bitcell_1rw_1r"

compiler/tests/05_bitcell_array_test.py

@@ -17,7 +17,7 @@ import debug
 class array_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Testing 4x4 array for 6t_cell")
         a = factory.create(module_type="bitcell_array", cols=4, rows=4)

compiler/tests/05_pbitcell_array_test.py

@@ -16,7 +16,7 @@ import debug
 class pbitcell_array_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
         OPTS.bitcell = "pbitcell"

compiler/tests/06_hierarchical_decoder_test.py

@@ -15,7 +15,7 @@ import debug
 class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         # Doesn't require hierarchical decoder
         # debug.info(1, "Testing 4 row sample for hierarchical_decoder")
         # a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4)

compiler/tests/06_hierarchical_predecode2x4_test.py

@@ -15,7 +15,7 @@ import debug
 class hierarchical_predecode2x4_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         # checking hierarchical precode 2x4 for single port
         debug.info(1, "Testing sample for hierarchy_predecode2x4")

compiler/tests/06_hierarchical_predecode3x8_test.py

@@ -15,7 +15,7 @@ import debug
 class hierarchical_predecode3x8_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         # checking hierarchical precode 3x8 for single port
         debug.info(1, "Testing sample for hierarchy_predecode3x8")

compiler/tests/07_single_level_column_mux_array_test.py

@@ -14,7 +14,7 @@ import debug
 class single_level_column_mux_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import single_level_column_mux_array
         
         # check single level column mux array in single port

compiler/tests/08_precharge_array_test.py

@@ -15,7 +15,7 @@ import debug
 class precharge_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         # check precharge array in single port
         debug.info(2, "Checking 3 column precharge")

compiler/tests/08_wordline_driver_test.py

@@ -17,7 +17,7 @@ import debug
 class wordline_driver_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")

compiler/tests/09_sense_amp_array_test.py

@@ -15,7 +15,7 @@ import debug
 class sense_amp_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         # check sense amp array for single port
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")

compiler/tests/10_write_driver_array_test.py

@@ -15,7 +15,7 @@ import debug
 class write_driver_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8")

compiler/tests/11_dff_array_test.py

@@ -15,7 +15,7 @@ import debug
 class dff_array_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Testing dff_array for 3x3")
         a = factory.create(module_type="dff_array", rows=3, columns=3)

compiler/tests/11_dff_buf_array_test.py

@@ -15,7 +15,7 @@ import debug
 class dff_buf_array_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Testing dff_buf_array for 3x3")
         a = factory.create(module_type="dff_buf_array", rows=3, columns=3)

compiler/tests/11_dff_buf_test.py

@@ -15,7 +15,7 @@ import debug
 class dff_buf_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Testing dff_buf 4x 8x")
         a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8)

compiler/tests/12_tri_gate_array_test.py

@@ -15,7 +15,7 @@ import debug
 class tri_gate_array_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")
         a = factory.create(module_type="tri_gate_array", columns=8, word_size=8)

compiler/tests/13_delay_chain_test.py

@@ -15,7 +15,7 @@ import debug
 class delay_chain_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(2, "Testing delay_chain")
         a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4])

compiler/tests/14_replica_bitline_multiport_test.py

@@ -15,7 +15,7 @@ import debug
 class replica_bitline_multiport_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         stages=4
         fanout=4

compiler/tests/14_replica_bitline_test.py

@@ -15,7 +15,7 @@ import debug
 class replica_bitline_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         # check replica bitline in single port
         stages=4

compiler/tests/16_control_logic_test.py

@@ -15,7 +15,7 @@ import debug
 class control_logic_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         import control_logic
         import tech
 

compiler/tests/19_bank_select_test.py

@@ -15,7 +15,7 @@ import debug
 class bank_select_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         debug.info(1, "No column mux, rw control logic")
         a = factory.create(module_type="bank_select", port="rw")

compiler/tests/19_multi_bank_test.py

@@ -16,7 +16,7 @@ import debug
 class multi_bank_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
 
         c = sram_config(word_size=4,

compiler/tests/19_pmulti_bank_test.py

@@ -16,7 +16,7 @@ import debug
 class multi_bank_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         OPTS.bitcell = "pbitcell"
 

compiler/tests/19_psingle_bank_test.py

@@ -16,7 +16,7 @@ import debug
 class psingle_bank_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from bank import bank
         from sram_config import sram_config
         OPTS.bitcell = "pbitcell"

compiler/tests/19_single_bank_1rw_1r_test.py

@@ -15,7 +15,7 @@ import debug
 class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.num_rw_ports = 1

compiler/tests/19_single_bank_test.py

@@ -15,7 +15,7 @@ import debug
 class single_bank_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
 
         c = sram_config(word_size=4,

compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py

@@ -16,7 +16,7 @@ import debug
 class psram_1bank_2mux_1rw_1w_test(openram_test):
 
     def runTest(self):        
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"

compiler/tests/20_psram_1bank_2mux_1w_1r_test.py

@@ -16,7 +16,7 @@ import debug
 class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):        
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"

compiler/tests/20_psram_1bank_2mux_test.py

@@ -16,7 +16,7 @@ import debug
 class psram_1bank_2mux_test(openram_test):
 
     def runTest(self):        
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"

compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py

@@ -15,7 +15,7 @@ import debug
 class psram_1bank_4mux_1rw_1r_test(openram_test):
 
     def runTest(self):        
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"

compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py

@@ -15,7 +15,7 @@ import debug
 class sram_1bank_2mux_1rw_1r_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         
         OPTS.bitcell = "bitcell_1rw_1r"

compiler/tests/20_sram_1bank_2mux_1w_1r_test.py

@@ -16,7 +16,7 @@ import debug
 class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):        
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         OPTS.bitcell = "bitcell_1w_1r"
         OPTS.replica_bitcell="replica_bitcell_1w_1r"

compiler/tests/20_sram_1bank_2mux_test.py

@@ -16,7 +16,7 @@ import debug
 class sram_1bank_2mux_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         c = sram_config(word_size=4,
                         num_words=32,

compiler/tests/20_sram_1bank_4mux_test.py

@@ -16,7 +16,7 @@ import debug
 class sram_1bank_4mux_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         c = sram_config(word_size=4,
                         num_words=64,

compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py

@@ -15,7 +15,7 @@ import debug
 class sram_1bank_8mux_1rw_1r_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
 
         OPTS.bitcell = "bitcell_1rw_1r"

compiler/tests/20_sram_1bank_8mux_test.py

@@ -16,7 +16,7 @@ import debug
 class sram_1bank_8mux_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         c = sram_config(word_size=2,
                         num_words=128,

compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py

@@ -15,7 +15,7 @@ import debug
 class sram_1bank_nomux_1rw_1r_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         
         OPTS.bitcell = "bitcell_1rw_1r"

compiler/tests/20_sram_1bank_nomux_test.py

@@ -16,7 +16,7 @@ import debug
 class sram_1bank_nomux_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         c = sram_config(word_size=4,
                         num_words=16,

compiler/tests/20_sram_2bank_test.py

@@ -16,7 +16,7 @@ import debug
 class sram_2bank_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         from sram_config import sram_config
         c = sram_config(word_size=16,
                         num_words=32,

compiler/tests/21_hspice_delay_test.py

@@ -15,7 +15,7 @@ import debug
 class timing_sram_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True

compiler/tests/21_hspice_setuphold_test.py

@@ -15,7 +15,7 @@ import debug
 class timing_setup_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True

compiler/tests/21_ngspice_delay_test.py

@@ -15,7 +15,7 @@ import debug
 class timing_sram_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True

compiler/tests/21_ngspice_setuphold_test.py

@@ -15,7 +15,7 @@ import debug
 class timing_setup_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True

compiler/tests/22_psram_1bank_2mux_func_test.py

@@ -16,7 +16,7 @@ import debug
 class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False

compiler/tests/22_psram_1bank_4mux_func_test.py

@@ -16,7 +16,7 @@ import debug
 class psram_1bank_4mux_func_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False

compiler/tests/22_psram_1bank_8mux_func_test.py

@@ -16,7 +16,7 @@ import debug
 class psram_1bank_8mux_func_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False

compiler/tests/22_psram_1bank_nomux_func_test.py

@@ -16,7 +16,7 @@ import debug
 class psram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False

compiler/tests/22_sram_1bank_2mux_func_test.py

@@ -16,7 +16,7 @@ import debug
 class sram_1bank_2mux_func_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False

compiler/tests/22_sram_1bank_4mux_func_test.py

@@ -16,7 +16,7 @@ import debug
 class sram_1bank_4mux_func_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False

compiler/tests/22_sram_1bank_8mux_func_test.py

@@ -16,7 +16,7 @@ import debug
 class sram_1bank_8mux_func_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False

compiler/tests/22_sram_1bank_nomux_func_test.py

@@ -16,7 +16,7 @@ import debug
 class sram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         

compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py

@@ -16,7 +16,7 @@ import debug
 class psram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False

compiler/tests/23_lib_sram_model_corners_test.py

@@ -14,7 +14,7 @@ import debug
 class model_corners_lib_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         from characterizer import lib
         from sram import sram

compiler/tests/23_lib_sram_model_test.py

@@ -14,7 +14,7 @@ import debug
 class lib_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         from characterizer import lib
         from sram import sram

compiler/tests/23_lib_sram_prune_test.py

@@ -14,7 +14,7 @@ import debug
 class lib_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.trim_netlist = True
 

compiler/tests/23_lib_sram_test.py

@@ -14,7 +14,7 @@ import debug
 class lib_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.trim_netlist = False
 

compiler/tests/24_lef_sram_test.py

@@ -15,7 +15,7 @@ import debug
 class lef_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         from sram import sram
         from sram_config import sram_config

compiler/tests/25_verilog_sram_test.py

@@ -14,7 +14,7 @@ import debug
 class verilog_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         from sram import sram
         from sram_config import sram_config

compiler/tests/26_pex_test.py

@@ -16,7 +16,7 @@ import debug
 class sram_func_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
 
         OPTS.use_pex = True
 

compiler/tests/27_worst_case_delay_test.py

@@ -17,7 +17,7 @@ class worst_case_timing_sram_test(openram_test):
 
     def runTest(self):
         OPTS.tech_name = "freepdk45"
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True

compiler/tests/28_delay_model_test.py

@@ -15,7 +15,7 @@ import debug
 class delay_model_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_20_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True

compiler/tests/30_openram_test.py

@@ -19,7 +19,7 @@ class openram_test(openram_test):
 
     def runTest(self):
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
-        globals.init_openram("{0}/tests/config_20_{1}".format(OPENRAM_HOME,OPTS.tech_name))
+        globals.init_openram("{0}/tests/config_{1}".format(OPENRAM_HOME,OPTS.tech_name))
         
         debug.info(1, "Testing top-level openram.py with 2-bit, 16 word SRAM.")
         out_file = "testsram"
@@ -49,7 +49,7 @@ class openram_test(openram_test):
             exe_name = "{0}/openram.py ".format(OPENRAM_HOME)
         else:
             exe_name = "coverage run -p {0}/openram.py ".format(OPENRAM_HOME) 
-        config_name = "{0}config_20_{1}.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name)
+        config_name = "{0}config_{1}.py".format(OPENRAM_HOME + "/tests/",OPTS.tech_name)
         cmd = "{0} -n -o {1} -p {2} {3} {4} 2>&1 > {5}/output.log".format(exe_name,
                                                                           out_file,
                                                                           out_path,