Add link to presentation in README

This commit is contained in:
Matt Guthaus 2019-03-06 08:29:43 -08:00
parent cfc14f327e
commit acf2798a18
7 changed files with 52 additions and 38 deletions

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@ -25,6 +25,13 @@ other views necessary to use SRAMs in ASIC design. OpenRAM supports
integration in both commercial and open-source flows with both
predictive and fabricable technologies.
# Documentation
Please take a look at our presentation We have created a detailed
presentation that serves as our [documentation][documentation].
This is the most up-to-date information, so please let us know if you see
things that need to be fixed.
# Basic Setup
## Docker Image
@ -197,6 +204,7 @@ Each specific technology (e.g., [FreePDK45]) should be a subdirectory
# Further Help
+ [Additional hints](./HINTS.md)
+ [Documentation][documentation]
+ [OpenRAM Slack Workspace][Slack]
+ [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe])
+ [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe])
@ -233,7 +241,7 @@ If I forgot to add you, please let me know!
[Github pull request]: https://github.com/VLSIDA/PrivateRAM/pulls
[Github projects]: https://github.com/VLSIDA/PrivateRAM
[email me]: mailto:mrg+openram@ucsc.edu
[documentation]: https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing
[dev-group]: mailto:openram-dev-group@ucsc.edu
[user-group]: mailto:openram-user-group@ucsc.edu
[dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu

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@ -7,19 +7,20 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
class ptx_1finger_nmos_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
import tech
debug.info(2, "Checking min size NMOS with 1 finger")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=1,
tx_type="nmos")
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=1,
tx_type="nmos")
self.local_drc_check(fet)
globals.end_openram()

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@ -7,19 +7,20 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
class ptx_1finger_pmos_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
import tech
debug.info(2, "Checking min size PMOS with 1 finger")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=1,
tx_type="pmos")
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=1,
tx_type="pmos")
self.local_drc_check(fet)
globals.end_openram()

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@ -7,21 +7,22 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
class ptx_3finger_nmos_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
import tech
debug.info(2, "Checking three fingers NMOS")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=3,
tx_type="nmos",
connect_active=True,
connect_poly=True)
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=3,
tx_type="nmos",
connect_active=True,
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()

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@ -7,21 +7,22 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
class ptx_3finger_pmos_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
import tech
debug.info(2, "Checking three fingers PMOS")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=3,
tx_type="pmos",
connect_active=True,
connect_poly=True)
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=3,
tx_type="pmos",
connect_active=True,
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()

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@ -7,21 +7,22 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
class ptx_4finger_nmos_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
import tech
debug.info(2, "Checking three fingers NMOS")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=4,
tx_type="nmos",
connect_active=True,
connect_poly=True)
fet = factory.create(module_type="ptx",
width= tech.drc["minwidth_tx"],
mults=4,
tx_type="nmos",
connect_active=True,
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()

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@ -7,21 +7,22 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
import tech
debug.info(2, "Checking three fingers PMOS")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=4,
tx_type="pmos",
connect_active=True,
connect_poly=True)
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=4,
tx_type="pmos",
connect_active=True,
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()