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Remove factory from lef and verilog tests

This commit is contained in:
Matt Guthaus 2019-03-08 09:22:48 -08:00
parent bd256d33d6
commit 196710ec3e
2 changed files with 8 additions and 4 deletions
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6
compiler/tests/24_lef_sram_test.py
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@ -9,7 +9,6 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 24_lef_sram_test")
@ -18,6 +17,7 @@ class lef_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
@ -25,7 +25,9 @@ class lef_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
gdsfile = s.name + ".gds"
leffile = s.name + ".lef"

6
compiler/tests/25_verilog_sram_test.py
View File

@ -9,7 +9,6 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class verilog_test(openram_test):
@ -17,6 +16,7 @@ class verilog_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=16,
@ -24,7 +24,9 @@ class verilog_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank")
s = factory.create(module_type="sram", sram_config=c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
vfile = s.name + ".v"
vname = OPTS.openram_temp + vfile