mirror of https://github.com/VLSIDA/OpenRAM.git
Copy 1rw/1r cell to 1w/1r.
This commit is contained in:
Matt Guthaus
parent
6c9ae1c659
commit
6cdc870091
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@ -0,0 +1,106 @@
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import design
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import debug
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import utils
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from tech import GDS,layer,parameter,drc
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class bitcell_1w_1r(design.design):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("cell_1w_1r", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "cell_1w_1r", GDS["unit"])
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def __init__(self, name=""):
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# Ignore the name argument
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design.design.__init__(self, "cell_1w_1r")
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debug.info(2, "Create bitcell with 1W and 1R Port")
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self.width = bitcell_1w_1r.width
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self.height = bitcell_1w_1r.height
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self.pin_map = bitcell_1w_1r.pin_map
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def analytical_delay(self, slew, load=0, swing = 0.5):
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# delay of bit cell is not like a driver(from WL)
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# so the slew used should be 0
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# it should not be slew dependent?
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# because the value is there
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# the delay is only over half transsmission gate
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from tech import spice
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r = spice["min_tx_r"]*3
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c_para = spice["min_tx_drain_c"]
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result = self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew, swing = swing)
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return result
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def list_bitcell_pins(self, col, row):
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""" Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
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bitcell_pins = ["bl0_{0}".format(col),
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"br0_{0}".format(col),
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"bl1_{0}".format(col),
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"br1_{0}".format(col),
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"wl0_{0}".format(row),
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"wl1_{0}".format(row),
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"vdd",
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"gnd"]
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return bitcell_pins
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def list_all_wl_names(self):
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""" Creates a list of all wordline pin names """
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row_pins = ["wl0", "wl1"]
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return row_pins
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def list_all_bitline_names(self):
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""" Creates a list of all bitline pin names (both bl and br) """
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column_pins = ["bl0", "br0", "bl1", "br1"]
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return column_pins
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def list_all_bl_names(self):
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""" Creates a list of all bl pins names """
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column_pins = ["bl0", "bl1"]
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return column_pins
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def list_all_br_names(self):
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""" Creates a list of all br pins names """
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column_pins = ["br0", "br1"]
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return column_pins
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def list_read_bl_names(self):
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""" Creates a list of bl pin names associated with read ports """
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column_pins = ["bl0", "bl1"]
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return column_pins
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def list_read_br_names(self):
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""" Creates a list of br pin names associated with read ports """
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column_pins = ["br0", "br1"]
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return column_pins
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def list_write_bl_names(self):
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""" Creates a list of bl pin names associated with write ports """
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column_pins = ["bl0"]
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return column_pins
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def list_write_br_names(self):
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""" Creates a list of br pin names asscociated with write ports"""
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column_pins = ["br0"]
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return column_pins
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def analytical_power(self, proc, vdd, temp, load):
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"""Bitcell power in nW. Only characterizes leakage."""
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from tech import spice
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leakage = spice["bitcell_leakage"]
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dynamic = 0 #temporary
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total_power = self.return_power(dynamic, leakage)
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return total_power
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def get_wl_cin(self):
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"""Return the relative capacitance of the access transistor gates"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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#Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
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#FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
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access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
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return 2*access_tx_cin
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@ -0,0 +1,32 @@
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import design
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import debug
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import utils
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from tech import GDS,layer,drc,parameter
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class replica_bitcell_1w_1r(design.design):
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"""
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A single bit cell which is forced to store a 0.
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This module implements the single memory cell used in the design. It
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is a hand-made cell, so the layout and netlist should be available in
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the technology library. """
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pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
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(width,height) = utils.get_libcell_size("replica_cell_1w_1r", GDS["unit"], layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1w_1r", GDS["unit"])
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def __init__(self, name=""):
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# Ignore the name argument
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design.design.__init__(self, "replica_cell_1w_1r")
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debug.info(2, "Create replica bitcell 1w+1r object")
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self.width = replica_bitcell_1w_1r.width
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self.height = replica_bitcell_1w_1r.height
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self.pin_map = replica_bitcell_1w_1r.pin_map
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def get_wl_cin(self):
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"""Return the relative capacitance of the access transistor gates"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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#Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
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#FIXME: sizing is not accurate with the handmade cell. Change once cell widths are fixed.
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access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
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return 2*access_tx_cin
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#!/usr/bin/env python3
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"""
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Run a regression test on a 1 bank SRAM
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
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class psram_1bank_2mux_1w_1r_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from sram import sram
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from sram_config import sram_config
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OPTS.bitcell = "bitcell_1w_1r"
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OPTS.replica_bitcell="replica_bitcell_1w_1r"
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OPTS.num_rw_ports = 0
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OPTS.num_w_ports = 1
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OPTS.num_r_ports = 1
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c = sram_config(word_size=4,
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num_words=32,
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num_banks=1)
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c.num_words=32
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c.words_per_row=2
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c.recompute_sizes()
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debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.words_per_row,
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c.num_banks))
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a = sram(c, "sram")
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self.local_check(a, final_verification=True)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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Binary file not shown.
Binary file not shown.
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@ -0,0 +1,14 @@
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.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
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MM9 RA_to_R_right wl1 br1 gnd NMOS_VTG W=180.0n L=50n m=1
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MM8 RA_to_R_right Q gnd gnd NMOS_VTG W=180.0n L=50n m=1
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MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
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MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
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MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
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MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
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MM1 Q Q_bar gnd gnd NMOS_VTG W=270.0n L=50n m=1
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MM0 Q_bar Q gnd gnd NMOS_VTG W=270.0n L=50n m=1
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MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
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MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
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.ENDS
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Binary file not shown.
Binary file not shown.
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@ -0,0 +1,41 @@
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timestamp 1536091415
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version 8.2
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tech scmos
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style TSMC0.35um(tsmc35)from:t11c
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scale 1000 1 5
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resistclasses 3700 2800 1018000 1018000 1 6000 6000 80 70 80 40
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node "comment_0_0#" 0 0 0 0 bb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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node "br" 6 -1.43219e-14 96 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3456 464 0 0 0 0
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node "bl" 6 -8.88178e-16 40 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3200 432 0 0 0 0
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node "wl" 115 -2.89546e-13 -8 12 p 0 0 0 0 0 0 0 0 0 0 1536 360 0 0 2496 344 0 0 0 0 0 0
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node "a_36_40#" 140 -3.51719e-13 36 40 ndif 960 144 304 72 0 0 0 0 0 0 1984 424 0 0 2048 288 0 0 0 0 0 0
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node "a_28_32#" 160 -8.06466e-13 28 32 p 960 144 304 72 0 0 0 0 0 0 2000 456 0 0 1920 272 0 0 0 0 0 0
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node "gnd" 41 -27.888 -32 -32 pw 1792 240 512 128 0 0 0 0 29600 696 0 0 0 0 2688 400 6400 864 0 0 0 0
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equiv "gnd" "gnd"
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node "vdd" 2340 2596 -32 116 nw 256 64 800 176 17600 576 0 0 0 0 0 0 0 0 3456 464 256 64 0 0 0 0
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cap "wl" "bl" 189.768
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cap "a_36_40#" "br" 17.59
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cap "wl" "br" 189.768
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cap "vdd" "bl" 135.015
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cap "bl" "br" 27.492
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cap "vdd" "br" 117.084
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cap "gnd" "a_28_32#" 880.405
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cap "gnd" "a_36_40#" 401.284
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cap "a_28_32#" "a_36_40#" 272.793
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cap "gnd" "wl" 1198.41
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cap "gnd" "bl" 712.11
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cap "a_28_32#" "wl" 108.364
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cap "vdd" "gnd" 510.12
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cap "gnd" "br" 698.471
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cap "a_36_40#" "wl" 108.364
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cap "a_28_32#" "bl" 104.205
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cap "vdd" "a_28_32#" 430.812
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cap "a_36_40#" "bl" 29.396
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cap "a_28_32#" "br" 308.488
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cap "vdd" "a_36_40#" 709.108
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fet nfet 96 12 97 13 128 48 "gnd" "wl" 16 0 "br" 16 0 "a_28_32#" 16 0
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fet nfet 40 12 41 13 128 48 "gnd" "wl" 16 0 "bl" 16 0 "a_36_40#" 16 0
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fet nfet 116 40 117 41 256 80 "gnd" "a_36_40#" 16 0 "a_28_32#" 32 0 "gnd" 32 0
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fet nfet 28 40 29 41 256 80 "gnd" "a_28_32#" 16 0 "gnd" 32 0 "a_36_40#" 32 0
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fet pfet 108 148 109 149 192 56 "vdd" "a_36_40#" 32 0 "a_28_32#" 12 0 "vdd" 12 0
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fet pfet 28 148 29 149 192 56 "vdd" "a_28_32#" 32 0 "vdd" 12 0 "a_36_40#" 12 0
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@ -0,0 +1,15 @@
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* SPICE3 file created from cell_6t.ext - technology: scmos
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M1000 a_36_40# a_28_32# vdd vdd pfet w=0.6u l=0.8u
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+ ad=0.76p pd=3.6u as=2p ps=8.8u
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M1001 vdd a_36_40# a_28_32# vdd pfet w=0.6u l=0.8u
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+ ad=0p pd=0u as=0.76p ps=3.6u
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M1002 a_36_40# a_28_32# gnd gnd nfet w=1.6u l=0.4u
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+ ad=2.4p pd=7.2u as=4.48p ps=12u
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M1003 gnd a_36_40# a_28_32# gnd nfet w=1.6u l=0.4u
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+ ad=0p pd=0u as=2.4p ps=7.2u
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M1004 a_36_40# wl bl gnd nfet w=0.8u l=0.4u
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+ ad=0p pd=0u as=0.8p ps=3.6u
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M1005 a_28_32# wl br gnd nfet w=0.8u l=0.4u
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+ ad=0p pd=0u as=0.8p ps=3.6u
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C0 vdd 0 2.60fF
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@ -0,0 +1,35 @@
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timestamp 1541443051
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version 8.2
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tech scmos
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style TSMC0.35um(tsmc35)from:t11c
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scale 1000 1 5
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resistclasses 3700 2800 1018000 1018000 1 6000 6000 80 70 80 40
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node "comment_0_0#" 0 0 0 0 bb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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node "br" 6 1.40998e-14 96 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3456 464 0 0 0 0
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node "bl" 6 -8.88178e-16 40 -8 ndc 320 72 0 0 0 0 0 0 0 0 0 0 0 0 512 96 3200 432 0 0 0 0
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node "wl" 115 -2.89546e-13 -8 12 p 0 0 0 0 0 0 0 0 0 0 1536 360 0 0 2496 344 0 0 0 0 0 0
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node "a_36_40#" 140 -3.51719e-13 36 40 ndif 960 144 304 72 0 0 0 0 0 0 1984 424 0 0 2048 288 0 0 0 0 0 0
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node "gnd" 41 -27.888 -32 -32 pw 1792 240 512 128 0 0 0 0 29600 696 0 0 0 0 2688 400 6400 864 0 0 0 0
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equiv "gnd" "gnd"
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node "vdd" 2517 2596 -32 116 nw 1216 208 1104 248 17600 576 0 0 0 0 2000 456 0 0 5632 736 256 64 0 0 0 0
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cap "vdd" "br" 442.06
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cap "bl" "wl" 189.768
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cap "gnd" "br" 698.471
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cap "bl" "a_36_40#" 29.396
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cap "wl" "a_36_40#" 108.364
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cap "bl" "vdd" 239.22
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cap "bl" "gnd" 712.11
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cap "wl" "vdd" 108.364
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cap "wl" "gnd" 1198.41
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cap "bl" "br" 27.492
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cap "a_36_40#" "vdd" 981.901
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cap "wl" "br" 189.768
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cap "a_36_40#" "gnd" 401.284
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cap "vdd" "gnd" 1390.52
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cap "a_36_40#" "br" 17.59
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fet nfet 96 12 97 13 128 48 "gnd" "wl" 16 0 "br" 16 0 "vdd" 16 0
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fet nfet 40 12 41 13 128 48 "gnd" "wl" 16 0 "bl" 16 0 "a_36_40#" 16 0
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fet nfet 116 40 117 41 256 80 "gnd" "a_36_40#" 16 0 "vdd" 32 0 "gnd" 32 0
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fet nfet 28 40 29 41 256 80 "gnd" "vdd" 16 0 "gnd" 32 0 "a_36_40#" 32 0
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fet pfet 108 148 109 149 192 56 "vdd" "a_36_40#" 32 0 "vdd" 24 0
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fet pfet 28 148 29 149 192 56 "vdd" "vdd" 32 0 "vdd" 12 0 "a_36_40#" 12 0
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@ -0,0 +1,16 @@
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* SPICE3 file created from replica_cell_6t.ext - technology: scmos
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M1000 a_36_40# vdd vdd vdd pfet w=0.6u l=0.8u
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+ ad=0.76p pd=3.6u as=2.76p ps=12.4u
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** SOURCE/DRAIN TIED
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M1001 vdd a_36_40# vdd vdd pfet w=0.8u l=0.6u
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+ ad=0p pd=0u as=0p ps=0u
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M1002 a_36_40# vdd gnd gnd nfet w=1.6u l=0.4u
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+ ad=2.4p pd=7.2u as=4.48p ps=12u
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M1003 gnd a_36_40# vdd gnd nfet w=1.6u l=0.4u
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+ ad=0p pd=0u as=3.04p ps=10.4u
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M1004 a_36_40# wl bl gnd nfet w=0.8u l=0.4u
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+ ad=0p pd=0u as=0.8p ps=3.6u
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M1005 vdd wl br gnd nfet w=0.8u l=0.4u
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+ ad=0p pd=0u as=0.8p ps=3.6u
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C0 vdd 0 2.60fF
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@ -0,0 +1,14 @@
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.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
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MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
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MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
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MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u
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MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
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MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
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MM4 Q_bar wl0 br0 gnd n w=0.8u l=0.4u
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MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u
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MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u
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MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u
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MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u
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.ENDS
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@ -0,0 +1,38 @@
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****** HSPICE -- M-2017.03 linux64 (Feb 20 2017) ******
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Input File: cell_6t.sp
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lic:
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lic: FLEXlm: SDK_11.6.4
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||||
lic: USER: mrg HOSTNAME: 72fb17cef281
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lic: HOSTID: 0242ac110002 PID: 69
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lic: Using FLEXlm license file:
|
||||
lic: 27000@license.soe.ucsc.edu
|
||||
lic: Checkout 1 hspice
|
||||
lic: License/Maintenance for hspice will expire on 18-dec-2020/2018.09
|
||||
lic: 1(in_use)/50(total) FLOATING license(s) on SERVER 27000@license.soe.ucsc.edu
|
||||
lic:
|
||||
init: begin read circuit files, cpu clock= 9.60E-01
|
||||
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/a
|
||||
d
|
||||
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/b
|
||||
ehave
|
||||
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/c
|
||||
omlinear
|
||||
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/d
|
||||
io
|
||||
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/f
|
||||
et
|
||||
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/l
|
||||
in_tech
|
||||
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/p
|
||||
ci
|
||||
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/s
|
||||
ignet
|
||||
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/t
|
||||
i
|
||||
option search = /bsoe/software/synopsys/M-2017.03/hspice/parts/x
|
||||
ilinx
|
||||
option runlvl
|
||||
init: end read circuit files, cpu clock= 9.60E-01 peak memory= 290 mb
|
||||
init: begin check errors, cpu clock= 9.60E-01
|
||||
>error ***** hspice job aborted
|
||||
lic: Release hspice token(s)
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
|
||||
.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
|
||||
MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
|
||||
MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
|
||||
MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u
|
||||
MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
|
||||
MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
|
||||
MM4 vdd wl0 br0 gnd n w=0.8u l=0.4u
|
||||
MM1 Q vdd gnd gnd n w=1.6u l=0.4u
|
||||
MM0 vdd Q gnd gnd n w=1.6u l=0.4u
|
||||
MM3 Q vdd vdd vdd p w=0.6u l=0.4u
|
||||
MM2 vdd Q vdd vdd p w=0.6u l=0.4u
|
||||
.ENDS
|
||||
|
||||
Loading…
Reference in New Issue