mirror of https://github.com/VLSIDA/OpenRAM.git
Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.
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@ -28,6 +28,8 @@ class verilog:
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self.vf.write("// Word size: {0}\n".format(self.word_size))
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if self.wmask_enabled:
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self.vf.write("// Write size: {0}\n\n".format(self.write_size))
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else:
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self.vf.write("\n")
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self.vf.write("module {0}(\n".format(self.name))
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for port in self.all_ports:
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@ -34,19 +34,19 @@ class control_logic_test(openram_test):
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OPTS.num_r_ports = 1
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debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
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a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
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a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, write_size=8, port_type="rw")
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self.local_check(a)
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# OPTS.num_rw_ports = 0
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# OPTS.num_w_ports = 1
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debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
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a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w")
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a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, write_size=8, port_type="w")
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self.local_check(a)
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# OPTS.num_w_ports = 0
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# OPTS.num_r_ports = 1
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debug.info(1, "Testing sample for control_logic for multiport, only read control logic")
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a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="r")
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a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, write_size=8, port_type="r")
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self.local_check(a)
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globals.end_openram()
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@ -24,7 +24,7 @@ class control_logic_test(openram_test):
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# check control logic for single port
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debug.info(1, "Testing sample for control_logic")
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a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
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a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, write_size=32)
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self.local_check(a)
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# run the test from the command line
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