Create port address module

compiler/base/hierarchy_layout.py

@@ -227,6 +227,9 @@ class layout():
         You can optionally rename the pin to a new name. 
         """
         pins=instance.get_pins(pin_name)
+        
+        debug.check(len(pins)>0,"Could not find pin {}".format(pin_name))
+        
         for pin in pins:
             if new_name=="":
                 new_name = pin.name
@@ -238,9 +241,7 @@ class layout():
         You can optionally rename the pin to a new name. 
         """
         for pin_name in self.pin_map.keys():
-            pins=instance.get_pins(pin_name)
-            for pin in pins:
-                self.add_layout_pin(prefix+pin_name, pin.layer, pin.ll(), pin.width(), pin.height())
+            self.copy_layout_pin(instance, pin_name, prefix+pin_name)
             
     def add_layout_pin_segment_center(self, text, layer, start, end):
         """ 

compiler/modules/bank.py

@@ -358,9 +358,6 @@ class bank(design.design):
                                               cols=self.num_cols)
         self.add_mod(self.wordline_driver)
 
-        self.inv = factory.create(module_type="pinv")
-        self.add_mod(self.inv)
-
         if(self.num_banks > 1):
             self.bank_select = factory.create(module_type="bank_select")
             self.add_mod(self.bank_select)

compiler/modules/port_data.py

@@ -1,8 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
+# Copyright (c) 2016-2019 Regents of the University of California 
 # All rights reserved.
 #
 import sys
@@ -72,7 +70,7 @@ class port_data(design.design):
         self.DRC_LVS()
 
     def add_pins(self):
-        """ Adding pins for Bank module"""
+        """ Adding pins for port address module"""
         for bit in range(self.num_cols):
             self.add_pin(self.bl_names[self.port]+"_{0}".format(bit),"INOUT")
             self.add_pin(self.br_names[self.port]+"_{0}".format(bit),"INOUT")

compiler/tests/18_port_address_test.py

@@ -0,0 +1,32 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys,os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+class port_address_test(openram_test):
+
+    def runTest(self):
+        globals.init_openram("config_{0}".format(OPTS.tech_name))
+
+        debug.info(1, "Port address 16 rows")
+        a = factory.create("port_address", cols=16, rows=16)
+        self.local_check(a)
+        
+        globals.end_openram()
+        
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/18_port_data_test.py

@@ -1,9 +1,7 @@
 #!/usr/bin/env python3
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
+# Copyright (c) 2016-2019 Regents of the University of California
 # All rights reserved.
 #
 import unittest