mirror of https://github.com/VLSIDA/OpenRAM.git
Added incorrect read checking in characterizer.
This commit is contained in:
Hunter Nichols
parent
d54074d68e
commit
b4cce65889
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@ -1,4 +1,4 @@
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import sys,re,shutil
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import sys,re,shutil,copy
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import debug
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import tech
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import math
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@ -48,32 +48,33 @@ class delay(simulation):
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def create_measurement_objects(self):
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"""Create the measurements used for read and write ports"""
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self.create_read_port_measurement_objects()
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self.create_write_port_measurement_objects()
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self.read_meas_lists = self.create_read_port_measurement_objects()
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self.write_meas_lists = self.create_write_port_measurement_objects()
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def create_read_port_measurement_objects(self):
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"""Create the measurements used for read ports: delays, slews, powers"""
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self.read_meas_objs = []
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self.read_lib_meas = []
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trig_delay_name = "clk{0}"
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targ_name = "{0}{1}_{2}".format(self.dout_name,"{}",self.probe_data) #Empty values are the port and probe data bit
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self.read_meas_objs.append(delay_measure("delay_lh", trig_delay_name, targ_name, "RISE", "RISE", measure_scale=1e9))
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self.read_meas_objs[-1].meta_str = "read1" #Used to index time delay values when measurements written to spice file.
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self.read_meas_objs.append(delay_measure("delay_hl", trig_delay_name, targ_name, "FALL", "FALL", measure_scale=1e9))
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self.read_meas_objs[-1].meta_str = "read0"
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self.read_lib_meas.append(delay_measure("delay_lh", trig_delay_name, targ_name, "RISE", "RISE", measure_scale=1e9))
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self.read_lib_meas[-1].meta_str = "read1" #Used to index time delay values when measurements written to spice file.
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self.read_lib_meas.append(delay_measure("delay_hl", trig_delay_name, targ_name, "FALL", "FALL", measure_scale=1e9))
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self.read_lib_meas[-1].meta_str = "read0"
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self.delay_meas = self.read_lib_meas[:] #For debugging, kept separated
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self.read_meas_objs.append(slew_measure("slew_lh", targ_name, "RISE", measure_scale=1e9))
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self.read_meas_objs[-1].meta_str = "read1"
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self.read_meas_objs.append(slew_measure("slew_hl", targ_name, "FALL", measure_scale=1e9))
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self.read_meas_objs[-1].meta_str = "read0"
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self.read_lib_meas.append(slew_measure("slew_lh", targ_name, "RISE", measure_scale=1e9))
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self.read_lib_meas[-1].meta_str = "read1"
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self.read_lib_meas.append(slew_measure("slew_hl", targ_name, "FALL", measure_scale=1e9))
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self.read_lib_meas[-1].meta_str = "read0"
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self.read_meas_objs.append(power_measure("read1_power", "RISE", measure_scale=1e3))
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self.read_meas_objs[-1].meta_str = "read1"
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self.read_meas_objs.append(power_measure("read0_power", "FALL", measure_scale=1e3))
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self.read_meas_objs[-1].meta_str = "read0"
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self.read_lib_meas.append(power_measure("read1_power", "RISE", measure_scale=1e3))
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self.read_lib_meas[-1].meta_str = "read1"
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self.read_lib_meas.append(power_measure("read0_power", "FALL", measure_scale=1e3))
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self.read_lib_meas[-1].meta_str = "read0"
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#This will later add a half-period to the spice time delay. Only for reading 0.
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for obj in self.read_meas_objs:
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for obj in self.read_lib_meas:
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if obj.meta_str is "read0":
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obj.meta_add_delay = True
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@ -85,17 +86,22 @@ class delay(simulation):
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bl_name = "Xsram.Xbank0.bl{}_{}".format(port_format, self.bitline_column)
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br_name = "Xsram.Xbank0.br{}_{}".format(port_format, self.bitline_column)
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# self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[0], trig_name, bl_name, "RISE", .5))
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# self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[1], trig_name, br_name, "RISE", .5))
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# self.read_lib_meas.append(voltage_when_measure(self.voltage_when_names[0], trig_name, bl_name, "RISE", .5))
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# self.read_lib_meas.append(voltage_when_measure(self.voltage_when_names[1], trig_name, br_name, "RISE", .5))
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#These are read values but need to be separated for unique error checking.
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self.create_bitline_delay_measurement_objects()
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read_measures = []
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read_measures.append(self.read_lib_meas)
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#Other measurements associated with the read port not included in the liberty file
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read_measures.append(self.create_bitline_delay_measurement_objects())
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read_measures.append(self.create_debug_measurement_objects())
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return read_measures
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def create_bitline_delay_measurement_objects(self):
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"""Create the measurements used for bitline delay values. Due to unique error checking, these are separated from other measurements.
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These measurements are only associated with read values
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"""
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self.bitline_delay_objs = []
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self.bitline_delay_meas = []
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trig_name = "clk{0}"
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if len(self.all_ports) == 1: #special naming case for single port sram bitlines which does not include the port in name
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port_format = ""
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@ -106,23 +112,51 @@ class delay(simulation):
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targ_val = (self.vdd_voltage - tech.spice["v_threshold_typical"])/self.vdd_voltage #Calculate as a percentage of vdd
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targ_name = "{0}{1}_{2}".format(self.dout_name,"{}",self.probe_data) #Empty values are the port and probe data bit
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# self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[0], trig_name, bl_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9))
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# self.bitline_delay_objs[-1].meta_str = "read0"
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# self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[1], trig_name, br_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9))
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# self.bitline_delay_objs[-1].meta_str = "read1"
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# self.bitline_delay_meas.append(delay_measure(self.bitline_delay_names[0], trig_name, bl_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9))
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# self.bitline_delay_meas[-1].meta_str = "read0"
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# self.bitline_delay_meas.append(delay_measure(self.bitline_delay_names[1], trig_name, br_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9))
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# self.bitline_delay_meas[-1].meta_str = "read1"
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#Enforces the time delay on the bitline measurements for read0 or read1
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for obj in self.bitline_delay_objs:
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for obj in self.bitline_delay_meas:
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obj.meta_add_delay = True
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return self.bitline_delay_meas
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def create_write_port_measurement_objects(self):
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"""Create the measurements used for read ports: delays, slews, powers"""
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self.write_meas_objs = []
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self.write_lib_meas = []
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self.write_meas_objs.append(power_measure("write1_power", "RISE", measure_scale=1e3))
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self.write_meas_objs[-1].meta_str = "write1"
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self.write_meas_objs.append(power_measure("write0_power", "FALL", measure_scale=1e3))
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self.write_meas_objs[-1].meta_str = "write0"
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self.write_lib_meas.append(power_measure("write1_power", "RISE", measure_scale=1e3))
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self.write_lib_meas[-1].meta_str = "write1"
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self.write_lib_meas.append(power_measure("write0_power", "FALL", measure_scale=1e3))
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self.write_lib_meas[-1].meta_str = "write0"
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write_measures = []
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write_measures.append(self.write_lib_meas)
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return write_measures
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def create_debug_measurement_objects(self):
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"""Create debug measurement to help identify failures."""
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self.debug_delay_meas = []
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self.debug_volt_meas = []
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for meas in self.delay_meas:
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debug_meas = copy.deepcopy(meas)
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debug_meas.name = debug_meas.name+'_debug'
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#This particular debugs check if output value is flipped, so TARG_DIR is flipped
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if meas.targ_dir_str == 'FALL':
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debug_meas.targ_dir_str = 'RISE'
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else:
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debug_meas.targ_dir_str = 'FALL'
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#inserting debug member variable
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debug_meas.parent = meas.name
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self.debug_delay_meas.append(debug_meas)
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self.debug_volt_meas.append(voltage_at_measure("v_{}".format(debug_meas.meta_str),
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debug_meas.targ_name_no_port))
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self.debug_volt_meas[-1].meta_str = debug_meas.meta_str
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return self.debug_delay_meas+self.debug_volt_meas
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def create_signal_names(self):
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self.addr_name = "A"
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self.din_name = "DIN"
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@ -284,6 +318,8 @@ class delay(simulation):
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return self.get_power_measure_variants(port, measure_obj, "read")
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elif meas_type is voltage_when_measure:
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return self.get_volt_when_measure_variants(port, measure_obj)
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elif meas_type is voltage_at_measure:
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return self.get_volt_at_measure_variants(port, measure_obj)
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else:
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debug.error("Input function not defined for measurement type={}".format(meas_type))
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@ -299,6 +335,7 @@ class delay(simulation):
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else:
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debug.error("Unrecognised delay Index={}".format(delay_obj.meta_str),1)
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#These measurements have there time further delayed to the neg. edge of the clock.
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if delay_obj.meta_add_delay:
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meas_cycle_delay += self.period/2
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@ -312,7 +349,21 @@ class delay(simulation):
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return (t_initial, t_final, port)
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def get_volt_when_measure_variants(self, port, power_obj):
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def get_volt_at_measure_variants(self, port, volt_meas):
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"""Get the measurement values that can either vary port to port (time delays)"""
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#Only checking 0 value reads for now.
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if volt_meas.meta_str == "read0":
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#Falling delay are measured starting from neg. clk edge. Delay adjusted to that.
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meas_cycle = self.cycle_times[self.measure_cycles[port][volt_meas.meta_str]]
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elif volt_meas.meta_str == "read1":
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meas_cycle = self.cycle_times[self.measure_cycles[port][volt_meas.meta_str]]
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else:
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debug.error("Unrecognised delay Index={}".format(volt_meas.meta_str),1)
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#Measurement occurs at the end of the period -> current period start + period
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at_time = meas_cycle+self.period
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return (at_time, port)
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def get_volt_when_measure_variants(self, port, volt_meas):
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"""Get the measurement values that can either vary port to port (time delays)"""
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#Only checking 0 value reads for now.
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t_trig = meas_cycle_delay = self.cycle_times[self.measure_cycles[port]["read0"]]
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@ -324,9 +375,10 @@ class delay(simulation):
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Write the measure statements to quantify the delay and power results for a read port.
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"""
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# add measure statements for delays/slews
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for measure in self.read_meas_objs+self.bitline_delay_objs:
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measure_variant_inp_tuple = self.get_read_measure_variants(port, measure)
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measure.write_measure(self.stim, measure_variant_inp_tuple)
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for meas_list in self.read_meas_lists:
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for measure in meas_list:
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measure_variant_inp_tuple = self.get_read_measure_variants(port, measure)
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measure.write_measure(self.stim, measure_variant_inp_tuple)
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def get_write_measure_variants(self, port, measure_obj):
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"""Checks the measurement object and calls respective function for related measurement inputs."""
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@ -341,9 +393,10 @@ class delay(simulation):
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Write the measure statements to quantify the power results for a write port.
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"""
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# add measure statements for power
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for measure in self.write_meas_objs:
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measure_variant_inp_tuple = self.get_write_measure_variants(port, measure)
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measure.write_measure(self.stim, measure_variant_inp_tuple)
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for meas_list in self.write_meas_lists:
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for measure in meas_list:
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measure_variant_inp_tuple = self.get_write_measure_variants(port, measure)
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measure.write_measure(self.stim, measure_variant_inp_tuple)
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def write_delay_measures(self):
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"""
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@ -462,6 +515,7 @@ class delay(simulation):
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#Sanity Check
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debug.check(self.period > 0, "Target simulation period non-positive")
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sim_passed = True
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result = [{} for i in self.all_ports]
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# Checking from not data_value to data_value
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self.write_delay_stimulus()
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@ -471,17 +525,18 @@ class delay(simulation):
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#Loop through all targeted ports and collect delays and powers.
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#Too much duplicate code here. Try reducing
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for port in self.targ_read_ports:
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debug.info(2, "Check delay values for port {}".format(port))
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debug.info(2, "Checking delay values for port {}".format(port))
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read_port_dict = {}
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#Get measurements from output file
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for measure in self.read_meas_objs:
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for measure in self.read_lib_meas:
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read_port_dict[measure.name] = measure.retrieve_measure(port=port)
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debug_passed = self.check_debug_measures(port, read_port_dict)
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#Check timing for read ports. Power is only checked if it was read correctly
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if not self.check_valid_delays(read_port_dict):
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if not self.check_valid_delays(read_port_dict) or not debug_passed:
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return (False,{})
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if not check_dict_values_is_float(read_port_dict):
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debug.error("Failed to Measure Read Port Values:\n\t\t{0}".format(read_port_dict),1) #Printing the entire dict looks bad.
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debug.error("Failed to Measure Read Port Values:\n\t\t{0}".format(read_port_dict),1) #Printing the entire dict looks bad.
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result[port].update(read_port_dict)
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@ -490,7 +545,7 @@ class delay(simulation):
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for port in self.targ_write_ports:
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write_port_dict = {}
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for measure in self.write_meas_objs:
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for measure in self.write_lib_meas:
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write_port_dict[measure.name] = measure.retrieve_measure(port=port)
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if not check_dict_values_is_float(write_port_dict):
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@ -498,13 +553,54 @@ class delay(simulation):
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result[port].update(write_port_dict)
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# The delay is from the negative edge for our SRAM
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return (True,result)
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return (sim_passed,result)
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def check_debug_measures(self, port, read_measures):
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"""Debug measures that indicate special conditions."""
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#Currently, only check if the opposite than intended value was read during
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# the read cycles i.e. neither of these measurements should pass.
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success = True
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for meas in self.debug_delay_meas:
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val = meas.retrieve_measure(port=port)
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debug.info(2,"{}={}".format(meas.name, val))
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if type(val) != float:
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continue
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if meas.meta_add_delay:
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max_delay = self.period/2
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else:
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max_delay = self.period
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#If the debug measurement occurs after the original (and passes other conditions)
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#then it fails i.e. the debug value represents the final (but failing) state of the output
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parent_compare = type(read_measures[meas.parent]) != float or val > read_measures[meas.parent]
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if 0 < val < max_delay and parent_compare:
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success = False
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debug.info(1, "Debug measurement failed. Incorrect Value found on output.")
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break
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for meas in self.debug_volt_meas:
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val = meas.retrieve_measure(port=port)
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debug.info(2,"{}={}".format(meas.name, val))
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if type(val) != float:
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continue
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if meas.meta_str == 'read1' and val < tech.spice["v_threshold_typical"]:
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success = False
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debug.info(1, "Debug measurement failed. Value {}v was read on read 1 cycle.".format(val))
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break
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elif meas.meta_str == 'read0' and val > self.vdd_voltage-tech.spice["v_threshold_typical"]:
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success = False
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debug.info(1, "Debug measurement failed. Value {}v was read on read 0 cycle.".format(val))
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break
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return success
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def evaluate_bitline_delay(self, port):
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"""Parse and check the bitline delay. One of the measurements is expected to fail which warrants its own function."""
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bl_delay_meas_dict = {}
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values_added = 0 #For error checking
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for measure in self.bitline_delay_objs:
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for measure in self.bitline_delay_meas:
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bl_delay_val = measure.retrieve_measure(port=port)
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if type(bl_delay_val) != float or 0 > bl_delay_val or bl_delay_val > self.period/2: #Only add if value is valid, do not error.
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debug.error("Bitline delay measurement failed: half-period={}, {}={}".format(self.period/2, measure.name, bl_delay_val),1)
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@ -556,7 +652,8 @@ class delay(simulation):
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delays_str = "delay_hl={0} delay_lh={1}".format(delay_hl, delay_lh)
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slews_str = "slew_hl={0} slew_lh={1}".format(slew_hl,slew_lh)
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half_period = self.period/2 #high-to-low delays start at neg. clk edge, so they need to be less than half_period
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if abs(delay_hl)>half_period or abs(delay_lh)>self.period or abs(slew_hl)>half_period or abs(slew_lh)>self.period:
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if abs(delay_hl)>half_period or abs(delay_lh)>self.period or abs(slew_hl)>half_period or abs(slew_lh)>self.period \
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or delay_hl<0 or delay_lh<0 or slew_hl<0 or slew_lh<0:
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debug.info(2,"UNsuccessful simulation (in ns):\n\t\t{0}\n\t\t{1}\n\t\t{2}".format(period_load_slew_str,
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delays_str,
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slews_str))
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@ -156,4 +156,32 @@ class voltage_when_measure(spice_measurement):
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trig_voltage = self.trig_val_of_vdd*vdd_voltage
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return (meas_name,trig_name,targ_name,trig_voltage,self.trig_dir_str,trig_td)
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return (meas_name,trig_name,targ_name,trig_voltage,self.trig_dir_str,trig_td)
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class voltage_at_measure(spice_measurement):
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"""Generates a spice measurement to measure the voltage at a specific time.
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The time is considered variant with different periods."""
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def __init__(self, measure_name, targ_name, measure_scale=None):
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spice_measurement.__init__(self, measure_name, measure_scale)
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self.set_meas_constants(targ_name)
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def get_measure_function(self):
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return stimuli.gen_meas_find_voltage_at_time
|
||||
|
||||
def set_meas_constants(self, targ_name):
|
||||
"""Sets values useful for power simulations. This value is only meta related to the lib file (rise/fall)"""
|
||||
self.targ_name_no_port = targ_name
|
||||
|
||||
def get_measure_values(self, time_at, port=None):
|
||||
"""Constructs inputs to stimulus measurement function. Variant values are inputs here."""
|
||||
if port != None:
|
||||
#For dictionary indexing reasons, the name is formatted differently than the signals
|
||||
meas_name = "{}{}".format(self.name, port)
|
||||
targ_name = self.targ_name_no_port.format(port)
|
||||
else:
|
||||
meas_name = self.name
|
||||
targ_name = self.targ_name_no_port
|
||||
|
||||
return (meas_name,targ_name,time_at)
|
||||
|
||||
|
|
@ -226,6 +226,13 @@ class stimuli():
|
|||
trig_dir,
|
||||
trig_td))
|
||||
|
||||
def gen_meas_find_voltage_at_time(self, meas_name, targ_name, time_at):
|
||||
""" Creates the .meas statement for voltage at time"""
|
||||
measure_string=".meas tran {0} FIND v({1}) AT={2}n \n\n"
|
||||
self.sf.write(measure_string.format(meas_name,
|
||||
targ_name,
|
||||
time_at))
|
||||
|
||||
def gen_meas_power(self, meas_name, t_initial, t_final):
|
||||
""" Creates the .meas statement for the measurement of avg power """
|
||||
# power mea cmd is different in different spice:
|
||||
|
|
|
|||
|
|
@ -26,10 +26,15 @@ class timing_sram_test(openram_test):
|
|||
reload(characterizer)
|
||||
from characterizer import delay
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=1,
|
||||
num_words=16,
|
||||
# c = sram_config(word_size=1,
|
||||
# num_words=16,
|
||||
# num_banks=1)
|
||||
# c.words_per_row=1
|
||||
c = sram_config(word_size=32,
|
||||
num_words=256,
|
||||
num_banks=1)
|
||||
c.words_per_row=1
|
||||
c.words_per_row=2
|
||||
OPTS.use_tech_delay_chain_size = True
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
|
||||
s = factory.create(module_type="sram", sram_config=c)
|
||||
|
|
@ -42,13 +47,13 @@ class timing_sram_test(openram_test):
|
|||
s.s.graph_exclude_data_dff()
|
||||
s.s.graph_exclude_ctrl_dffs()
|
||||
|
||||
debug.info(1,'pins={}'.format(s.s.pins))
|
||||
import graph_util
|
||||
graph = graph_util.timing_graph()
|
||||
pins=['DIN0[0]', 'ADDR0[0]', 'ADDR0[1]', 'ADDR0[2]', 'ADDR0[3]', 'csb0', 'web0', 'clk0', 'DOUT0[0]', 'vdd', 'gnd']
|
||||
s.s.build_graph(graph,"Xsram",pins)
|
||||
#debug.info(1,"{}".format(graph))
|
||||
graph.print_all_paths('clk0', 'DOUT0[0]')
|
||||
# debug.info(1,'pins={}'.format(s.s.pins))
|
||||
# import graph_util
|
||||
# graph = graph_util.timing_graph()
|
||||
# pins=['DIN0[0]', 'ADDR0[0]', 'ADDR0[1]', 'ADDR0[2]', 'ADDR0[3]', 'csb0', 'web0', 'clk0', 'DOUT0[0]', 'vdd', 'gnd']
|
||||
# s.s.build_graph(graph,"Xsram",pins)
|
||||
# #debug.info(1,"{}".format(graph))
|
||||
# graph.print_all_paths('clk0', 'DOUT0[0]')
|
||||
# import sys
|
||||
# sys.exit(1)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue