mirror of https://github.com/VLSIDA/OpenRAM.git
Merge remote-tracking branch 'origin' into tech_reorg
This commit is contained in:
Matt Guthaus
commit
7129f79dc4
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@ -42,8 +42,8 @@ class delay(simulation):
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#Altering the names will crash the characterizer. TODO: object orientated approach to the measurements.
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self.delay_meas_names = ["delay_lh", "delay_hl", "slew_lh", "slew_hl"]
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self.power_meas_names = ["read0_power", "read1_power", "write0_power", "write1_power"]
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self.voltage_when_names = ["volt_bl", "volt_br"]
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self.bitline_delay_names = ["delay_bl", "delay_br"]
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#self.voltage_when_names = ["volt_bl", "volt_br"]
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#self.bitline_delay_names = ["delay_bl", "delay_br"]
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def create_measurement_objects(self):
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"""Create the measurements used for read and write ports"""
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@ -84,8 +84,8 @@ class delay(simulation):
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bl_name = "Xsram.Xbank0.bl{}_{}".format(port_format, self.bitline_column)
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br_name = "Xsram.Xbank0.br{}_{}".format(port_format, self.bitline_column)
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self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[0], trig_name, bl_name, "RISE", .5))
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self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[1], trig_name, br_name, "RISE", .5))
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# self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[0], trig_name, bl_name, "RISE", .5))
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# self.read_meas_objs.append(voltage_when_measure(self.voltage_when_names[1], trig_name, br_name, "RISE", .5))
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#These are read values but need to be separated for unique error checking.
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self.create_bitline_delay_measurement_objects()
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@ -105,10 +105,10 @@ class delay(simulation):
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targ_val = (self.vdd_voltage - tech.spice["v_threshold_typical"])/self.vdd_voltage #Calculate as a percentage of vdd
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targ_name = "{0}{1}_{2}".format(self.dout_name,"{}",self.probe_data) #Empty values are the port and probe data bit
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self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[0], trig_name, bl_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9))
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self.bitline_delay_objs[-1].meta_str = "read0"
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self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[1], trig_name, br_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9))
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self.bitline_delay_objs[-1].meta_str = "read1"
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# self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[0], trig_name, bl_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9))
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# self.bitline_delay_objs[-1].meta_str = "read0"
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# self.bitline_delay_objs.append(delay_measure(self.bitline_delay_names[1], trig_name, br_name, "FALL", "FALL", targ_vdd=targ_val, measure_scale=1e9))
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# self.bitline_delay_objs[-1].meta_str = "read1"
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#Enforces the time delay on the bitline measurements for read0 or read1
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for obj in self.bitline_delay_objs:
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obj.meta_add_delay = True
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@ -966,7 +966,7 @@ class delay(simulation):
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def get_empty_measure_data_dict(self):
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"""Make a dict of lists for each type of delay and power measurement to append results to"""
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measure_names = self.delay_meas_names + self.power_meas_names + self.voltage_when_names + self.bitline_delay_names
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measure_names = self.delay_meas_names + self.power_meas_names
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#Create list of dicts. List lengths is # of ports. Each dict maps the measurement names to lists.
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measure_data = [{mname:[] for mname in measure_names} for i in self.all_ports]
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return measure_data
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@ -0,0 +1,41 @@
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from pathlib import Path
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import glob
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import os
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import sys
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# This is the path to the directory you would like to search
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# This directory is searched recursively for .html files
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path_to_files = sys.argv[1]
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def get_file_tree(path):
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return list(Path(path).rglob("*.html"))
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def parse_html(file, comment):
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start_tag = '<!--'+comment
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end_tag = comment+'-->'
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with open(file, 'r') as f:
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file_string = f.read()
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with open(file, 'w') as f:
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file_string = file_string.replace(start_tag,"")
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file_string = file_string.replace(end_tag,"")
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f.write(file_string)
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def uncomment(comments):
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comment_files = []
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for datasheet in datasheet_list:
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for comment in comments:
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if glob.glob(os.path.dirname(datasheet)+'/*' + comment):
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parse_html(datasheet, comment)
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datasheet_list = get_file_tree(path_to_files)
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comments = ['.db']
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uncomment(comments)
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@ -38,6 +38,9 @@ class datasheet():
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with open(os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/datasheet/assets/OpenRAM_logo.png', "rb") as image_file:
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openram_logo = base64.b64encode(image_file.read())
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#comment table rows which we may want to enable after compile time
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comments = ['.db']
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self.html += '<a href="https://vlsida.soe.ucsc.edu/"><img src="data:image/png;base64,{0}" alt="VLSIDA"></a><a href ="https://github.com/VLSIDA/OpenRAM"><img src ="data:image/png;base64,{1}" alt = "OpenRAM"></a>'.format(str(vlsi_logo)[2:-1], str(openram_logo)[2:-1])
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self.html += '<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">' + \
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@ -51,11 +54,11 @@ class datasheet():
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'Git commit id: ' + str(self.git_id) + '</p>'
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# print port table
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self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration</p>'
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self.html += self.io_table.to_html()
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self.html += self.io_table.to_html(comments)
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# print operating condidition information
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self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Operating Conditions</p>'
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self.html += self.operating_table.to_html()
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self.html += self.operating_table.to_html(comments)
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# check if analytical model is being used
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self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Timing Data</p>'
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@ -66,13 +69,14 @@ class datasheet():
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model = "spice characterizer"
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# display timing data
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self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Using '+model+'</p>'
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self.html += self.timing_table.to_html()
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self.html += self.timing_table.to_html(comments)
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# display power data
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self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Power Data</p>'
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self.html += self.power_table.to_html()
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self.html += self.power_table.to_html(comments)
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# display corner information
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self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Characterization Corners</p>'
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self.html += self.corners_table.to_html()
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self.html += self.corners_table.to_html(comments)
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# display deliverables table
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self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Deliverables</p>'
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self.html += self.dlv_table.to_html()
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self.dlv_table.sort()
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self.html += self.dlv_table.to_html(comments)
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@ -386,6 +386,9 @@ def parse_characterizer_csv(f, pages):
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[PROC, VOLT, TEMP, LIB_NAME.replace(OUT_DIR, '').replace(NAME, '')])
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new_sheet.dlv_table.add_row(
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['.lib', 'Synthesis models', '<a href="file://{0}">{1}</a>'.format(LIB_NAME, LIB_NAME.replace(OUT_DIR, ''))])
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new_sheet.dlv_table.add_row(
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['.db', 'Compiled .lib', '<a href="{1}">{1}</a>'.format(LIB_NAME[:-3] + 'db', LIB_NAME.replace(OUT_DIR, '')[:-3] + 'db')])
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if found == 0:
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@ -603,6 +606,8 @@ def parse_characterizer_csv(f, pages):
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['.html', 'This datasheet', '<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name, 'html')])
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new_sheet.dlv_table.add_row(
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['.lib', 'Synthesis models', '<a href="{1}">{1}</a>'.format(LIB_NAME, LIB_NAME.replace(OUT_DIR, ''))])
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new_sheet.dlv_table.add_row(
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['.db', 'Compiled .lib', '<a href="{1}">{1}</a>'.format(LIB_NAME[:-3] + 'db', LIB_NAME.replace(OUT_DIR, '')[:-3] + 'db')])
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new_sheet.dlv_table.add_row(
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['.py', 'OpenRAM configuration file', '<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name, 'py')])
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new_sheet.dlv_table.add_row(
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@ -22,27 +22,38 @@ class table_gen:
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html += '</thead>'
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return html
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def gen_table_body(self):
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def gen_table_body(self,comments):
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"""generate html body (used after gen_table_head)"""
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html = ''
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html += '<tbody>'
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html += '<tr>'
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for row in self.rows[1:]:
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html += '<tr>'
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for col in row:
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html += '<td>' + str(col) + '</td>'
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html += '</tr>'
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if row[0] not in comments:
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html += '<tr>'
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for col in row:
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html += '<td>' + str(col) + '</td>'
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html += '</tr>'
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else:
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html += '<!--'+row[0]+'<tr>'
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for col in row:
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html += '<td>' + str(col) + '</td>'
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html += '</tr>'+row[0]+'-->'
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html += '</tr>'
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html += '</tbody>'
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return html
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def sort(self):
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self.rows[1:] = sorted(self.rows[1:], key=lambda x : x[0])
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def to_html(self):
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def to_html(self,comments):
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"""writes table_gen object to inline html"""
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html = ''
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html += '<table id= \"'+self.table_id+'\">'
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html += self.gen_table_head()
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html += self.gen_table_body()
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html += '</table>'
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html += self.gen_table_body(comments)
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html += '</table>\n'
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return html
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@ -51,9 +51,7 @@ class timing_sram_test(openram_test):
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_bl': [0.1980959],
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'delay_br': [0.1946091],
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'delay_hl': [0.2121267],
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golden_data = {'delay_hl': [0.2121267],
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'delay_lh': [0.2121267],
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'leakage_power': 0.0023761999999999998,
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'min_period': 0.43,
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@ -61,14 +59,10 @@ class timing_sram_test(openram_test):
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'read1_power': [0.48940979999999995],
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'slew_hl': [0.0516745],
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'slew_lh': [0.0516745],
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'volt_bl': [0.5374525],
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'volt_br': [1.1058],
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'write0_power': [0.46267169999999996],
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'write1_power': [0.4670826]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_bl': [1.1029],
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'delay_br': [0.9656455999999999],
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'delay_hl': [1.288],
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golden_data = {'delay_hl': [1.288],
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'delay_lh': [1.288],
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'leakage_power': 0.0273896,
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'min_period': 2.578,
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@ -76,8 +70,6 @@ class timing_sram_test(openram_test):
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'read1_power': [16.2616],
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'slew_hl': [0.47891700000000004],
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'slew_lh': [0.47891700000000004],
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'volt_bl': [4.2155],
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'volt_br': [5.8142],
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'write0_power': [16.0656],
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'write1_power': [16.2616]}
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@ -51,9 +51,7 @@ class timing_sram_test(openram_test):
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_bl': [0.2003652],
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'delay_br': [0.198698],
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'delay_hl': [0.2108836],
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golden_data = {'delay_hl': [0.2108836],
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'delay_lh': [0.2108836],
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'leakage_power': 0.001564799,
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'min_period': 0.508,
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@ -61,14 +59,10 @@ class timing_sram_test(openram_test):
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'read1_power': [0.4198608],
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'slew_hl': [0.0455126],
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'slew_lh': [0.0455126],
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'volt_bl': [0.6472883],
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'volt_br': [1.114024],
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'write0_power': [0.40681890000000004],
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'write1_power': [0.4198608]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_bl': [1.3937359999999999],
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'delay_br': [1.2596429999999998],
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'delay_hl': [1.5747600000000002],
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golden_data = {'delay_hl': [1.5747600000000002],
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'delay_lh': [1.5747600000000002],
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'leakage_power': 0.00195795,
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'min_period': 3.281,
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@ -76,8 +70,6 @@ class timing_sram_test(openram_test):
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'read1_power': [14.369810000000001],
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'slew_hl': [0.49631959999999997],
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'slew_lh': [0.49631959999999997],
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'volt_bl': [4.132618],
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'volt_br': [5.573099],
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'write0_power': [13.79953],
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'write1_power': [14.369810000000001]}
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