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OpenRAM
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Merged with dev and fixed conflicts.

This commit is contained in:
Hunter Nichols 2019-04-03 16:45:01 -07:00
parent cc5b347f42 df4e2fead8
commit edac60d2a8
165 changed files with 820 additions and 12572 deletions
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2
LICENSE
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@ -1,6 +1,6 @@
BSD 3-Clause License
Copyright (c) 2019 Regents of the University of California and The Board
Copyright (c) 2018-2019 Regents of the University of California and The Board
of Regents for the Oklahoma Agricultural and Mechanical College
(acting for and on behalf of Oklahoma State University)
All rights reserved.

BIN
OpenRAM_ICCAD_2016_presentation.pdf
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12
README.md
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@ -25,6 +25,13 @@ other views necessary to use SRAMs in ASIC design. OpenRAM supports
integration in both commercial and open-source flows with both
predictive and fabricable technologies.
# Documentation
Please take a look at our presentation We have created a detailed
presentation that serves as our [documentation][documentation].
This is the most up-to-date information, so please let us know if you see
things that need to be fixed.
# Basic Setup
## Docker Image
@ -68,7 +75,7 @@ You may also wish to add OPENRAM\_HOME to your PYTHONPATH:
export PYTHONPATH="$PYTHONPATH:$OPENRAM_HOME"
```
We include the tech files necessary for [FreePDK45] and [SCMOS]
We include the tech files necessary for [SCMOS]
SCN4M_SUBM. The [SCMOS] spice models, however, are generic and should
be replaced with foundry models. If you are using [FreePDK45], you
should also have that set up and have the environment variable point
@ -197,6 +204,7 @@ Each specific technology (e.g., [FreePDK45]) should be a subdirectory
# Further Help
+ [Additional hints](./HINTS.md)
+ [Documentation][documentation]
+ [OpenRAM Slack Workspace][Slack]
+ [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe])
+ [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe])
@ -233,7 +241,7 @@ If I forgot to add you, please let me know!
[Github pull request]: https://github.com/VLSIDA/PrivateRAM/pulls
[Github projects]: https://github.com/VLSIDA/PrivateRAM
[email me]: mailto:mrg+openram@ucsc.edu
[documentation]: https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing
[dev-group]: mailto:openram-dev-group@ucsc.edu
[user-group]: mailto:openram-user-group@ucsc.edu
[dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu

38
compiler/base/hierarchy_design.py
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@ -25,33 +25,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
hierarchy_spice.spice.__init__(self, name)
# Check if the name already exists, if so, give an error
# because each reference must be a unique name.
# These modules ensure unique names or have no changes if they
# aren't unique
ok_list = ['contact',
'ptx',
'pbitcell',
'replica_pbitcell',
'sram',
'hierarchical_predecode2x4',
'hierarchical_predecode3x8']
# Library cells don't change
if self.is_library_cell:
return
# Name is unique so far
elif name not in hierarchy_design.name_map:
hierarchy_design.name_map.append(name)
else:
# Name is in our list of exceptions (they don't change)
for ok_names in ok_list:
if ok_names == self.__class__.__name__:
break
else:
debug.error("Duplicate layout reference name {0} of class {1}. GDS2 requires names be unique.".format(name,self.__class__),-1)
def get_layout_pins(self,inst):
""" Return a map of pin locations of the instance offset """
# find the instance
@ -64,12 +37,17 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
return inst_map
def DRC_LVS(self, final_verification=False):
def DRC_LVS(self, final_verification=False, top_level=False):
"""Checks both DRC and LVS for a module"""
# Final verification option does not allow nets to be connected by label.
# Unit tests will check themselves.
if OPTS.is_unit_test:
return
if not OPTS.check_lvsdrc:
return
# Do not run if disabled in options.
if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
if (OPTS.inline_lvsdrc or top_level):
global total_drc_errors
global total_lvs_errors

17
compiler/base/hierarchy_layout.py
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@ -190,7 +190,8 @@ class layout():
debug.error("Should use a pin iterator since more than one pin {}".format(text),-1)
# If we have one pin, return it and not the list.
# Otherwise, should use get_pins()
return self.pin_map[text][0]
any_pin = next(iter(self.pin_map[text]))
return any_pin
except Exception as e:
#print e
self.gds_write("missing_pin.gds")
@ -205,7 +206,7 @@ class layout():
if text in self.pin_map.keys():
return self.pin_map[text]
else:
return []
return set()
def copy_layout_pin(self, instance, pin_name, new_name=""):
"""
@ -260,7 +261,7 @@ class layout():
"""
Delete a labeled pin (or all pins of the same name)
"""
self.pin_map[text]=[]
self.pin_map[text]=set()
def add_layout_pin(self, text, layer, offset, width=None, height=None):
"""
@ -277,13 +278,11 @@ class layout():
# Check if there's a duplicate!
# and if so, silently ignore it.
# Rounding errors may result in some duplicates.
pin_list = self.pin_map[text]
for pin in pin_list:
if pin == new_pin:
return pin
self.pin_map[text].append(new_pin)
if new_pin not in self.pin_map[text]:
self.pin_map[text].add(new_pin)
except KeyError:
self.pin_map[text] = [new_pin]
self.pin_map[text] = set()
self.pin_map[text].add(new_pin)
return new_pin

3
compiler/example_configs/example_config_1rw_1r_scn4m_subm.py
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@ -10,6 +10,9 @@ process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
route_supplies = True
check_lvsdrc = True
output_path = "temp"
output_name = "sram_1rw_1r_{0}_{1}_{2}".format(word_size,num_words,tech_name)

3
compiler/example_configs/example_config_1w_1r_scn4m_subm.py
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@ -10,6 +10,9 @@ process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
route_supplies = True
check_lvsdrc = True
output_path = "temp"
output_name = "sram_1w_1r_{0}_{1}_{2}".format(word_size,num_words,tech_name)

3
compiler/example_configs/example_config_freepdk45.py
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@ -6,6 +6,9 @@ process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]
route_supplies = True
check_lvsdrc = True
output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

3
compiler/example_configs/example_config_scn4m_subm.py
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@ -6,6 +6,9 @@ process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
route_supplies = True
check_lvsdrc = True
output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

14
compiler/example_configs/giant_config_scn4m_subm.py Normal file
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@ -0,0 +1,14 @@
word_size = 64
num_words = 1024
tech_name = "scn4m_subm"
process_corners = ["TT"]
supply_voltages = [ 5.0 ]
temperatures = [ 25 ]
output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
drc_name = "magic"
lvs_name = "netgen"
pex_name = "magic"

87
compiler/globals.py
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@ -79,10 +79,6 @@ def print_banner():
debug.print_raw("|=========" + "Computer Science and Engineering Department".center(60) + "=========|")
debug.print_raw("|=========" + "University of California Santa Cruz".center(60) + "=========|")
debug.print_raw("|=========" + " ".center(60) + "=========|")
debug.print_raw("|=========" + "VLSI Computer Architecture Research Group".center(60) + "=========|")
debug.print_raw("|=========" + "Electrical and Computer Engineering Department".center(60) + "=========|")
debug.print_raw("|=========" + "Oklahoma State University".center(60) + "=========|")
debug.print_raw("|=========" + " ".center(60) + "=========|")
user_info = "Usage help: openram-user-group@ucsc.edu"
debug.print_raw("|=========" + user_info.center(60) + "=========|")
dev_info = "Development help: openram-dev-group@ucsc.edu"
@ -128,6 +124,8 @@ def init_openram(config_file, is_unit_test=True):
import_tech()
set_default_corner()
init_paths()
from sram_factory import factory
@ -135,10 +133,6 @@ def init_openram(config_file, is_unit_test=True):
setup_bitcell()
# Reset the static duplicate name checker for unit tests.
import hierarchy_design
hierarchy_design.hierarchy_design.name_map=[]
global OPTS
global CHECKPOINT_OPTS
@ -187,11 +181,12 @@ def setup_bitcell():
# See if a custom bitcell exists
from importlib import find_loader
bitcell_loader = find_loader(OPTS.bitcell)
replica_bitcell_loader = find_loader(OPTS.replica_bitcell)
# Use the pbitcell if we couldn't find a custom bitcell
# or its custom replica bitcell
if bitcell_loader==None or replica_bitcell_loader==None:
try:
__import__(OPTS.bitcell)
__import__(OPTS.replica_bitcell)
except ImportError:
# Use the pbitcell if we couldn't find a custom bitcell
# or its custom replica bitcell
# Use the pbitcell (and give a warning if not in unit test mode)
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
@ -392,9 +387,20 @@ def init_paths():
except:
debug.error("Unable to make output directory.",-1)
def set_default_corner():
""" Set the default corner. """
# Set some default options now based on the technology...
if (OPTS.process_corners == ""):
OPTS.process_corners = tech.spice["fet_models"].keys()
if (OPTS.supply_voltages == ""):
OPTS.supply_voltages = tech.spice["supply_voltages"]
if (OPTS.temperatures == ""):
OPTS.temperatures = tech.spice["temperatures"]
# imports correct technology directories for testing
def import_tech():
""" Dynamically adds the tech directory to the path and imports it. """
global OPTS
debug.info(2,"Importing technology: " + OPTS.tech_name)
@ -403,34 +409,30 @@ def import_tech():
try:
OPENRAM_TECH = os.path.abspath(os.environ.get("OPENRAM_TECH"))
except:
debug.error("$OPENRAM_TECH is not properly defined.",1)
debug.check(os.path.isdir(OPENRAM_TECH),"$OPENRAM_TECH does not exist: {0}".format(OPENRAM_TECH))
OPTS.openram_tech = OPENRAM_TECH + "/" + OPTS.tech_name
if not OPTS.openram_tech.endswith('/'):
OPTS.openram_tech += "/"
debug.info(1, "Technology path is " + OPTS.openram_tech)
debug.error("$OPENRAM_TECH environment variable is not defined.",1)
# Add all of the paths
for tech_path in OPENRAM_TECH.split(":"):
debug.check(os.path.isdir(tech_path),"$OPENRAM_TECH does not exist: {0}".format(tech_path))
sys.path.append(tech_path)
debug.info(1, "Adding technology path: {}".format(tech_path))
# Import the tech
try:
filename = "setup_openram_{0}".format(OPTS.tech_name)
# we assume that the setup scripts (and tech dirs) are located at the
# same level as the compielr itself, probably not a good idea though.
path = "{0}/setup_scripts".format(os.environ.get("OPENRAM_TECH"))
debug.check(os.path.isdir(path),"OPENRAM_TECH does not exist: {0}".format(path))
sys.path.append(os.path.abspath(path))
__import__(filename)
tech_mod = __import__(OPTS.tech_name)
except ImportError:
debug.error("Nonexistent technology_setup_file: {0}.py".format(filename))
sys.exit(1)
debug.error("Nonexistent technology_setup_file: {0}.py".format(filename), -1)
import tech
# Set some default options now based on the technology...
if (OPTS.process_corners == ""):
OPTS.process_corners = tech.spice["fet_models"].keys()
if (OPTS.supply_voltages == ""):
OPTS.supply_voltages = tech.spice["supply_voltages"]
if (OPTS.temperatures == ""):
OPTS.temperatures = tech.spice["temperatures"]
OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/"
# Add the tech directory
tech_path = OPTS.openram_tech
sys.path.append(tech_path)
try:
import tech
except ImportError:
debug.error("Could not load tech module.", -1)
def print_time(name, now_time, last_time=None, indentation=2):
@ -472,11 +474,14 @@ def report_status():
OPTS.num_r_ports,
OPTS.num_w_ports))
if OPTS.netlist_only:
debug.print_raw("Netlist only mode (no physical design is being done).")
debug.print_raw("Netlist only mode (no physical design is being done, netlist_only=False to disable).")
if not OPTS.route_supplies:
debug.print_raw("Design supply routing skipped for run-time (incomplete GDS will not be saved, route_supplies=True to enable).")
if not OPTS.inline_lvsdrc:
debug.print_raw("DRC/LVS/PEX is only run on the top-level design.")
debug.print_raw("DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to enable).")
if not OPTS.check_lvsdrc:
debug.print_raw("DRC/LVS/PEX is completely disabled.")
debug.print_raw("DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).")

2
compiler/modules/control_logic.py
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@ -14,7 +14,7 @@ class control_logic(design.design):
Dynamically generated Control logic for the total SRAM circuit.
"""
def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw"):
def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw", name=""):
""" Constructor """
name = "control_logic_" + port_type
design.design.__init__(self, name)

4
compiler/modules/tri_gate_array.py
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@ -10,9 +10,9 @@ class tri_gate_array(design.design):
Dynamically generated tri gate array of all bitlines. words_per_row
"""
def __init__(self, columns, word_size):
def __init__(self, columns, word_size, name):
"""Intial function of tri gate array """
design.design.__init__(self, "tri_gate_array")
design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name))
self.columns = columns

7
compiler/openram.py
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@ -48,8 +48,13 @@ debug.print_raw("Words per row: {}".format(c.words_per_row))
#from parser import *
output_extensions = ["sp","v","lib","py","html","log"]
# Only output lef/gds if back-end
if not OPTS.netlist_only:
output_extensions.extend(["gds","lef"])
output_extensions.extend(["lef"])
# Only output gds if final routing
if OPTS.route_supplies:
output_extensions.extend(["gds"])
output_files = ["{0}{1}.{2}".format(OPTS.output_path,OPTS.output_name,x) for x in output_extensions]
debug.print_raw("Output files are: ")
for path in output_files:

85
compiler/options.py
View File

@ -8,22 +8,74 @@ class options(optparse.Values):
that is the sole required command-line positional argument for openram.py.
"""
###################
# Configuration options
###################
# This is the technology directory.
openram_tech = ""
# This is the name of the technology.
tech_name = ""
# Port configuration (1-2 ports allowed)
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
# These will get initialized by the user or the tech file
supply_voltages = ""
temperatures = ""
process_corners = ""
# Size parameters must be specified by user in config file.
#num_words = 0
#word_size = 0
# You can manually specify banks, but it is better to auto-detect it.
num_banks = 1
###################
# Optimization options
###################
# Uses the delay chain size in the tech.py file rather automatic sizing.
use_tech_delay_chain_size = False
###################
# Debug options.
###################
# This is the temp directory where all intermediate results are stored.
openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
#openram_temp = "{0}/openram_temp/".format(os.getenv("HOME"))
try:
# If user defined the temporary location in their environment, use it
openram_temp = os.path.abspath(os.environ.get("OPENRAM_TMP"))
except:
# Else use a unique temporary directory
openram_temp = "/tmp/openram_{0}_{1}_temp/".format(getpass.getuser(),os.getpid())
# This is the verbosity level to control debug information. 0 is none, 1
# is minimal, etc.
debug_level = 0
###################
# Run-time vs accuracy options.
# Default, sacrifice accuracy/completeness for speed.
# Must turn on options for verification, final routing, etc.
###################
# When enabled, layout is not generated (and no DRC or LVS are performed)
netlist_only = False
# Whether we should do the final power routing
route_supplies = False
# This determines whether LVS and DRC is checked at all.
check_lvsdrc = True
check_lvsdrc = False
# This determines whether LVS and DRC is checked for every submodule.
inline_lvsdrc = False
# Remove noncritical memory cells for characterization speed-up
trim_netlist = True
# Run with extracted parasitics
use_pex = False
###################
# Tool options
###################
# Variable to select the variant of spice
spice_name = ""
# The spice executable being used which is derived from the user PATH.
@ -36,12 +88,9 @@ class options(optparse.Values):
drc_exe = None
lvs_exe = None
pex_exe = None
# Should we print out the banner at startup
print_banner = True
# Run with extracted parasitics
use_pex = False
# Remove noncritical memory cells for characterization speed-up
trim_netlist = True
# Use detailed LEF blockages
detailed_blockages = True
# Define the output file paths
@ -53,28 +102,10 @@ class options(optparse.Values):
# Purge the temp directory after a successful run (doesn't purge on errors, anyhow)
purge_temp = True
# These are the configuration parameters
num_rw_ports = 1
num_r_ports = 0
num_w_ports = 0
# These will get initialized by the the file
supply_voltages = ""
temperatures = ""
process_corners = ""
# These are the main configuration parameters that should be over-ridden
# in a configuration file.
#num_words = 0
#word_size = 0
# You can manually specify banks, but it is better to auto-detect it.
num_banks = 1
#Uses the delay chain size in the tech.py file rather automatic sizing.
use_tech_delay_chain_size = False
###################
# These are the default modules that can be over-riden
###################
bank_select = "bank_select"
bitcell_array = "bitcell_array"
bitcell = "bitcell"

2
compiler/run_profile.sh
View File

@ -1,3 +1,3 @@
#!/bin/bash
python3 -m cProfile -o profile.dat ./openram.py example_configs/medium_config_scn4m_subm.py -v | tee -i medium.log
python3 -m cProfile -o profile.dat ./openram.py example_configs/giant_config_scn4m_subm.py -v | tee -i big.log
echo "Run view_profile.py to view results"

17
compiler/sram.py
View File

@ -62,19 +62,22 @@ class sram():
""" Save all the output files while reporting time to do it as well. """
if not OPTS.netlist_only:
# Write the layout
start_time = datetime.datetime.now()
gdsname = OPTS.output_path + self.s.name + ".gds"
debug.print_raw("GDS: Writing to {0}".format(gdsname))
self.gds_write(gdsname)
print_time("GDS", datetime.datetime.now(), start_time)
# Create a LEF physical model
start_time = datetime.datetime.now()
lefname = OPTS.output_path + self.s.name + ".lef"
debug.print_raw("LEF: Writing to {0}".format(lefname))
self.lef_write(lefname)
print_time("LEF", datetime.datetime.now(), start_time)
if OPTS.route_supplies:
# Write the layout
start_time = datetime.datetime.now()
gdsname = OPTS.output_path + self.s.name + ".gds"
debug.print_raw("GDS: Writing to {0}".format(gdsname))
self.gds_write(gdsname)
print_time("GDS", datetime.datetime.now(), start_time)
# Save the spice file
start_time = datetime.datetime.now()

7
compiler/sram_base.py
View File

@ -111,7 +111,8 @@ class sram_base(design, verilog, lef):
self.height = highest_coord[1]
start_time = datetime.now()
self.DRC_LVS(final_verification=True)
# We only enable final verification if we have routed the design
self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True)
if not OPTS.is_unit_test:
print_time("Verification",datetime.now(), start_time)
@ -121,6 +122,10 @@ class sram_base(design, verilog, lef):
def route_supplies(self):
""" Route the supply grid and connect the pins to them. """
# Do not route the power supply
if not OPTS.route_supplies:
return
for inst in self.insts:
self.copy_power_pins(inst,"vdd")
self.copy_power_pins(inst,"gnd")

2
compiler/sram_factory.py
View File

@ -58,7 +58,7 @@ class sram_factory:
(obj_kwargs, obj_item) = obj
# Must have the same dictionary exactly (conservative)
if obj_kwargs == kwargs:
#debug.info(1, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs)))
debug.info(3, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs)))
return obj_item
# Use the default name if there are default arguments

2
compiler/tests/01_library_drc_test.py
View File

@ -12,7 +12,7 @@ import debug
class library_drc_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
import verify
(gds_dir, gds_files) = setup_files()

2
compiler/tests/02_library_lvs_test.py
View File

@ -12,7 +12,7 @@ import debug
class library_lvs_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
import verify
(gds_dir, sp_dir, allnames) = setup_files()

2
compiler/tests/03_contact_test.py
View File

@ -12,7 +12,7 @@ import debug
class contact_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
import contact

2
compiler/tests/03_path_test.py
View File

@ -12,7 +12,7 @@ import debug
class path_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
import wire_path
import tech
import design

13
compiler/tests/03_ptx_1finger_nmos_test.py
View File

@ -7,19 +7,20 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
class ptx_1finger_nmos_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
globals.init_openram("config_{0}".format(OPTS.tech_name))
import tech
debug.info(2, "Checking min size NMOS with 1 finger")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=1,
tx_type="nmos")
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=1,
tx_type="nmos")
self.local_drc_check(fet)
globals.end_openram()

13
compiler/tests/03_ptx_1finger_pmos_test.py
View File

@ -7,19 +7,20 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
class ptx_1finger_pmos_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
globals.init_openram("config_{0}".format(OPTS.tech_name))
import tech
debug.info(2, "Checking min size PMOS with 1 finger")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=1,
tx_type="pmos")
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=1,
tx_type="pmos")
self.local_drc_check(fet)
globals.end_openram()

17
compiler/tests/03_ptx_3finger_nmos_test.py
View File

@ -7,21 +7,22 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
class ptx_3finger_nmos_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
globals.init_openram("config_{0}".format(OPTS.tech_name))
import tech
debug.info(2, "Checking three fingers NMOS")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=3,
tx_type="nmos",
connect_active=True,
connect_poly=True)
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=3,
tx_type="nmos",
connect_active=True,
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()

17
compiler/tests/03_ptx_3finger_pmos_test.py
View File

@ -7,21 +7,22 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
class ptx_3finger_pmos_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
globals.init_openram("config_{0}".format(OPTS.tech_name))
import tech
debug.info(2, "Checking three fingers PMOS")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=3,
tx_type="pmos",
connect_active=True,
connect_poly=True)
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=3,
tx_type="pmos",
connect_active=True,
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()

17
compiler/tests/03_ptx_4finger_nmos_test.py
View File

@ -7,21 +7,22 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
class ptx_4finger_nmos_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
globals.init_openram("config_{0}".format(OPTS.tech_name))
import tech
debug.info(2, "Checking three fingers NMOS")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=4,
tx_type="nmos",
connect_active=True,
connect_poly=True)
fet = factory.create(module_type="ptx",
width= tech.drc["minwidth_tx"],
mults=4,
tx_type="nmos",
connect_active=True,
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()

15
compiler/tests/03_ptx_4finger_pmos_test.py
View File

@ -7,21 +7,22 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class ptx_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import ptx
globals.init_openram("config_{0}".format(OPTS.tech_name))
import tech
debug.info(2, "Checking three fingers PMOS")
fet = ptx.ptx(width=tech.drc["minwidth_tx"],
mults=4,
tx_type="pmos",
connect_active=True,
connect_poly=True)
fet = factory.create(module_type="ptx",
width=tech.drc["minwidth_tx"],
mults=4,
tx_type="pmos",
connect_active=True,
connect_poly=True)
self.local_drc_check(fet)
globals.end_openram()

2
compiler/tests/03_wire_test.py
View File

@ -12,7 +12,7 @@ import debug
class wire_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
import wire
import tech
import design

3
compiler/tests/04_pand2_test.py
View File

@ -9,12 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pand2_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
global verify
import verify

23
compiler/tests/04_pbitcell_test.py
View File

@ -16,15 +16,14 @@ from sram_factory import factory
class pbitcell_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from pbitcell import pbitcell
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.num_rw_ports=1
OPTS.num_w_ports=1
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=0
@ -32,7 +31,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 0 read/write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=1
@ -40,7 +39,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=1
factory.reset()
debug.info(2, "Bitcell with 0 write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=1
@ -48,7 +47,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=1
@ -56,7 +55,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
@ -64,7 +63,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=0
@ -72,7 +71,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 0 read/write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
@ -80,7 +79,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=2
factory.reset()
debug.info(2, "Bitcell with 0 write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
@ -88,7 +87,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
OPTS.num_rw_ports=2
@ -96,7 +95,7 @@ class pbitcell_test(openram_test):
OPTS.num_r_ports=0
factory.reset()
debug.info(2, "Bitcell with 0 read ports and 0 write ports")
tx = pbitcell(name="pbc")
tx = factory.create(module_type="pbitcell")
self.local_check(tx)
globals.end_openram()

9
compiler/tests/04_pbuf_test.py
View File

@ -9,19 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pbuf_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
import pbuf
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing inverter/buffer 4x 8x")
a = pbuf.pbuf(name="pbufx8", size=8)
a = factory.create(module_type="pbuf", size=8)
self.local_check(a)
globals.end_openram()

17
compiler/tests/04_pdriver_test.py
View File

@ -9,35 +9,32 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pdriver_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
import pdriver
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing inverter/buffer 4x 8x")
# a tests the error message for specifying conflicting conditions
#a = pdriver.pdriver(fanout = 4,size_list = [1,2,4,8])
#self.local_check(a)
b = pdriver.pdriver(name="pdriver1", size_list = [1,2,4,8])
b = factory.create(module_type="pdriver", size_list = [1,2,4,8])
self.local_check(b)
c = pdriver.pdriver(name="pdriver2", fanout = 50)
c = factory.create(module_type="pdriver", fanout = 50)
self.local_check(c)
d = pdriver.pdriver(name="pdriver3", fanout = 50, neg_polarity = True)
d = factory.create(module_type="pdriver", fanout = 50, neg_polarity = True)
self.local_check(d)
e = pdriver.pdriver(name="pdriver4", fanout = 64)
e = factory.create(module_type="pdriver", fanout = 64)
self.local_check(e)
f = pdriver.pdriver(name="pdriver5", fanout = 64, neg_polarity = True)
f = factory.create(module_type="pdriver", fanout = 64, neg_polarity = True)
self.local_check(f)
globals.end_openram()

9
compiler/tests/04_pinv_10x_test.py
View File

@ -9,17 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinv_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pinv
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Checking 10x inverter")
tx = pinv.pinv(name="pinvx10",size=8)
debug.info(2, "Checking 8x inverter")
tx = factory.create(module_type="pinv", size=8)
self.local_check(tx)
globals.end_openram()

7
compiler/tests/04_pinv_1x_beta_test.py
View File

@ -9,17 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinv_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pinv
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Checking 1x beta=3 size inverter")
tx = pinv.pinv(name="pinvx1b", size=1, beta=3)
tx = factory.create(module_type="pinv", size=1, beta=3)
self.local_check(tx)
globals.end_openram()

7
compiler/tests/04_pinv_1x_test.py
View File

@ -8,17 +8,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinv_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pinv
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Checking 1x size inverter")
tx = pinv.pinv(name="pinvx1", size=1)
tx = factory.create(module_type="pinv", size=1)
self.local_check(tx)
globals.end_openram()

7
compiler/tests/04_pinv_2x_test.py
View File

@ -9,17 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinv_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pinv
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Checking 2x size inverter")
tx = pinv.pinv(name="pinvx2", size=2)
tx = factory.create(module_type="pinv", size=2)
self.local_check(tx)
globals.end_openram()

6
compiler/tests/04_pinvbuf_test.py
View File

@ -9,16 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pinvbuf_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pinvbuf
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing inverter/buffer 4x 8x")
a = pinvbuf.pinvbuf(name="pinvufx8", size=8)
a = factory.create(module_type="pinvbuf", size=8)
self.local_check(a)
globals.end_openram()

7
compiler/tests/04_pnand2_test.py
View File

@ -11,17 +11,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pnand2_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pnand2
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Checking 2-input nand gate")
tx = pnand2.pnand2(name="pnand2", size=1)
tx = factory.create(module_type="pnand2", size=1)
self.local_check(tx)
globals.end_openram()

7
compiler/tests/04_pnand3_test.py
View File

@ -11,17 +11,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pnand3_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pnand3
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Checking 3-input nand gate")
tx = pnand3.pnand3(name="pnand3", size=1)
tx = factory.create(module_type="pnand3", size=1)
self.local_check(tx)
globals.end_openram()

7
compiler/tests/04_pnor2_test.py
View File

@ -11,17 +11,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class pnor2_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import pnor2
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Checking 2-input nor gate")
tx = pnor2.pnor2(name="pnor2", size=1)
tx = factory.create(module_type="pnor2", size=1)
self.local_check(tx)
globals.end_openram()

16
compiler/tests/04_precharge_test.py
View File

@ -9,19 +9,17 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class precharge_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import precharge
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
# check precharge in single port
debug.info(2, "Checking precharge for handmade bitcell")
tx = precharge.precharge(name="precharge_driver", size=1)
tx = factory.create(module_type="precharge", size=1)
self.local_check(tx)
# check precharge in multi-port
@ -32,15 +30,17 @@ class precharge_test(openram_test):
factory.reset()
debug.info(2, "Checking precharge for pbitcell (innermost connections)")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for pbitcell (innermost connections)")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl1", bitcell_br="br1")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for pbitcell (outermost connections)")
tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl2", bitcell_br="br2")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(tx)
globals.end_openram()

4
compiler/tests/04_replica_pbitcell_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class replica_pbitcell_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
import replica_pbitcell
OPTS.bitcell = "pbitcell"

12
compiler/tests/04_single_level_column_mux_test.py
View File

@ -9,21 +9,19 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 04_driver_test")
class single_level_column_mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import single_level_column_mux
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
# check single level column mux in single port
debug.info(2, "Checking column mux")
tx = single_level_column_mux.single_level_column_mux(name="mux8", tx_size=8)
tx = factory.create(module_type="single_level_column_mux", tx_size=8)
self.local_check(tx)
# check single level column mux in multi-port
@ -34,12 +32,12 @@ class single_level_column_mux_test(openram_test):
factory.reset()
debug.info(2, "Checking column mux for pbitcell (innermost connections)")
tx = single_level_column_mux.single_level_column_mux(name="mux8_2", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
tx = factory.create(module_type="single_level_column_mux", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking column mux for pbitcell (outermost connections)")
tx = single_level_column_mux.single_level_column_mux(name="mux8_3", tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
tx = factory.create(module_type="single_level_column_mux",tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(tx)
globals.end_openram()

6
compiler/tests/05_bitcell_1rw_1r_array_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 05_bitcell_1rw_1r_array_test")
@ -16,15 +17,14 @@ import debug
class bitcell_1rw_1r_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
a = bitcell_array.bitcell_array(name="bitcell_1rw_1r_array", cols=4, rows=4)
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()

6
compiler/tests/05_bitcell_array_test.py
View File

@ -9,6 +9,7 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 05_array_test")
@ -16,11 +17,10 @@ import debug
class array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing 4x4 array for 6t_cell")
a = bitcell_array.bitcell_array(name="bitcell_array", cols=4, rows=4)
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()

10
compiler/tests/05_pbitcell_array_test.py
View File

@ -9,21 +9,21 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 05_pbitcell_array_test")
class pbitcell_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bitcell_array
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 2
OPTS.num_r_ports = 2
OPTS.num_w_ports = 2
a = bitcell_array.bitcell_array(name="pbitcell_array_Rport_edge", cols=4, rows=4)
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell")
@ -31,7 +31,7 @@ class pbitcell_array_test(openram_test):
OPTS.num_rw_ports = 2
OPTS.num_r_ports = 0
OPTS.num_w_ports = 2
a = bitcell_array.bitcell_array(name="pbitcell_array_Wport_edge", cols=4, rows=4)
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
@ -39,7 +39,7 @@ class pbitcell_array_test(openram_test):
OPTS.num_rw_ports = 2
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
a = bitcell_array.bitcell_array(name="pbitcell_array_RWport_edge", cols=4, rows=4)
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()

23
compiler/tests/06_hierarchical_decoder_test.py
View File

@ -9,16 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class hierarchical_decoder_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import hierarchical_decoder
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
# Doesn't require hierarchical decoder
# debug.info(1, "Testing 4 row sample for hierarchical_decoder")
# a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4)
@ -31,19 +28,19 @@ class hierarchical_decoder_test(openram_test):
# check hierarchical decoder for single port
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
a = hierarchical_decoder.hierarchical_decoder(name="hd3", rows=16)
a = factory.create(module_type="hierarchical_decoder", rows=16)
self.local_check(a)
debug.info(1, "Testing 32 row sample for hierarchical_decoder")
a = hierarchical_decoder.hierarchical_decoder(name="hd4", rows=32)
a = factory.create(module_type="hierarchical_decoder", rows=32)
self.local_check(a)
debug.info(1, "Testing 128 row sample for hierarchical_decoder")
a = hierarchical_decoder.hierarchical_decoder(name="hd5", rows=128)
a = factory.create(module_type="hierarchical_decoder", rows=128)
self.local_check(a)
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
a = hierarchical_decoder.hierarchical_decoder(name="hd6", rows=512)
a = factory.create(module_type="hierarchical_decoder", rows=512)
self.local_check(a)
# check hierarchical decoder for multi-port
@ -54,19 +51,19 @@ class hierarchical_decoder_test(openram_test):
factory.reset()
debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
a = hierarchical_decoder.hierarchical_decoder(name="hd7", rows=16)
a = factory.create(module_type="hierarchical_decoder", rows=16)
self.local_check(a)
debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)")
a = hierarchical_decoder.hierarchical_decoder(name="hd8", rows=32)
a = factory.create(module_type="hierarchical_decoder", rows=32)
self.local_check(a)
debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)")
a = hierarchical_decoder.hierarchical_decoder(name="hd9", rows=128)
a = factory.create(module_type="hierarchical_decoder", rows=128)
self.local_check(a)
debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)")
a = hierarchical_decoder.hierarchical_decoder(name="hd10", rows=512)
a = factory.create(module_type="hierarchical_decoder", rows=512)
self.local_check(a)
globals.end_openram()

9
compiler/tests/06_hierarchical_predecode2x4_test.py
View File

@ -9,18 +9,17 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class hierarchical_predecode2x4_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import hierarchical_predecode2x4 as pre
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
# checking hierarchical precode 2x4 for single port
debug.info(1, "Testing sample for hierarchy_predecode2x4")
a = pre.hierarchical_predecode2x4(name="pre1")
a = factory.create(module_type="hierarchical_predecode2x4")
self.local_check(a)
# checking hierarchical precode 2x4 for multi-port
@ -30,7 +29,7 @@ class hierarchical_predecode2x4_test(openram_test):
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
a = pre.hierarchical_predecode2x4(name="pre2")
a = factory.create(module_type="hierarchical_predecode2x4")
self.local_check(a)
globals.end_openram()

9
compiler/tests/06_hierarchical_predecode3x8_test.py
View File

@ -9,18 +9,17 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class hierarchical_predecode3x8_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import hierarchical_predecode3x8 as pre
import tech
globals.init_openram("config_{0}".format(OPTS.tech_name))
# checking hierarchical precode 3x8 for single port
debug.info(1, "Testing sample for hierarchy_predecode3x8")
a = pre.hierarchical_predecode3x8(name="pre1")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
# checking hierarchical precode 3x8 for multi-port
@ -30,7 +29,7 @@ class hierarchical_predecode3x8_test(openram_test):
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
a = pre.hierarchical_predecode3x8(name="pre2")
a = factory.create(module_type="hierarchical_predecode3x8")
self.local_check(a)
globals.end_openram()

18
compiler/tests/07_single_level_column_mux_array_test.py
View File

@ -8,26 +8,26 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class single_level_column_mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
import single_level_column_mux_array
# check single level column mux array in single port
debug.info(1, "Testing sample for 2-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux1", columns=16, word_size=8)
a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8)
self.local_check(a)
debug.info(1, "Testing sample for 4-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux2", columns=16, word_size=4)
a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4)
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux3", columns=32, word_size=4)
a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4)
self.local_check(a)
# check single level column mux array in multi-port
@ -38,19 +38,19 @@ class single_level_column_mux_test(openram_test):
factory.reset()
debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux4", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 4-way column_mux_array in multi-port")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux5", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
a = factory.create(module_type="single_level_column_mux_array", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux6", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)")
a = single_level_column_mux_array.single_level_column_mux_array(name="mux7", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
a = factory.create(module_type="single_level_column_mux_array", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
self.local_check(a)
globals.end_openram()

9
compiler/tests/08_precharge_array_test.py
View File

@ -9,18 +9,17 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class precharge_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import precharge_array
globals.init_openram("config_{0}".format(OPTS.tech_name))
# check precharge array in single port
debug.info(2, "Checking 3 column precharge")
pc = precharge_array.precharge_array(name="pre1", columns=3)
pc = factory.create(module_type="precharge_array", columns=3)
self.local_check(pc)
# check precharge array in multi-port
@ -31,7 +30,7 @@ class precharge_test(openram_test):
factory.reset()
debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
pc = precharge_array.precharge_array(name="pre2", columns=3, bitcell_bl="bl0", bitcell_br="br0")
pc = factory.create(module_type="precharge_array", columns=3, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(pc)
# debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")

9
compiler/tests/08_wordline_driver_test.py
View File

@ -9,20 +9,19 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 04_driver_test")
class wordline_driver_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import wordline_driver
globals.init_openram("config_{0}".format(OPTS.tech_name))
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = wordline_driver.wordline_driver(name="wld1", rows=8, cols=32)
tx = factory.create(module_type="wordline_driver", rows=8, cols=32)
self.local_check(tx)
# check wordline driver for multi-port
@ -33,7 +32,7 @@ class wordline_driver_test(openram_test):
factory.reset()
debug.info(2, "Checking driver (multi-port case)")
tx = wordline_driver.wordline_driver(name="wld2", rows=8, cols=64)
tx = factory.create(module_type="wordline_driver", rows=8, cols=64)
self.local_check(tx)
globals.end_openram()

13
compiler/tests/09_sense_amp_array_test.py
View File

@ -9,22 +9,21 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class sense_amp_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import sense_amp_array
globals.init_openram("config_{0}".format(OPTS.tech_name))
# check sense amp array for single port
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
a = sense_amp_array.sense_amp_array(name="sa1", word_size=4, words_per_row=2)
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
self.local_check(a)
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
a = sense_amp_array.sense_amp_array(name="sa2", word_size=4, words_per_row=4)
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
self.local_check(a)
# check sense amp array for multi-port
@ -35,11 +34,11 @@ class sense_amp_test(openram_test):
factory.reset()
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
a = sense_amp_array.sense_amp_array(name="sa3", word_size=4, words_per_row=2)
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
self.local_check(a)
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
a = sense_amp_array.sense_amp_array(name="sa4", word_size=4, words_per_row=4)
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
self.local_check(a)
globals.end_openram()

13
compiler/tests/10_write_driver_array_test.py
View File

@ -9,22 +9,21 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class write_driver_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import write_driver_array
globals.init_openram("config_{0}".format(OPTS.tech_name))
# check write driver array for single port
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
a = write_driver_array.write_driver_array(name="wd1", columns=8, word_size=8)
a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
a = write_driver_array.write_driver_array(name="wd2", columns=16, word_size=8)
a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
self.local_check(a)
# check write driver array for multi-port
@ -35,11 +34,11 @@ class write_driver_test(openram_test):
factory.reset()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
a = write_driver_array.write_driver_array(name="wd3", columns=8, word_size=8)
a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
a = write_driver_array.write_driver_array(name="wd4", columns=16, word_size=8)
a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()

10
compiler/tests/11_dff_array_test.py
View File

@ -9,24 +9,24 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class dff_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import dff_array
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing dff_array for 3x3")
a = dff_array.dff_array(rows=3, columns=3)
a = factory.create(module_type="dff_array", rows=3, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_array for 1x3")
a = dff_array.dff_array(rows=1, columns=3)
a = factory.create(module_type="dff_array", rows=1, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_array for 3x1")
a = dff_array.dff_array(rows=3, columns=1)
a = factory.create(module_type="dff_array", rows=3, columns=1)
self.local_check(a)
globals.end_openram()

10
compiler/tests/11_dff_buf_array_test.py
View File

@ -9,24 +9,24 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class dff_buf_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import dff_buf_array
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing dff_buf_array for 3x3")
a = dff_buf_array.dff_buf_array(rows=3, columns=3)
a = factory.create(module_type="dff_buf_array", rows=3, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_buf_array for 1x3")
a = dff_buf_array.dff_buf_array(rows=1, columns=3)
a = factory.create(module_type="dff_buf_array", rows=1, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_buf_array for 3x1")
a = dff_buf_array.dff_buf_array(rows=3, columns=1)
a = factory.create(module_type="dff_buf_array", rows=3, columns=1)
self.local_check(a)
globals.end_openram()

6
compiler/tests/11_dff_buf_test.py
View File

@ -9,16 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class dff_buf_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import dff_buf
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing dff_buf 4x 8x")
a = dff_buf.dff_buf(4, 8)
a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8)
self.local_check(a)
globals.end_openram()

8
compiler/tests/12_tri_gate_array_test.py
View File

@ -9,20 +9,20 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class tri_gate_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import tri_gate_array
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")
a = tri_gate_array.tri_gate_array(columns=8, word_size=8)
a = factory.create(module_type="tri_gate_array", columns=8, word_size=8)
self.local_check(a)
debug.info(1, "Testing tri_gate_array for columns=16, word_size=8")
a = tri_gate_array.tri_gate_array(columns=16, word_size=8)
a = factory.create(module_type="tri_gate_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()

6
compiler/tests/13_delay_chain_test.py
View File

@ -9,16 +9,16 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class delay_chain_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import delay_chain
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing delay_chain")
a = delay_chain.delay_chain(name="dc", fanout_list=[4, 4, 4, 4])
a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4])
self.local_check(a)
globals.end_openram()

11
compiler/tests/14_replica_bitline_multiport_test.py
View File

@ -9,14 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
class replica_bitline_multiport_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import replica_bitline
globals.init_openram("config_{0}".format(OPTS.tech_name))
stages=4
fanout=4
@ -30,7 +29,7 @@ class replica_bitline_multiport_test(openram_test):
factory.reset()
debug.info(2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(name="rbl1", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
self.local_check(a)
# check replica bitline in pbitcell multi-port
@ -42,7 +41,7 @@ class replica_bitline_multiport_test(openram_test):
factory.reset()
debug.info(2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(name="rbl2", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
self.local_check(a)
OPTS.num_rw_ports = 1
@ -51,7 +50,7 @@ class replica_bitline_multiport_test(openram_test):
factory.reset()
debug.info(2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(name="rbl3", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
self.local_check(a)
globals.end_openram()

10
compiler/tests/14_replica_bitline_test.py
View File

@ -9,30 +9,28 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class replica_bitline_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import replica_bitline
globals.init_openram("config_{0}".format(OPTS.tech_name))
# check replica bitline in single port
stages=4
fanout=4
rows=13
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(name="rbl1", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
self.local_check(a)
#debug.error("Exiting...", 1)
stages=8
rows=100
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(name="rbl2", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
self.local_check(a)
globals.end_openram()
# run the test from the command line

13
compiler/tests/16_control_logic_test.py
View File

@ -9,18 +9,19 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class control_logic_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
import control_logic
import tech
# check control logic for single port
debug.info(1, "Testing sample for control_logic")
a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=32)
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
self.local_check(a)
# check control logic for multi-port
@ -31,7 +32,7 @@ class control_logic_test(openram_test):
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for control_logic for multiport")
a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8)
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8)
self.local_check(a)
# Check port specific control logic
@ -40,19 +41,19 @@ class control_logic_test(openram_test):
OPTS.num_r_ports = 0
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="rw")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="rw")
self.local_check(a)
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1
debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="w")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="w")
self.local_check(a)
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
debug.info(1, "Testing sample for control_logic for multiport, only read control logic")
a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="r")
a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=8, port_type="r")
self.local_check(a)
globals.end_openram()

12
compiler/tests/19_bank_select_test.py
View File

@ -9,21 +9,21 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class bank_select_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
import bank_select
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(1, "No column mux, rw control logic")
a = bank_select.bank_select(port="rw")
a = factory.create(module_type="bank_select", port="rw")
self.local_check(a)
OPTS.bitcell = "pbitcell"
debug.info(1, "No column mux, rw control logic")
a = bank_select.bank_select(port="rw")
a = factory.create(module_type="bank_select", port="rw")
self.local_check(a)
OPTS.num_rw_ports = 0
@ -31,11 +31,11 @@ class bank_select_test(openram_test):
OPTS.num_r_ports = 1
debug.info(1, "No column mux, w control logic")
a = bank_select.bank_select(port="w")
a = factory.create(module_type="bank_select", port="w")
self.local_check(a)
debug.info(1, "No column mux, r control logic")
a = bank_select.bank_select(port="r")
a = factory.create(module_type="bank_select", port="r")
self.local_check(a)
globals.end_openram()

16
compiler/tests/19_multi_bank_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 19_multi_bank_test")
class multi_bank_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from bank import bank
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
c = sram_config(word_size=4,
@ -24,31 +24,35 @@ class multi_bank_test(openram_test):
c.num_banks=2
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = bank(c, name="bank1_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = bank(c, name="bank2_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = bank(c, name="bank3_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = bank(c, name="bank4_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()

20
compiler/tests/19_pmulti_bank_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("SKIPPING 19_pmulti_bank_test")
class multi_bank_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from bank import bank
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
@ -29,27 +29,35 @@ class multi_bank_test(openram_test):
c.num_banks=2
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = bank(c, name="bank1_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = bank(c, name="bank2_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = bank(c, name="bank3_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = bank(c, name="bank4_multi")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()

4
compiler/tests/19_psingle_bank_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 19_psingle_bank_test")
class psingle_bank_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
from bank import bank
from sram_config import sram_config
OPTS.bitcell = "pbitcell"

20
compiler/tests/19_single_bank_1rw_1r_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class single_bank_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from bank import bank
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
@ -27,27 +27,35 @@ class single_bank_1rw_1r_test(openram_test):
num_words=16)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = bank(c, name="bank1_single")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = bank(c, name="bank2_single")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = bank(c, name="bank3_single")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = bank(c, name="bank4_single")
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
globals.end_openram()

20
compiler/tests/19_single_bank_test.py
View File

@ -9,40 +9,48 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class single_bank_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from bank import bank
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=16)
c.words_per_row=1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = bank(c, name="bank1_single")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=32
c.words_per_row=2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = bank(c, name="bank2_single")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.num_words=64
c.words_per_row=4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = bank(c, name="bank3_single")
a = factory.create("bank", sram_config=c)
self.local_check(a)
c.word_size=2
c.num_words=128
c.words_per_row=8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = bank(c, name="bank4_single")
a = factory.create("bank", sram_config=c)
self.local_check(a)
globals.end_openram()

22
compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
class psram_1bank_2mux_1rw_1w_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@ -31,14 +31,16 @@ class psram_1bank_2mux_1rw_1w_test(openram_test):
c.num_words=32
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w psram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

6
compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@ -38,7 +38,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

22
compiler/tests/20_psram_1bank_2mux_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error")
class psram_1bank_2mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@ -32,14 +32,16 @@ class psram_1bank_2mux_test(openram_test):
c.num_words=32
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w psram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

22
compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class psram_1bank_4mux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
@ -30,14 +30,16 @@ class psram_1bank_4mux_1rw_1r_test(openram_test):
c.num_words=64
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w psram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

22
compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class sram_1bank_2mux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "bitcell_1rw_1r"
@ -30,14 +30,16 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

22
compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "bitcell_1w_1r"
OPTS.replica_bitcell="replica_bitcell_1w_1r"
@ -31,14 +31,16 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
c.num_words=32
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w psram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

22
compiler/tests/20_sram_1bank_2mux_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_sram_1bank_2mux_test")
class sram_1bank_2mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
@ -24,14 +24,16 @@ class sram_1bank_2mux_test(openram_test):
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

22
compiler/tests/20_sram_1bank_4mux_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_sram_1bank_4mux_test")
class sram_1bank_4mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=64,
@ -24,14 +24,16 @@ class sram_1bank_4mux_test(openram_test):
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

22
compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class sram_1bank_8mux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "bitcell_1rw_1r"
@ -30,14 +30,16 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

22
compiler/tests/20_sram_1bank_8mux_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_sram_1bank_8mux_test")
class sram_1bank_8mux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
c = sram_config(word_size=2,
num_words=128,
@ -24,14 +24,16 @@ class sram_1bank_8mux_test(openram_test):
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

22
compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class sram_1bank_nomux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "bitcell_1rw_1r"
@ -30,14 +30,16 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

22
compiler/tests/20_sram_1bank_nomux_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 20_sram_1bank_nomux_test")
class sram_1bank_nomux_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=16,
@ -24,14 +24,16 @@ class sram_1bank_nomux_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w sram with {} bit words, {} words, {} words per row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = sram(c, "sram")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

56
compiler/tests/20_sram_2bank_test.py
View File

@ -9,14 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
@unittest.skip("Multibank is not working yet.")
class sram_2bank_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
from sram import sram
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
c = sram_config(word_size=16,
num_words=32,
@ -24,30 +24,66 @@ class sram_2bank_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Two bank, no column mux with control logic")
a = sram(c, "sram1")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
c.num_words=64
c.words_per_row=2
c.recompute_sizes()
debug.info(1, "Two bank two way column mux with control logic")
a = sram(c, "sram2")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
c.num_words=128
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Two bank, four way column mux with control logic")
a = sram(c, "sram3")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
c.word_size=2
c.num_words=256
c.words_per_row=8
c.recompute_sizes()
debug.info(1, "Two bank, eight way column mux with control logic")
a = sram(c, "sram4")
debug.info(1, "Layout test for {}rw,{}r,{}w sram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
factory.reset()
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()

6
compiler/tests/21_hspice_delay_test.py
View File

@ -9,12 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class timing_sram_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.spice_name="hspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
@ -24,7 +25,6 @@ class timing_sram_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1,
num_words=16,
@ -32,7 +32,7 @@ class timing_sram_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

3
compiler/tests/21_hspice_setuphold_test.py
View File

@ -9,12 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class timing_setup_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.spice_name="hspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True

6
compiler/tests/21_model_delay_test.py
View File

@ -9,13 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class model_delay_sram_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
#OPTS.spice_name="hspice"
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
@ -32,7 +32,7 @@ class model_delay_sram_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

6
compiler/tests/21_ngspice_delay_test.py
View File

@ -9,12 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class timing_sram_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.spice_name="ngspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
@ -24,7 +25,6 @@ class timing_sram_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=1,
num_words=16,
@ -32,7 +32,7 @@ class timing_sram_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram(c, name="sram1")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

3
compiler/tests/21_ngspice_setuphold_test.py
View File

@ -9,12 +9,13 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
class timing_setup_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.spice_name="ngspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True

6
compiler/tests/22_psram_1bank_2mux_func_test.py
View File

@ -9,13 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_2mux_1rw_1r_1w_func_test, third port reads are broken?")
class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
@ -30,7 +31,6 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=64,
@ -44,7 +44,7 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

6
compiler/tests/22_psram_1bank_4mux_func_test.py
View File

@ -9,13 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test, third port reads are broken?")
class psram_1bank_4mux_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
@ -30,7 +31,6 @@ class psram_1bank_4mux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=256,
@ -44,7 +44,7 @@ class psram_1bank_4mux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

6
compiler/tests/22_psram_1bank_8mux_func_test.py
View File

@ -9,13 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_8mux_func_test")
class psram_1bank_8mux_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
@ -30,7 +31,6 @@ class psram_1bank_8mux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=256,
@ -44,7 +44,7 @@ class psram_1bank_8mux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

6
compiler/tests/22_psram_1bank_nomux_func_test.py
View File

@ -9,13 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_psram_1bank_nomux_func_test")
class psram_1bank_nomux_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
@ -30,7 +31,6 @@ class psram_1bank_nomux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
@ -44,7 +44,7 @@ class psram_1bank_nomux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

6
compiler/tests/22_sram_1bank_2mux_func_test.py
View File

@ -9,13 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_1bank_2mux_func_test")
class sram_1bank_2mux_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
@ -25,7 +26,6 @@ class sram_1bank_2mux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=64,
@ -36,7 +36,7 @@ class sram_1bank_2mux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

6
compiler/tests/22_sram_1bank_4mux_func_test.py
View File

@ -9,13 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_1bank_4mux_func_test")
class sram_1bank_4mux_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
@ -25,7 +26,6 @@ class sram_1bank_4mux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=256,
@ -36,7 +36,7 @@ class sram_1bank_4mux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

6
compiler/tests/22_sram_1bank_8mux_func_test.py
View File

@ -9,13 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_1bank_8mux_func_test")
class sram_1bank_8mux_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
@ -28,7 +29,6 @@ class sram_1bank_8mux_func_test(openram_test):
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=256,
@ -39,7 +39,7 @@ class sram_1bank_8mux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

6
compiler/tests/22_sram_1bank_nomux_func_test.py
View File

@ -9,13 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_func_test")
class sram_1bank_nomux_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
@ -24,7 +25,6 @@ class sram_1bank_nomux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
@ -35,7 +35,7 @@ class sram_1bank_nomux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

6
compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py
View File

@ -9,13 +9,14 @@ import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
from sram_factory import factory
import debug
#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test")
class psram_1bank_nomux_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
@ -30,7 +31,6 @@ class psram_1bank_nomux_func_test(openram_test):
import characterizer
reload(characterizer)
from characterizer import functional, delay
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
@ -41,7 +41,7 @@ class psram_1bank_nomux_func_test(openram_test):
c.num_words,
c.words_per_row,
c.num_banks))
s = sram(c, name="sram")
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

7
compiler/tests/23_lib_sram_model_corners_test.py
View File

@ -14,7 +14,7 @@ import debug
class model_corners_lib_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
from characterizer import lib
from sram import sram
@ -25,7 +25,10 @@ class model_corners_lib_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, name="sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

7
compiler/tests/23_lib_sram_model_test.py
View File

@ -14,8 +14,8 @@ import debug
class lib_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.netlist_only = True
globals.init_openram("config_{0}".format(OPTS.tech_name))
from characterizer import lib
from sram import sram
from sram_config import sram_config
@ -25,6 +25,9 @@ class lib_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing analytical timing for sample 2 bit, 16 words SRAM with 1 bank")
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)

5
compiler/tests/23_lib_sram_prune_test.py
View File

@ -14,7 +14,7 @@ import debug
class lib_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.analytical_delay = False
OPTS.trim_netlist = True
@ -34,6 +34,9 @@ class lib_test(openram_test):
c.words_per_row=1
c.recompute_sizes()
debug.info(1, "Testing pruned timing for sample 2 bit, 16 words SRAM with 1 bank")
# This doesn't have to use the factory since worst case
# it will just replaece the top-level module of the same name
s = sram(c, "sram_2_16_1_{0}".format(OPTS.tech_name))
tempspice = OPTS.openram_temp + "temp.sp"

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