mirror of https://github.com/VLSIDA/OpenRAM.git
Modified some testing and initial delay chain sizes.
This commit is contained in:
Hunter Nichols
parent
8d7823e4dd
commit
12723adb0c
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@ -5,3 +5,4 @@
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*.out
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*.toc
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*.synctex.gz
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**/model_data
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@ -227,7 +227,11 @@ class model_check(delay):
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def get_num_delay_stages(self):
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"""Gets the number of stages in the delay chain from the control logic"""
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return len(self.sram.control_logic_rw.replica_bitline.delay_fanout_list)
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def get_num_delay_stage_fanout(self):
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"""Gets fanout in each stage in the delay chain. Assumes each stage is the same"""
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return self.sram.control_logic_rw.replica_bitline.delay_fanout_list[0]
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def get_num_wl_en_driver_stages(self):
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"""Gets the number of stages in the wl_en driver from the control logic"""
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return self.sram.control_logic_rw.wl_en_driver.num_stages
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@ -30,13 +30,13 @@ class control_logic(design.design):
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self.port_type = port_type
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self.num_cols = word_size*words_per_row
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self.num_words = num_rows * words_per_row
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self.num_words = num_rows*words_per_row
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self.enable_delay_chain_resizing = False
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self.enable_delay_chain_resizing = True
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#self.sram=None #disable re-sizing for debugging, FIXME: resizing is not working, needs to be adjusted for new control logic.
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self.wl_timing_tolerance = 1 #Determines how much larger the sen delay should be. Accounts for possible error in model.
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self.parasitic_inv_delay = parameter["min_inv_para_delay"] #Keeping 0 for now until further testing.
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#Determines how much larger the sen delay should be. Accounts for possible error in model.
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self.wl_timing_tolerance = 1
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self.parasitic_inv_delay = parameter["min_inv_para_delay"]
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self.wl_stage_efforts = None
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self.sen_stage_efforts = None
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@ -159,16 +159,16 @@ class control_logic(design.design):
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#Resize if necessary, condition depends on resizing method
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if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match():
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#This resizes to match fall and rise delays, can make the delay chain weird sizes.
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# stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
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# self.replica_bitline = factory.create(module_type="replica_bitline",
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# delay_fanout_list=stage_list,
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# bitcell_loads=bitcell_loads)
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stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
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self.replica_bitline = factory.create(module_type="replica_bitline",
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delay_fanout_list=stage_list,
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bitcell_loads=bitcell_loads)
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#This resizes based on total delay.
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delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic)
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self.replica_bitline = factory.create(module_type="replica_bitline",
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delay_fanout_list=[delay_fanout]*delay_stages,
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bitcell_loads=bitcell_loads)
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# delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic)
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# self.replica_bitline = factory.create(module_type="replica_bitline",
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# delay_fanout_list=[delay_fanout]*delay_stages,
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# bitcell_loads=bitcell_loads)
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self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
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self.delay_chain_resized = True
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@ -177,13 +177,10 @@ class control_logic(design.design):
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def get_heuristic_delay_chain_size(self):
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"""Use a basic heuristic to determine the size of the delay chain used for the Sense Amp Enable """
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# FIXME: These should be tuned according to the additional size parameters
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delay_fanout = 3 # This can be anything >=2
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delay_fanout = 2 # This can be anything >=2
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# Delay stages Must be non-inverting
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if self.words_per_row >= 4:
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delay_stages = 8
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elif self.words_per_row == 2:
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delay_stages = 6
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if self.words_per_row >= 2:
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delay_stages = 4
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else:
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delay_stages = 2
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@ -247,6 +244,8 @@ class control_logic(design.design):
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required_delay_rise = self.wl_delay_rise*self.wl_timing_tolerance - (self.sen_delay_rise-previous_delay_chain_delay/2)
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debug.info(2,"Required delays from chain: fall={}, rise={}".format(required_delay_fall,required_delay_rise))
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#If the fanout is different between rise/fall by this amount. Stage algorithm is made more pessimistic.
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WARNING_FANOUT_DIFF = 5
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#The stages need to be equal (or at least a even number of stages with matching rise/fall delays)
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while True:
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stages_fall = self.calculate_stages_with_fixed_fanout(required_delay_fall,fanout_fall)
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@ -254,7 +253,8 @@ class control_logic(design.design):
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debug.info(1,"Fall stages={}, rise stages={}".format(stages_fall,stages_rise))
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if stages_fall == stages_rise:
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break
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elif abs(stages_fall-stages_rise) == 1:
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elif abs(stages_fall-stages_rise) == 1 and WARNING_FANOUT_DIFF < abs(fanout_fall-fanout_rise):
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debug.info(1, "Delay chain fanouts between stages are large. Making chain size larger for safety.")
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break
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#There should also be a condition to make sure the fanout does not get too large.
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#Otherwise, increase the fanout of delay with the most stages, calculate new stages
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@ -4,6 +4,7 @@ Run a regression test on various srams
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"""
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import csv,sys,os
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import pandas as pd
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import matplotlib.pyplot as plt
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import unittest
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from testutils import header,openram_test
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@ -19,13 +20,14 @@ MODEL_DIR = "model_data/"
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class data_collection(openram_test):
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def runTest(self):
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word_size, num_words, words_per_row = 4, 16, 1
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self.init_data_gen()
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self.set_delay_chain(2,3)
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self.save_data_sram_corners(word_size, num_words, words_per_row)
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wl_dataframe, sae_dataframe = self.get_csv_data()
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self.evaluate_data(wl_dataframe, sae_dataframe)
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ratio_data = self.calculate_delay_ratios_of_srams()
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self.display_data(ratio_data)
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# word_size, num_words, words_per_row = 4, 16, 1
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# self.init_data_gen()
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# self.set_delay_chain(2,3)
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# self.save_data_sram_corners(word_size, num_words, words_per_row)
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# wl_dataframe, sae_dataframe = self.get_csv_data()
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# self.evaluate_data(wl_dataframe, sae_dataframe)
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#Run again but with different delay chain sizes
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# self.init_data_gen()
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@ -34,12 +36,27 @@ class data_collection(openram_test):
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# wl_dataframe, sae_dataframe = self.get_csv_data()
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# self.evaluate_data(wl_dataframe, sae_dataframe)
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model_delay_ratios, meas_delay_ratios, ratio_error = self.compare_model_to_measure()
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debug.info(1, "model_delay_ratios={}".format(model_delay_ratios))
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debug.info(1, "meas_delay_ratios={}".format(meas_delay_ratios))
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debug.info(1, "ratio_error={}".format(ratio_error))
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globals.end_openram()
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# model_delay_ratios, meas_delay_ratios, ratio_error = self.compare_model_to_measure()
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# debug.info(1, "model_delay_ratios={}".format(model_delay_ratios))
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# debug.info(1, "meas_delay_ratios={}".format(meas_delay_ratios))
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# debug.info(1, "ratio_error={}".format(ratio_error))
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# globals.end_openram()
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def calculate_delay_ratios_of_srams(self):
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"""Runs delay measurements on several sram configurations.
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Computes the delay ratio for each one."""
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delay_ratio_data = {}
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config_tuple_list = [(32, 1024, None)]
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#config_tuple_list = [(1, 16, 1),(4, 16, 1), (16, 16, 1), (32, 32, 1)]
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for sram_config in config_tuple_list:
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word_size, num_words, words_per_row = sram_config
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self.init_data_gen()
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self.save_data_sram_corners(word_size, num_words, words_per_row)
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model_delay_ratios, meas_delay_ratios, ratio_error = self.compare_model_to_measure()
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delay_ratio_data[sram_config] = ratio_error
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debug.info(1, "Ratio percentage error={}".format(ratio_error))
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return delay_ratio_data
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def get_csv_data(self):
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"""Hardcoded Hack to get the measurement data from the csv into lists. """
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wl_files_name = [file_name for file_name in self.file_names if "wl_measures" in file_name][0]
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@ -79,11 +96,30 @@ class data_collection(openram_test):
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corner = (wl_meas[proc_pos+1], wl_meas[volt_pos+1], wl_meas[temp_pos+1])
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meas_delay_ratios[corner] = wl_meas[wl_sum_pos+1]/sae_meas[sae_sum_pos+1]
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model_delay_ratios[corner] = wl_model[wl_sum_pos+1]/sae_model[sae_sum_pos+1]
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debug.info(1,"wl_model sum={}, sae_model_sum={}".format(wl_model[wl_sum_pos+1], sae_model[sae_sum_pos+1]))
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ratio_error[corner] = 100*abs(model_delay_ratios[corner]-meas_delay_ratios[corner])/meas_delay_ratios[corner]
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#Not using absolute error, positive error means model was larger, negative error means it was smaller.
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ratio_error[corner] = 100*(model_delay_ratios[corner]-meas_delay_ratios[corner])/meas_delay_ratios[corner]
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return model_delay_ratios, meas_delay_ratios, ratio_error
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def display_data(self, data):
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"""Displays the ratio data using matplotlib (requires graphics)"""
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config_data = []
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xticks = []
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#Organize data
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#First key level if the sram configuration (wordsize, num words, words per row)
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for config,corner_data_dict in data.items():
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#Second level is the corner data for that configuration.
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for corner, corner_data in corner_data_dict.items():
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#Right now I am only testing with a single corner, will not work with more than 1 corner
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config_data.append(corner_data)
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xticks.append("{}b,{}w,{}wpr".format(*config))
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#plot data
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data_range = [i+1 for i in range(len(data))]
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shapes = ['ro', 'bo', 'go', 'co', 'mo']
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plt.xticks(data_range, xticks)
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plt.plot(data_range, config_data, 'ro')
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plt.show()
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def calculate_delay_error(self, wl_dataframe, sae_dataframe):
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"""Calculates the percentage difference in delays between the wordline and sense amp enable"""
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start_data_pos = len(self.config_fields) #items before this point are configuration related
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@ -123,6 +159,9 @@ class data_collection(openram_test):
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def save_data_sram_corners(self, word_size, num_words, words_per_row):
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"""Performs corner analysis on a single SRAM configuration"""
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self.create_sram(word_size, num_words, words_per_row)
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#Setting to none forces SRAM to determine the value. Must be checked after sram creation
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if not words_per_row:
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words_per_row = self.sram.s.words_per_row
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#Run on one size to initialize CSV writing (csv names come from return value). Strange, but it is okay for now.
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corner_gen = self.corner_combination_generator()
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init_corner = next(corner_gen)
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@ -150,7 +189,7 @@ class data_collection(openram_test):
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OPTS.trim_netlist = False
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OPTS.netlist_only = True
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OPTS.analytical_delay = False
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OPTS.use_tech_delay_chain_size = True
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#OPTS.use_tech_delay_chain_size = True
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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@ -209,13 +248,16 @@ class data_collection(openram_test):
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self.csv_files = {}
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self.csv_writers = {}
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self.file_names = []
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delay_stages = self.delay_obj.get_num_delay_stages()
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delay_stage_fanout = self.delay_obj.get_num_delay_stage_fanout()
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for data_name, header_list in header_dict.items():
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file_name = '{}data_{}b_{}word_{}way_dc{}x{}_{}.csv'.format(MODEL_DIR,
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word_size,
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num_words,
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words_per_row,
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parameter["static_delay_stages"],
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parameter["static_fanout_per_stage"],
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delay_stages,
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delay_stage_fanout,
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data_name)
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self.file_names.append(file_name)
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self.csv_files[data_name] = open(file_name, 'w')
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@ -238,13 +280,11 @@ class data_collection(openram_test):
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self.sram_spice = OPTS.openram_temp + "temp.sp"
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self.sram.sp_write(self.sram_spice)
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debug.info(1, "SRAM column address size={}".format(self.sram.s.col_addr_size))
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def get_sram_data(self, corner):
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"""Generates the delay object using the corner and runs a simulation for data."""
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from characterizer import model_check
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self.delay_obj = model_check(self.sram.s, self.sram_spice, corner)
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import tech
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#Only 1 at a time
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probe_address = "1" * self.sram.s.addr_size
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@ -253,6 +293,7 @@ class data_collection(openram_test):
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slews = [tech.spice["rise_time"]*2]
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sram_data = self.delay_obj.analyze(probe_address,probe_data,slews,loads)
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return sram_data
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def remove_lists_from_dict(self, dict):
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@ -1,2 +0,0 @@
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0,sum
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4,16,1,False,TT,1.0,25,0.020618,0.0062215,0.018563000000000003,0.017233000000000002,0.007710799999999999,0.0099965,0.045221000000000004,0.12556380000000003
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@ -1,2 +0,0 @@
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0,sum
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4,16,1,False,TT,1.0,25,8.8,2.65,6.4,7.4,3.4,7.15,7.15,42.949999999999996
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@ -1,2 +0,0 @@
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15,sum
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4,16,1,False,TT,1.0,25,0.010512,0.0089216,0.014109,0.013643,0.014564,0.0086745,0.0704241
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@ -1,2 +0,0 @@
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15,sum
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4,16,1,False,TT,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4,32.13333333333334
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@ -1,2 +0,0 @@
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0,sum
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4,16,1,False,TT,1.0,25,0.020572,0.006256,0.015678,0.014110000000000001,0.017755,0.013415,0.0076344,0.010162,0.04153,0.14711239999999998
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@ -1,2 +0,0 @@
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xand2_rbl_in.zb_int,Xsram.Xcontrol0.rbl_in,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_1,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_2,Xsram.Xcontrol0.Xreplica_bitline.Xdelay_chain.dout_3,Xsram.Xcontrol0.Xreplica_bitline.delayed_en,Xsram.Xcontrol0.pre_s_en,Xsram.Xcontrol0.Xbuf_s_en.Zb1_int,Xsram.s_en0,sum
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4,16,1,False,TT,1.0,25,8.8,2.65,5.4,5.4,5.4,6.4,3.4,7.15,7.15,51.74999999999999
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@ -1,2 +0,0 @@
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15,sum
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4,16,1,False,TT,1.0,25,0.010463,0.0089004,0.014107,0.013630000000000001,0.0146,0.0086902,0.0703906
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@ -1,2 +0,0 @@
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word_size,num_words,words_per_row,dc_resized,process,voltage,temp,Xsram.Xcontrol0.Xbuf_wl_en.Zb1_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb2_int,Xsram.Xcontrol0.Xbuf_wl_en.Zb3_int,Xsram.wl_en0,Xsram.Xbank0.Xwordline_driver0.wl_bar_15,Xsram.Xbank0.wl_15,sum
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4,16,1,False,TT,1.0,25,5.4,5.4,5.733333333333333,4.4,5.8,5.4,32.13333333333334
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Reference in New Issue