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Revert bus bits back into pins

This commit is contained in:
Matt Guthaus 2019-02-22 16:22:27 -08:00
parent d043c72277
commit 583dc4410b
3 changed files with 9 additions and 9 deletions
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6
compiler/characterizer/lib.py
View File

@ -327,7 +327,7 @@ class lib:
self.lib.write(" }\n")
self.lib.write(" pin(DOUT{}){{\n".format(read_port))
self.lib.write(" pin(DOUT{0}[{1}:0]){{\n".format(read_port,self.sram.word_size-1))
self.lib.write(" timing(){ \n")
self.lib.write(" timing_sense : non_unate; \n")
self.lib.write(" related_pin : \"clk{0}\"; \n".format(read_port))
@ -360,7 +360,7 @@ class lib:
self.lib.write(" address : ADDR{0}; \n".format(write_port))
self.lib.write(" clocked_on : clk{0}; \n".format(write_port))
self.lib.write(" }\n")
self.lib.write(" pin(DIN{}){{\n".format(write_port))
self.lib.write(" pin(DIN{0}[{1}:0]){{\n".format(write_port,self.sram.word_size-1))
self.write_FF_setuphold(write_port)
self.lib.write(" }\n") # pin
self.lib.write(" }\n") #bus
@ -380,7 +380,7 @@ class lib:
self.lib.write(" direction : input; \n")
self.lib.write(" capacitance : {0}; \n".format(tech.spice["dff_in_cap"]))
self.lib.write(" max_transition : {0};\n".format(self.slews[-1]))
self.lib.write(" pin(ADDR{})".format(port))
self.lib.write(" pin(ADDR{0}[{1}:0])".format(port,self.sram.addr_size-1))
self.lib.write("{\n")
self.write_FF_setuphold(port)

6
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
View File

@ -93,7 +93,7 @@ cell (sram_2_16_1_freepdk45){
address : ADDR0;
clocked_on : clk0;
}
pin(DIN0){
pin(DIN0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -132,7 +132,7 @@ cell (sram_2_16_1_freepdk45){
memory_read(){
address : ADDR0;
}
pin(DOUT0){
pin(DOUT0[1:0]){
timing(){
timing_sense : non_unate;
related_pin : "clk0";
@ -166,7 +166,7 @@ cell (sram_2_16_1_freepdk45){
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
pin(ADDR0){
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";

6
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
View File

@ -93,7 +93,7 @@ cell (sram_2_16_1_scn4m_subm){
address : ADDR0;
clocked_on : clk0;
}
pin(DIN0){
pin(DIN0[1:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -132,7 +132,7 @@ cell (sram_2_16_1_scn4m_subm){
memory_read(){
address : ADDR0;
}
pin(DOUT0){
pin(DOUT0[1:0]){
timing(){
timing_sense : non_unate;
related_pin : "clk0";
@ -166,7 +166,7 @@ cell (sram_2_16_1_scn4m_subm){
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
pin(ADDR0){
pin(ADDR0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";