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1839 Commits

Author SHA1 Message Date
Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Hunter Nichols 5bfc42fdbb Added quality improvements to graph: improved naming, auto vdd/gnd removal 2019-04-29 23:57:25 -07:00
Matt Guthaus 534c6b36df Use correct back end config file. 2019-04-29 10:20:27 -07:00
Matt Guthaus 8d8565bd9c Add inline_drclvs option for improved coverage 2019-04-29 09:15:46 -07:00
Matt Guthaus 978ba9d2f2 Refactor run scripts. 
Run DRC, LVS, and PEX share a run_*.sh script.
 2019-04-26 15:43:46 -07:00
Matt Guthaus 946a0aca86 Simplify DRC and LVS run scripts. 
Modified run scripts to work on local only files in the temp
directory. This assumes the files and subckts are named the
same as the clel name. Script now copies library files
to the temp directory as well.
 2019-04-26 15:17:39 -07:00
Matt Guthaus 51a97979b9 Add front and back-end test 30. 2019-04-26 15:17:19 -07:00
Matt Guthaus d23aa9a1bd Use local setup.tcl and flatten bitcell arrays. 2019-04-26 14:12:51 -07:00
Matt Guthaus 9cead23f22 Add hierarchy to netgen LVS command. 2019-04-26 13:46:34 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 0439b129bb Some pgates are designs since not a fixed height 2019-04-26 12:33:53 -07:00
Matt Guthaus 05ad4285af Cleanup pgate code. 
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
 2019-04-26 12:30:42 -07:00
Jesse Cirimelli-Low e507fbd5e9 Merge branch 'datasheet_gen' into dev 2019-04-26 12:29:37 -07:00
Matt Guthaus 3ffcad0db8 Add port makeall for removing symmetry problems in netgen 2019-04-26 09:17:52 -07:00
Hunter Nichols f35385f42a Cleaned up names, added exclusions to narrow paths for analysis. 2019-04-24 23:51:09 -07:00
Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules. 2019-04-24 14:23:22 -07:00
Matt Guthaus 59d2e45744 Move characterization on/off feedback to report_status. 2019-04-24 11:30:38 -07:00
Matt Guthaus 7f5e6dd6f8 Fix unconnected supply pin bug in supply router. 
Simplified some of the supply router pin groups so that it assumes
each group is fully connected. When computing enclosures of the
pins on the routing grid, it will remove disconnected enclosure
shapes to keep things connected.
 2019-04-24 10:54:22 -07:00
Matt Guthaus 66c703d932 Simplify router code to clean it up a bit. 2019-04-22 15:30:35 -07:00
Matt Guthaus 5b828f32cb Create auxiliary run_drc.sh and run_lvs.sh with arguments for calibre 2019-04-22 15:12:59 -07:00
Hunter Nichols 4f28295e20 Added initial graph for correct naming 2019-04-19 01:27:06 -07:00
Jesse Cirimelli-Low 49e5f97eb4 fixed bug where log would fail to generate if output folder did not exist 2019-04-17 15:02:10 -07:00
Matt Guthaus 25bc3a66ed Add far left option for contact placement in pgates. 2019-04-17 13:41:35 -07:00
Matt Guthaus a35bf29bdd Improve print output for debugging layout objects. 2019-04-17 13:41:17 -07:00
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
Hunter Nichols c1411f4227 Applied quick corner estimation to analytical delay. 2019-04-09 12:26:54 -07:00
Hunter Nichols a500d7ee3d Adjusted bitcell analytical delays for multiport cells. 2019-04-09 02:49:52 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols 1438519495 Added check to pdriver for 0 fanout which can break compute_sizes. 2019-04-03 17:53:28 -07:00
Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts. 2019-04-03 16:45:01 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Matt Guthaus df4e2fead8 Return empty set instead of a list. 2019-04-01 15:59:57 -07:00
Matt Guthaus 07ecf52b9f Add giant example for front-end mode 2019-04-01 15:49:01 -07:00
Matt Guthaus 5f37677225 Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
Matt Guthaus 74f904a509 Cleanup options for front-end. Improve info output. 2019-04-01 10:35:17 -07:00
Matt Guthaus c3e074c069 Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
Hunter Nichols 97777475b4 Added additions to account for custom delay chains. 2019-03-28 17:16:23 -07:00
Hunter Nichols 50d3b4cb8d Added some bitline measures to the model_checker 2019-03-19 15:03:57 -07:00
Matt Guthaus 95d96bd45d Add OPENRAM_TMP environment check 2019-03-08 11:12:30 -08:00
Matt Guthaus 0354e2dfb7 Rename config_20 to config since it is used in all tests 2019-03-08 10:47:41 -08:00
Matt Guthaus 196710ec3e Remove factory from lef and verilog tests 2019-03-08 09:22:48 -08:00
Matt Guthaus bd256d33d6 Remove syntax error 2019-03-08 08:35:18 -08:00
Matt Guthaus 7129f79dc4 Merge remote-tracking branch 'origin' into tech_reorg 2019-03-08 08:33:46 -08:00
Matt Guthaus d8f64500e6 Remove factory create from lib tests so that we can give required name 2019-03-08 08:31:26 -08:00
Hunter Nichols e39f9ee481 Merge branch 'dev' into multiport_characterization 2019-03-07 12:31:14 -08:00
Hunter Nichols 910878ed30 Removed bitline measures until hardcoded signal names are made dynamic 2019-03-07 12:30:27 -08:00
Jesse Cirimelli-Low e6311dd44a Merge branch 'datasheet_gen' into dev 2019-03-06 23:47:19 -08:00
Jesse Cirimelli-Low 4754e6851d add_db takes commline line argv for path 2019-03-06 22:21:05 -08:00
Jesse Cirimelli-Low c1770036ac made the add_db code much simpler 2019-03-06 22:20:34 -08:00
Jesse Cirimelli-Low 83e810f8b8 added sorting to deliverables output 2019-03-06 21:12:21 -08:00
Jesse Cirimelli-Low fac9ff9be6 changed add_db.py to uncommenting method 2019-03-06 20:59:52 -08:00
Matt Guthaus 95137a2c26 Wrap debug line 2019-03-06 14:24:24 -08:00
Matt Guthaus 77229d5121 Reduce verbosity 2019-03-06 14:24:18 -08:00
Matt Guthaus c4c844a8a2 Remove duplicate module name checking since we use the factory 2019-03-06 14:14:46 -08:00
Matt Guthaus 09a429aef7 Update unit tests to all use the sram_factory 2019-03-06 14:12:24 -08:00
Matt Guthaus acf2798a18 Add link to presentation in README 2019-03-06 08:29:43 -08:00
Matt Guthaus cfc14f327e Factor default corner out of import_tech 2019-03-06 07:46:30 -08:00
Matt Guthaus d178801882 Simplify tech organization and import 2019-03-06 07:41:38 -08:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols ddeb40c9bf Added lib test which generates multiple corner models. Only does process currently. 2019-03-04 16:27:10 -08:00
Hunter Nichols 7e67b741f6 Merge branch 'dev' into multiport_characterization 2019-03-04 00:43:03 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Matt Guthaus 22deab959c Fix setup_bitcell to allow user to force override the bitcell. 2019-03-03 11:58:41 -08:00
Matt Guthaus abcb1cfa2c Correct elsif to elif 2019-02-28 09:17:24 -08:00
Matt Guthaus da6aa161de Don't autodetect the bitcell if the user overrides it 2019-02-28 09:12:32 -08:00
Matt Guthaus fb7264bae2 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2019-02-28 08:44:18 -08:00
Jesse Cirimelli-Low 3802c537e5 added add_db.py to add .db files to datasheets 2019-02-27 22:20:06 -08:00
Hunter Nichols 816669b9ca Merge branch 'dev' into multiport_characterization 2019-02-26 22:48:39 -08:00
Hunter Nichols ea51cfdbb4 Removed data collection script 2019-02-26 22:46:38 -08:00
Hunter Nichols 42bc6efb21 Added additional graphing and data collection to script 2019-02-26 20:06:35 -08:00
Matt Guthaus f865e66181 Remove git_id file 2019-02-25 16:47:38 -08:00
Matt Guthaus de977732db Only warn if not unit tests 2019-02-25 16:13:54 -08:00
Matt Guthaus 1f1426b97c Add auto-detect of custom bitcells 2019-02-25 16:10:34 -08:00
Matt Guthaus c79b97eb51 Merge remote-tracking branch 'origin/dev' into multiport 2019-02-25 15:46:39 -08:00
Matt Guthaus a4b5368302 Add total size in warning for output size. 2019-02-25 14:57:18 -08:00
Matt Guthaus 638afaeb31 Remove duplicate profile stats script 2019-02-25 10:14:02 -08:00
Matt Guthaus a18071a4ff Add warning for large memory sizes 2019-02-25 10:07:05 -08:00
Jesse Cirimelli-Low 34294443d4 updated logos and css for official colors 2019-02-25 07:46:34 -08:00
Jesse Cirimelli-Low 677588290d merging with dev now that it is passing 2019-02-25 07:05:06 -08:00
Matt Guthaus a210fdda0f Fix arguments for none verification 2019-02-24 10:49:35 -08:00
Matt Guthaus 9b785cd535 Fix error in cell width. Fix escape warning. 2019-02-24 10:48:54 -08:00
Matt Guthaus 4577d380f9 Add example 1w/1r 2019-02-24 09:57:34 -08:00
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
Matt Guthaus 6c9ae1c659 Remove temp names in DRC/LVS. Extract unique doesn't actually extract. 2019-02-24 07:26:21 -08:00
Jesse Cirimelli-Low b9525e0f9e Merge branch 'dev' into datasheet_gen 2019-02-23 15:45:51 -08:00
Matt Guthaus 4da56098e7 Merge branch 'magic_lvs_ports' into dev 2019-02-22 19:02:43 -08:00
Matt Guthaus 599e5457a0 Fix all libs to have pin indices 2019-02-22 17:40:49 -08:00
Matt Guthaus 583dc4410b Revert bus bits back into pins 2019-02-22 16:22:27 -08:00
Matt Guthaus 9459839c06 Clean up output file names for lvs. Update lvs script in magic. 2019-02-22 14:38:00 -08:00
Jesse Cirimelli-Low 8c9c910855 Merge branch 'datasheet_gen' into dev 2019-02-22 11:41:03 -08:00
Jesse Cirimelli-Low ff09254590 fixed analytical flag 2019-02-22 08:19:54 -08:00
Jesse Cirimelli-Low 0cabee060d fixed area rounding 2019-02-22 06:57:54 -08:00
Jesse Cirimelli-Low b4f1d53a1b fixed DRC datasheet error 2019-02-22 06:46:28 -08:00
Matt Guthaus d043c72277 Fix temp name error in openram.py 2019-02-21 11:16:21 -08:00
Matt Guthaus bb408d0a45 Add missing / in output path for log 2019-02-21 10:23:30 -08:00
Jennifer Eve Sowash 1249dcc34d Merge branch 'dev' into pdriver 2019-02-20 13:00:58 -08:00
Jennifer Eve Sowash 6d3a29328c Fixed a bug with corner_name in lib.py remaining static. 2019-02-20 12:59:40 -08:00
Jesse Cirimelli-Low 723ec9925f Merge branch 'datasheet_gen' into dev 2019-02-15 21:47:24 -08:00
Jesse Cirimelli-Low d533a8ae26 fixed logger typo 2019-02-15 21:45:05 -08:00
Jesse Cirimelli-Low e3ff9b53e9 fixed area not being found 2019-02-14 07:01:35 -08:00
Hunter Nichols 8c1fe253d5 Added variable fanouts to delay testing. 2019-02-13 22:24:58 -08:00
Jesse Cirimelli-Low 3f761afcbc Merge branch 'datasheet_gen' into dev 2019-02-13 17:43:31 -08:00
Matt Guthaus d4c21cd26e Remove extraneous character. 2019-02-13 17:41:33 -08:00
Matt Guthaus 2553439447 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2019-02-13 17:01:41 -08:00
Matt Guthaus c359bbf42a Fix deprecation warnings in regex by converting to raw strings. Add error if unable to find DRC errors in Magic. 2019-02-13 17:01:26 -08:00
Jesse Cirimelli-Low e890c0e188 fixed -v logging 2019-02-13 15:21:16 -08:00
Hunter Nichols 4faec52409 Allowed data collection and analysis to run independently. 2019-02-12 20:58:50 -08:00
Hunter Nichols a4bb481612 Added tracking for available data. 2019-02-12 16:28:37 -08:00
Jesse Cirimelli-Low 36d8d98b17 Merge branch 'dev' into datasheet_gen 2019-02-08 12:05:04 -08:00
Hunter Nichols 9e23e6584a Made variance plot look slightly better. 2019-02-07 15:30:47 -08:00
Hunter Nichols 5e9851c5f1 Merge branch 'dev' into multiport_characterization 2019-02-07 14:31:26 -08:00
Hunter Nichols ebf43298c0 Added mean/variance plotting 2019-02-07 14:26:48 -08:00
Matt Guthaus d9efb682dd Do not clean up if preserve temp in local_drc_check 2019-02-07 11:08:34 -08:00
Jesse Cirimelli-Low bfc20a9aa9 removes debug corners 2019-02-07 06:38:07 -08:00
Jesse Cirimelli-Low be4b7697cb Merge branch 'dev' into datasheet_gen 2019-02-07 06:35:57 -08:00
Jesse Cirimelli-Low 6cde6beafa added documetation to functions 2019-02-07 06:33:39 -08:00
Hunter Nichols d0edda93ad Added more variance analysis for the delay data 2019-02-07 02:27:22 -08:00
Jesse Cirimelli-Low e131af2cc3 power added to datasheet (finally) 2019-02-06 20:31:22 -08:00
Hunter Nichols 690055174d Fixed bug in control logic test with port configs. 2019-02-06 20:09:01 -08:00
Hunter Nichols 56e79c050b Changed test values to fix tests. 2019-02-06 15:27:29 -08:00
Hunter Nichols 01c8405d12 Fix bitline measurement delays and adjusted default delay chain for column mux srams 2019-02-06 00:46:25 -08:00
Hunter Nichols 5f01a52113 Fixed some delay model bugs. 2019-02-05 21:15:12 -08:00
Jesse Cirimelli-Low 374e7a31eb Merge branch 'dev' into datasheet_gen 2019-02-05 17:14:58 -08:00
Hunter Nichols e3d003d410 Adjusted test values to account for recent changes. 2019-02-05 00:43:16 -08:00
Hunter Nichols 543e0a1b9a Merge branch 'dev' into multiport_characterization 2019-02-04 23:54:16 -08:00
Hunter Nichols 12723adb0c Modified some testing and initial delay chain sizes. 2019-02-04 23:38:26 -08:00
Jesse Cirimelli-Low c22025839c datasheet now indicates if analytical or characterizer is used 2019-01-31 08:28:51 -08:00
Jesse Cirimelli-Low 21868e1b60 removed expanded process names from corners 2019-01-31 08:09:00 -08:00
Hunter Nichols 8d7823e4dd Added delay ratio comparisons between model and measurements 2019-01-31 00:26:27 -08:00
Jesse Cirimelli-Low 475db65d26 added units to AREA on datasheet 2019-01-30 17:49:43 -08:00
Matt Guthaus ec1fb087b5 Check membership of keys without using keys() list 2019-01-30 13:02:34 -08:00
Hunter Nichols 45fceb1f4e Added word per row to sram config with a default arguement to fix test. 2019-01-30 11:43:47 -08:00
Matt Guthaus 74fbe8fe63 Convert source and target lists to sets for faster contains check. 2019-01-30 11:15:47 -08:00
Matt Guthaus 07f4d639eb Remove non-rectangular error and just skip them. 2019-01-30 10:25:01 -08:00
Matt Guthaus 7836929db2 Use hash of tuples instead of checking rectangle in list 2019-01-30 10:03:07 -08:00
Matt Guthaus aaf028cacf Optimize hpwl runtime. Fix error in via cost when L shape. 2019-01-30 08:49:47 -08:00
Matt Guthaus 82a09be026 Move inspect into if statement for runtime 2019-01-30 08:42:25 -08:00
Hunter Nichols c10c9e4009 Refactored some code and other additional improvements. 2019-01-29 23:02:28 -08:00
Hunter Nichols 242a63accb Fixed issues introduced by pdriver additions in model unit test 2019-01-29 16:43:30 -08:00
Hunter Nichols d1218778b1 Fixed merge conflicts 2019-01-28 22:33:08 -08:00
Matt Guthaus 1bdf4dbe4f Re-enable abort on supply error. 2019-01-28 17:07:38 -08:00
Matt Guthaus 47a3dfafee Merge branch 'driver_sizing' into dev 2019-01-28 15:12:01 -08:00
Matt Guthaus f84dc3cadc Fix hspice delay golden results 2019-01-28 10:39:09 -08:00
Jesse Cirimelli-Low ed901aba5f changed datetime to date 2019-01-28 10:29:27 -08:00
Matt Guthaus d77bba3af2 Fix clock fanout to include internal FF. Update delays in golden tests. 2019-01-28 08:48:32 -08:00
Matt Guthaus 881c449c7c Fix error in offset computation for right drivers 2019-01-28 07:53:36 -08:00
Matt Guthaus c4438584fe Move jog for wl to mid-cells rather than mid-pins. 2019-01-27 12:59:02 -08:00
Matt Guthaus 18805423e3 Simplify pdriver code. 2019-01-25 17:18:12 -08:00
Matt Guthaus beceb3fb60 Fix buggy analytical delay in pdriver 2019-01-25 16:22:59 -08:00
Matt Guthaus 01ab253925 Move gdsMill license to README 2019-01-25 15:56:12 -08:00
Matt Guthaus d2864370aa Temporarily disable abort on supply error 2019-01-25 15:43:57 -08:00
Matt Guthaus 09d6a63861 Change path to wire_path for Anaconda package conflict 2019-01-25 15:07:56 -08:00
Matt Guthaus 0c3baa5172 Added some comments to the spice files. 2019-01-25 15:00:00 -08:00
Matt Guthaus 1afd4341bd Update stage effort of clk_buf_driver 2019-01-25 14:22:37 -08:00
Matt Guthaus 6f32bac1a2 Use rx of last pdriver instance after placing instances 2019-01-25 14:17:37 -08:00
Matt Guthaus 614aa54f17 Move clkbuf output lower to avoid dff outputs 2019-01-25 14:03:52 -08:00
Matt Guthaus ddf734891a Fix pdriver width error 2019-01-25 10:26:31 -08:00
Matt Guthaus 8f56953af0 Convert wordline driver to use sized pdriver 2019-01-24 10:20:23 -08:00
Hunter Nichols ee03b4ecb8 Added some data variation checking 2019-01-24 09:25:09 -08:00
Jesse Cirimelli-Low 65c5cc9fe7 added support for more corner variations 2019-01-24 07:09:51 -08:00
Matt Guthaus 091b4e4c62 Add size commments to spize. Change pdriver stage effort. 2019-01-23 17:27:15 -08:00
Hunter Nichols d527b7da62 Added delay error calculations 2019-01-23 13:19:35 -08:00
Matt Guthaus 8a85d3141a Fix polarity problem. 2019-01-23 13:08:43 -08:00
Matt Guthaus d64d262d78 Fix pdriver instantiation. Change sizes based on word_size. 2019-01-23 12:51:28 -08:00
Matt Guthaus b58fd03083 Change pbuf/pinv to pdriver in control logic. 2019-01-23 12:03:52 -08:00
Hunter Nichols 6d3884d60d Added corner data collection. 2019-01-22 16:40:46 -08:00
Jesse Cirimelli-Low ac17e71973 removed debug print statement 2019-01-22 15:47:16 -08:00
Jesse Cirimelli-Low 886dd4d313 Merge branch 'dev' into datasheet_gen 2019-01-22 15:24:44 -08:00
Jesse Cirimelli-Low 978990f4dd cleaned up debug.py edits 2019-01-22 15:24:38 -08:00
Matt Guthaus 23718b952f Check for print statements in more files since we now use print_raw 2019-01-18 10:16:55 -08:00
Matt Guthaus f5f27073be Merge remote-tracking branch 'origin/dev' into factory 2019-01-18 09:52:18 -08:00
Hunter Nichols 5885e3b635 Removed carriage returns, adjusted signal names generation for variable delay chain size. 2019-01-18 00:23:50 -08:00
Yusu Wang c20fb2a70e replace matrix to array 2019-01-17 12:01:08 -08:00
Hunter Nichols 4ced6be6bd Added data collection and some initial data 2019-01-17 09:54:34 -08:00
Hunter Nichols 5bbc43d0a0 Added data collection of wordline and s_en measurements. 2019-01-17 01:59:41 -08:00
Jesse Cirimelli-Low 9c8090d94b added debug.info to logging 2019-01-16 19:56:23 -08:00
Matt Guthaus 7a152ea13d Move sram_factory to root dir 2019-01-16 17:06:29 -08:00
Matt Guthaus 9ecfaf16ea Add the factory class 2019-01-16 17:04:28 -08:00
Matt Guthaus 91636be642 Convert all contacts to use the sram_factory 2019-01-16 16:56:06 -08:00
Matt Guthaus 5192a01f2d Convert pgates to use ptx through the factory 2019-01-16 16:30:31 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Jesse Cirimelli-Low 25b0da404f removed EOL error in comment 2019-01-16 16:08:41 -08:00
Jesse Cirimelli-Low 41b8e8665b updated datasheet descriptors 2019-01-16 15:43:08 -08:00
Jesse Cirimelli-Low 0556b86424 html datasheet no longer dependeds on sram 2019-01-16 14:52:01 -08:00
Jesse Cirimelli-Low 192c615a38 moved library page to new repo 2019-01-16 07:33:17 -08:00
Hunter Nichols cc0be510c7 Added some data scaling and error calculation in model check. 2019-01-16 00:46:24 -08:00
Jesse Cirimelli-Low 813a551691 comment parsing 1/2 complete; page gen setup complete 2019-01-15 20:48:20 -08:00
Jesse Cirimelli-Low 903cafb336 html parsing finished 2019-01-15 19:47:48 -08:00
Hunter Nichols 6152ec7ec5 Merge branch 'dev' into multiport_characterization 2019-01-15 16:33:39 -08:00
Jesse Cirimelli-Low b66c53a99a added log file to datasheet 2019-01-13 15:02:13 -08:00
Jesse Cirimelli-Low 87380a4801 complete log file generation 2019-01-13 14:34:46 -08:00
Matt Guthaus e210ef2a41 Add assert to lef and verilog unit test. Fix verilog files in golden results. 2019-01-11 16:42:50 -08:00
Matt Guthaus a7dd62b0e5 falling_edge not negative_edge 2019-01-11 15:17:27 -08:00
Matt Guthaus 20b869f8e1 Remove tabs 2019-01-11 14:16:57 -08:00
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
Matt Guthaus f0ab155172 Change dout to negative clock edge relative 2019-01-11 09:51:05 -08:00
Hunter Nichols 21663439cc Added slews measurements to the model checker. Removed unused code in bitline delay class. 2019-01-09 22:42:34 -08:00
Jesse Cirimelli-Low a25e0f6c8c Merge branch 'dev' into datasheet_gen 2019-01-09 13:48:43 -08:00
Matt Guthaus cdef5f0ecb Change kbits to bits in output 2019-01-09 16:57:12 -08:00
Matt Guthaus be9f81768d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2019-01-09 15:20:34 -08:00
Matt Guthaus 94a6cbc28b Remove extra bracket in pin blokc 2019-01-09 13:44:25 -08:00
Jesse Cirimelli-Low b0978e62f3 removed openram placeholder logo to stage for public push 2019-01-09 12:32:17 -08:00
Matt Guthaus 49d0b9d69c Remove old scn3me golden results. Remove indices from new golden results. 2019-01-09 12:04:17 -08:00
Matt Guthaus fe077a453a Change capitalization of message to be consistent 2019-01-09 12:00:14 -08:00
Matt Guthaus 7e635d02be Remove indices from pins in lib file 2019-01-09 12:00:00 -08:00
Matt Guthaus 4d0a8b9c8a Check for coverage executable and run without if not found. 2019-01-09 08:24:20 -08:00
Jesse Cirimelli-Low e9b8eab2c3 Merge branch 'dev' into datasheet_gen 2019-01-09 06:16:09 -08:00
Jesse Cirimelli-Low 8b8985dbd1 track table_gen 2019-01-09 06:15:22 -08:00
Jesse Cirimelli-Low 3f8628fa94 flask totally purged, fixed table headers 2019-01-08 20:04:30 -08:00
Jesse Cirimelli-Low e58515b89b tables stable and flask removed, headers are bugged 2019-01-08 19:50:47 -08:00
Jesse Cirimelli-Low 6033cc604d stable, but incomplete flaskless table gen rewrite 2019-01-08 18:54:20 -08:00
Jesse Cirimelli-Low 19a986c35c no-flask rewrite for initial datasheet case complete 2019-01-07 19:43:57 -08:00
Jesse Cirimelli-Low 24161a1df2 Merge branch 'dev' into datasheet_gen 2019-01-07 18:18:46 -08:00
Jesse Cirimelli-Low 1283cbc3be fixed EOL error in descriptor 2019-01-07 18:17:38 -08:00
Jesse Cirimelli-Low 5508ae945d updated file html description to simplify parsing 2019-01-07 17:08:47 -08:00
Matt Guthaus 2236ca40df Make xa least priority since it fails functional tests. 2019-01-03 19:20:31 -08:00
Jesse Cirimelli-Low 6acc8c8902 removed print debug statement 2019-01-03 13:41:25 -08:00
Jesse Cirimelli-Low 53b7e46db4 fixed bug where retrieving git id would fail depending on cwd 2019-01-03 12:28:29 -08:00
Hunter Nichols 272267358f Moved all bitline delay measurements to delay class. Added measurements to check delay model. 2019-01-03 05:51:28 -08:00
Jesse Cirimelli-Low c69e5fdb18 added compile time to datasheet 2019-01-02 10:30:03 -08:00
Jesse Cirimelli-Low cc27736a45 moved DRC and LVS error reports to datasheet.info from datasheet.py 2019-01-02 10:14:45 -08:00
Hunter Nichols 66b2fcdc91 Added data parsing to measurement objects and adding power measurements. 2018-12-20 15:54:56 -08:00
Hunter Nichols b10ef3fb7e Replaced delay measure statement with object implementation. 2018-12-19 18:33:06 -08:00
Hunter Nichols 8eb4812e16 Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model. 2018-12-17 23:32:02 -08:00
Hunter Nichols 51b1bd46da Added option to use delay chain size defined in tech.py 2018-12-14 18:02:19 -08:00
Hunter Nichols dc20bf9e11 Added bitline measurements to ngspice delay test. 2018-12-13 22:31:08 -08:00
Hunter Nichols e4065929c2 Added bitline threshold delay checks to delay tests. 2018-12-13 22:21:30 -08:00
Jennifer Eve Sowash 4a5c18b6cc Removed line to skip pdriver_test 2018-12-13 19:10:38 -08:00
Jennifer Eve Sowash bc44c80d40 Added height to init in pdriver.py 2018-12-13 19:03:31 -08:00
Hunter Nichols 97fc37aec1 Added checks for the bitline voltage at sense amp enable 50%. 2018-12-12 23:59:32 -08:00
Hunter Nichols 0510aeb3ec Merged with dev, removed commented out code. 2018-12-12 16:02:16 -08:00
Hunter Nichols 50f13eabce Added better port selection to bitline measurements. 2018-12-12 15:59:20 -08:00
Hunter Nichols 0a26e40022 Attempts to fix failing tests. Random seed differences between mada and pipeline. 2018-12-12 13:12:26 -08:00
Hunter Nichols 6ac474d642 Added bitline measures with hardcoded names. 2018-12-12 00:43:08 -08:00
Hunter Nichols 82e074ebf0 Added initial structure for bitline measurements. 2018-12-11 14:06:11 -08:00
Jennifer Eve Sowash a51aacfa90 Added corner case for 1 inv pos polarity and renamed variables. 2018-12-07 19:42:11 -08:00
Matt Guthaus 37c10a2198 Merge branch 'supply_routing' into dev 2018-12-07 17:04:37 -08:00
Matt Guthaus b15584a821 Print start time after banner and init 2018-12-07 15:50:18 -08:00
Hunter Nichols 4d84731c34 Edited heuristic delay chain and delay model to account for read port differences. 2018-12-07 15:39:53 -08:00
Matt Guthaus 3f468b1c18 Only print_time when not a unit test or debug_level set 2018-12-07 15:14:28 -08:00
Jennifer Eve Sowash d302f1cd0a Merge branch 'pdriver' into dev 2018-12-07 14:37:25 -08:00
Matt Guthaus 5248482fab Merge branch 'dev' into supply_routing 2018-12-07 14:28:49 -08:00
Matt Guthaus 6f171ad147 Added router timing code. Commented combine adjacent pins due to run-time complexity 2018-12-07 13:54:18 -08:00
Matt Guthaus 5ed9904855 Cast dict_values to a list for pin_groups 2018-12-07 13:02:50 -08:00
Jennifer Eve Sowash a6eec10f41 Passed freepdk45 tests with pdriver.py 2018-12-07 12:58:05 -08:00
Matt Guthaus dfb2cf3cbd Change analyze_pins to a heuristic algorithm less than O(n^2) 2018-12-07 12:41:32 -08:00
Jennifer Eve Sowash a24e5229cb Fixed method of determining inverter number. 2018-12-07 10:19:18 -08:00
Matt Guthaus a96f492d0a Add profile scripts 2018-12-07 08:56:40 -08:00
Jesse Cirimelli-Low 3d9203a7ea Merge branch 'dev' into datasheet_gen 2018-12-07 04:29:07 -08:00
Matt Guthaus 5319107afa Skip pdriver test until LVS fix 2018-12-07 07:41:35 -08:00
Matt Guthaus d38d5a6d58 Merge branch 'supply_routing' into dev 2018-12-07 07:39:53 -08:00
Jennifer Eve Sowash 653ab3eda4 Changed method of determining number of inverters. 2018-12-06 19:34:19 -08:00
Jennifer Eve Sowash 8ea85e3e65 Merge branch 'dev' into pdriver 2018-12-06 14:38:08 -08:00
Jennifer Eve Sowash 5e19cf1e24 Updated naming, added compute_sizes(), and fixed sizing function. 2018-12-06 14:36:01 -08:00
Matt Guthaus 537e0689fb Add combine adjacent pins back 2018-12-06 14:29:06 -08:00
Matt Guthaus c51752d245 Provide more stats in -v output 2018-12-06 14:11:15 -08:00
Matt Guthaus 514f6fda27 Increase size for warning of column mux limit 2018-12-06 13:57:38 -08:00
Matt Guthaus 3f1fbc3d90 Merge remote-tracking branch 'origin' into supply_routing 2018-12-06 13:53:51 -08:00
Matt Guthaus c0295a2c3d Rewrite if/else to be correct and more legible. 2018-12-06 13:23:39 -08:00
Matt Guthaus 46d3068821 Output number of words per row before SRAM creation. Recompute words per row in unit tests. 2018-12-06 13:11:47 -08:00
Matt Guthaus 6f1af4d0c9 Remove extraneous m2m3 via that causes DRC 2018-12-06 12:45:45 -08:00
Matt Guthaus b5a7274316 Change Netlisting to submodules to reflect what time is of 2018-12-06 11:59:20 -08:00
Matt Guthaus e4c67875d2 Add non-minimum width metal2 in route when vias can be close 2018-12-06 11:58:57 -08:00
Matt Guthaus b7bbc9b994 Add output on number of ports. 2018-12-06 11:58:34 -08:00
Matt Guthaus b72382b400 Fix offset bug with negative vertical supply rails 2018-12-06 11:58:19 -08:00
Jesse Cirimelli-Low afb32ed834 removed outdated 'unknown' for analytical frequency 2018-12-06 10:29:48 -08:00
Jesse Cirimelli-Low bf27eb8cd6 removed placeholder data 2018-12-06 10:17:12 -08:00
Jesse Cirimelli-Low 1633ae0265 base64 encode images for portability 2018-12-06 10:13:28 -08:00
Jesse Cirimelli-Low 02b4b13cc4 fixed config file path 2018-12-06 09:26:38 -08:00
Jesse Cirimelli-Low e41b90449d specify config file abs path 2018-12-06 05:34:05 -08:00
Hunter Nichols b157fc58a1 Moved feasible period search from functional.py to tests. 2018-12-05 23:23:40 -08:00
Hunter Nichols 1e87a0efd2 Re-added new width 1rw,1r bitcells with flattened gds. 2018-12-05 20:43:10 -08:00
Hunter Nichols 448e8f4cfd Merged with dev 2018-12-05 17:49:42 -08:00
Jesse Cirimelli-Low cd0e763895 moved system call to datasheet.info generator 2018-12-05 17:35:35 -08:00
Matt Guthaus 7645a909eb Merge branch 'supply_routing' into dev 2018-12-05 17:24:51 -08:00
Hunter Nichols ea55bda493 Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
Jesse Cirimelli-Low 1dae539e1d track git_id 2018-12-05 16:13:52 -08:00
Jesse Cirimelli-Low 7e475b376e switch to git rev-parse solution for id parsing 2018-12-05 14:58:37 -08:00
Jesse Cirimelli-Low 32bd91aafd track ORIG_HEAD file 2018-12-05 13:39:54 -08:00
Jesse Cirimelli-Low 7a20420030 get ORIG_HEAD with pre-commit hook 2018-12-05 13:38:09 -08:00
Matt Guthaus 2cd1322071 Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
Matt Guthaus fa3bf2915a Remove commented code 2018-12-05 09:56:19 -08:00
Matt Guthaus 0c0a23e6eb Cleanup code. Add time breakdown for SRAM creation. 2018-12-05 09:51:17 -08:00
Hunter Nichols 0c3c58011b Fixed delay test values. 2018-12-05 00:13:23 -08:00
Matt Guthaus f1c74d6bfb Merge branch 'dev' into supply_routing 2018-12-04 17:57:18 -08:00
Matt Guthaus d95b34caf2 Round output to look pretty 2018-12-04 17:08:47 -08:00
Matt Guthaus e750d446dc Fix syntax error. Enable skipped test. 2018-12-04 17:08:22 -08:00
Matt Guthaus 126d4a8d10 Fix instersection bug. Improve primary and secondary pin algo. 2018-12-04 16:53:04 -08:00
Jesse Cirimelli-Low b6e7ddd023 Merge branch 'dev' into datasheet_gen 2018-12-04 16:27:04 -08:00
Matt Guthaus 7ce75398a8 Change warning to info 2018-12-04 09:42:47 -08:00
Matt Guthaus 7fce6f06ca Expand grids to maximal pin before removing blockages 2018-12-04 09:35:40 -08:00
Matt Guthaus 389bb91af4 Simplifying supply router to single grid track 2018-12-04 08:41:57 -08:00
Matt Guthaus 2a68b57215 Changed psram info to sram 2018-12-03 15:59:31 -08:00
Jesse Cirimelli-Low 2c12ef2161 added warning to test 30 coverage is not installed 2018-12-03 13:24:22 -08:00
Jennifer Eve Sowash 2534a32e20 pdriver.py passes resgression tests. Size and number of inverters has been added. 2018-12-03 12:55:48 -08:00
Jesse Cirimelli-Low 71bb1bb9f1 updated test 30 to dev version 2018-12-03 11:09:45 -08:00
Matt Guthaus c6f03e70d4 Convert supply to wider DRC rules 2018-12-03 11:09:17 -08:00
Jesse Cirimelli-Low c869c7e870 added tracking to new debug files 2018-12-03 10:54:50 -08:00
Jesse Cirimelli-Low 5646660765 added git id to datasheet 2018-12-03 10:53:50 -08:00
Jesse Cirimelli-Low 9501b99df7 merged branch wtih dev 2018-12-03 09:47:34 -08:00
Jennifer Eve Sowash da631618b6 Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver 2018-12-03 09:14:13 -08:00
Matt Guthaus bcc6b95564 Add coverage exclusions. Add subprocess coverage. 2018-12-03 09:13:57 -08:00
Jennifer Sowash 887674aa85 Added pdriver.py for testing. 2018-12-03 09:11:12 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 49f7022416 Skip failing tests with comments for bugs. 2018-11-30 12:33:43 -08:00
Matt Guthaus 90d1fa7c43 Bitcell supply routing fixes. 
Flatten and simplify 1rw 1r bitcell.
Move bitcell vias to M3 if rotation is limited.
Simplify replica bitcell vdd routing.
 2018-11-30 12:32:13 -08:00
Matt Guthaus 7e054a51e2 Some techs don't need m1 power pins 2018-11-29 18:47:38 -08:00
Matt Guthaus 0af4263edb Remove extra rotated vias in bitcell array to simplify power routing 2018-11-29 18:13:15 -08:00
Matt Guthaus 0e7301fff8 Update unit test golden results. Skip two tests. 2018-11-29 17:28:57 -08:00
Matt Guthaus e98f7075e2 Merge branch 'multiport_control_fix' of ssh://scone/home/mrg/openram into multiport_control_fix 2018-11-29 16:29:17 -08:00
Matt Guthaus 33a7683473 Remove used gated_clk instead of cs for read-only control logic. 2018-11-29 16:28:37 -08:00
Matt Guthaus a7be60529f Do not rotate vias in horizontal channel routes 2018-11-29 13:57:40 -08:00
Matt Guthaus 3c4d559308 Fixed syntax error referring to column mux 2018-11-29 13:29:16 -08:00
Matt Guthaus 3d3f54aa86 Add col addr line spacing for col addr decoder 2018-11-29 13:22:48 -08:00
Matt Guthaus 4df862d8af Convert channel router to take netlist of pins rather than names. 2018-11-29 12:12:10 -08:00
Matt Guthaus a7bc9e0de0 Use module height not instance uy for sram placement 2018-11-29 10:34:25 -08:00
Matt Guthaus 0a16d83181 Add more layout and functional port tests. 2018-11-29 10:28:43 -08:00
Matt Guthaus 14fa33e21d Remove 4 bank code and test for now. 2018-11-29 10:28:09 -08:00
Matt Guthaus 7054d0881a Fix col address dff spacing from bank. 2018-11-29 09:54:29 -08:00
Matt Guthaus 02a67f9867 Missing gap in port 1 col decoder 2018-11-28 18:07:31 -08:00
Matt Guthaus d041a498f3 Fix height of port 1 control bus. Adjust column decoder names. 2018-11-28 17:48:25 -08:00
Jesse Cirimelli-Low a4b1d2f13b added css style code 2018-11-28 17:21:50 -08:00
Jesse Cirimelli-Low 06805d1e70 file browser does not show files in root directory; removed test file 2018-11-28 17:18:59 -08:00
Matt Guthaus f8513da162 Remove local temp dir 2018-11-28 17:04:53 -08:00
Matt Guthaus a2a9cea37e Make column decoder same height as control to control and supply overlaps 2018-11-28 16:59:58 -08:00
Jesse Cirimelli-Low 79c4b3c4cd added files links 2018-11-28 16:56:24 -08:00
Matt Guthaus 3cfe74cefb Functional simulation uses threshold for high and low noise margins 2018-11-28 16:55:04 -08:00
Jesse Cirimelli-Low 44638cb885 jinja2 file browser working 2018-11-28 16:48:24 -08:00
Matt Guthaus 25ae3a5eae Fix error of no control bus width 2018-11-28 15:42:51 -08:00
Matt Guthaus d99dcd33e2 Fix SRAM level control routing errors. 2018-11-28 15:30:52 -08:00
Matt Guthaus 143e4ed7f9 Change hierchical decoder output order to match changes to netlist. 2018-11-28 14:09:45 -08:00
Matt Guthaus b5b691b73d Fix missing via in clk input of control 2018-11-28 13:20:39 -08:00
Matt Guthaus 2ed8fc1506 pgate inputs and outputs are all on M1 for flexible via placement when using gates. 2018-11-28 12:42:29 -08:00
Matt Guthaus 93904d9f2d Control logic passes DRC/LVS in SCMOS 2018-11-28 11:02:24 -08:00
Matt Guthaus 410115e830 Modify dff_buf to stagger Q and Qb outputs. 2018-11-28 10:43:11 -08:00
Matt Guthaus 25611fcbc1 Remove dff_inv since we can just use dff_buf 2018-11-28 10:42:22 -08:00
Matt Guthaus ea6abfadb7 Stagger outputs of dff_buf 2018-11-28 09:48:16 -08:00
Matt Guthaus d2ca2efdbe Limit ps, pd, as, ad precision in ptx. 2018-11-28 09:47:54 -08:00
Jesse Cirimelli-Low a56e3f609b removed debug print statements 2018-11-28 09:39:58 -08:00
Jesse Cirimelli-Low 0920321a2e start of static html generation code 2018-11-27 19:49:05 -08:00
Matt Guthaus c43a140b5e All control routed and DRC clean. LVS errors. 2018-11-27 17:18:03 -08:00
Matt Guthaus 5d59863efc Fix p_en_bar at top level. Change default scn4m period to 10ns. 2018-11-27 14:44:55 -08:00
Matt Guthaus c45f990413 Change en to en_bar in precharge. Fix logic for inverted p_en_bar. 2018-11-27 14:17:55 -08:00
Matt Guthaus 0c286d6c29 Revert to 5V example until we fix spice models in scn4m_subm 2018-11-27 14:17:06 -08:00
Jesse Cirimelli-Low 5aa8c46c16 Merge branch 'dev' into datasheet_gen 2018-11-27 13:54:21 -08:00
Matt Guthaus bf31126679 Correct decoder output numbers to follow address order 2018-11-27 12:03:13 -08:00
Matt Guthaus b912f289a6 Remove extra X in instance names 2018-11-27 12:02:53 -08:00
Matt Guthaus 2237af0463 Merge branch 'multiport_control_fix' of ssh://scone/home/mrg/openram into multiport_control_fix 2018-11-26 18:01:34 -08:00
Matt Guthaus cf23eacd0e Add wl_en 2018-11-26 18:00:59 -08:00
Matt Guthaus 21759d59b4 Remove inverter in wordline driver 2018-11-26 16:41:31 -08:00
Matt Guthaus 9e0b31d685 Make pand2 and pbuf derive pgate. Initial DRC wrong layout. 2018-11-26 16:19:18 -08:00
Matt Guthaus dd79fc560b Corretct modules for add_inst 2018-11-26 15:35:29 -08:00
Matt Guthaus b440031855 Add netlist only mode to new pgates 2018-11-26 15:29:42 -08:00
Matt Guthaus 2eff166527 Rotate vias in pand2 2018-11-26 14:05:04 -08:00
Matt Guthaus 5209619987 Move pnand2 output to allow input pin access on M2 2018-11-26 13:59:53 -08:00
Matt Guthaus 8fba32ca12 Add pand2 draft 2018-11-26 13:45:22 -08:00
Jennifer Eve Sowash 524334d24d Merge branch 'dev' into pdriver 2018-11-26 13:15:47 -08:00
Hunter Nichols b06aa84824 Functional tests now find a feasible period instead of using a heuristic. Bug found, trimming pbitcell netlists causes bit flips. 2018-11-23 18:55:15 -08:00
Hunter Nichols 5f954689a5 In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes. 2018-11-23 13:19:55 -08:00
Jennifer Eve Sowash bb7773ca7f Editted pbuf.py to pass regression. 2018-11-20 14:39:11 -08:00
Jesse Cirimelli-Low 29f19ad70f replaced absolute links with relative links 2018-11-20 12:27:54 -08:00
Jesse Cirimelli-Low 7d070c2652 Added links to logos 2018-11-20 11:51:38 -08:00
Hunter Nichols 67977bab3e Fixed port issue in bank. Changed golden data due to netlist change. 2018-11-20 11:39:14 -08:00
Jesse Cirimelli-Low 1942ef33ac Merge branch 'dev' into datasheet_gen 2018-11-20 11:23:42 -08:00
Hunter Nichols 62cbbca852 Merged, fixed conflict bt matching control logic creation to dev. 2018-11-19 22:20:20 -08:00
Hunter Nichols 2f29ad5510 Disabled resizing based on rise/fall delays. It creates delay chains which cannot be routed. 2018-11-19 22:13:58 -08:00
Matt Guthaus b8299565eb Use grid furthest from blockages when blocked pin. Enclose multiple connectors. 2018-11-19 17:32:55 -08:00
Hunter Nichols 8257e4fe8c Changed syntax in replica_bl tests, golden data to fit new values in delay tests. 2018-11-19 16:51:43 -08:00
Matt Guthaus 20d4e390f6 Add bounding box of connector for when there are multiple connectors 2018-11-19 15:45:07 -08:00
Matt Guthaus 2694ee1a4c Add all insufficient grids that overlap the pin at all 2018-11-19 15:43:19 -08:00
Hunter Nichols e8f1c19af6 Merge branch 'dev' into multiport_characterization 2018-11-19 15:42:48 -08:00
Matt Guthaus a47509de26 Move via away from cell edges 2018-11-19 15:42:22 -08:00
Hunter Nichols a55d907d03 High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME 2018-11-19 15:40:26 -08:00
Matt Guthaus 6a7d721562 Add new bbox routine for pin enclosures 2018-11-19 09:28:29 -08:00
Matt Guthaus 4630f52de2 Use array ur instead of bank ur to pace row addr dff 2018-11-19 08:41:26 -08:00
Hunter Nichols d3c47ac976 Made delay measurements less dependent on period. 2018-11-18 23:28:49 -08:00
Matt Guthaus 7709d5caa7 Move row addr dffs to top of bank to prevent addr route problems 2018-11-18 10:02:08 -08:00
Matt Guthaus ba8bec3f67 Two m1 pitches at top of control logic 2018-11-18 09:30:27 -08:00
Matt Guthaus c677efa217 Fix control logic center location. Fix rail height error in write only control logic. 2018-11-18 09:15:03 -08:00
Hunter Nichols 3716030a23 Added delay chain sizing for rise/fall delays. Disabled to some sizes being having very large fanouts. 2018-11-16 16:57:22 -08:00
Matt Guthaus 047d6ca2ef Must channel rout the column mux bits since they could overlap 2018-11-16 16:21:31 -08:00
Matt Guthaus b89c011e41 Add psram 1w/1r test. Fix bl/br port naming errors in bank. 2018-11-16 15:31:22 -08:00
Matt Guthaus 8f28f4fde5 Don't always add all 3 types of contorl. Add write and read only port lists. 2018-11-16 15:03:12 -08:00
Matt Guthaus b13d938ea8 Add m3m4 short hand in design class 2018-11-16 14:10:49 -08:00
Matt Guthaus 4997a20511 Must set library cell flag for netlist only mode as well 2018-11-16 13:37:17 -08:00
Matt Guthaus ca750b698a Uniquify bitcell array 2018-11-16 12:52:22 -08:00
Matt Guthaus e040fd12f9 Bitcell and bitcell array can be named the same. 2018-11-16 12:00:23 -08:00
Matt Guthaus 5e0eb609da Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names. 2018-11-16 11:48:41 -08:00
Matt Guthaus 68ac7e5955 Fix offset of column decoder with new mirroring 2018-11-15 17:27:58 -08:00
Matt Guthaus 712b71c5ca Mirror port 1 column decoder in X and Y 2018-11-15 15:26:59 -08:00
Jennifer Eve Sowash c73004de35 Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver 2018-11-15 14:06:38 -08:00
Jesse Cirimelli-Low 59c0421804 merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py 2018-11-15 10:45:33 -08:00
Matt Guthaus 21d111acfe Move wordline driver clock line below decoder. Fix port 1 clock route DRC. 2018-11-15 10:30:38 -08:00
Hunter Nichols 6e47de3f9b Separated relative delay into rise/fall. 2018-11-14 23:34:53 -08:00
Matt Guthaus 66982a9283 Only add second port if it is specified. 2018-11-14 17:11:23 -08:00
Matt Guthaus 2fd86958a8 Merge branch 'multiport_layout' of ssh://scone/home/mrg/openram into multiport_layout 2018-11-14 17:07:01 -08:00
Matt Guthaus 3cfefa784f Fix run-time bug in combine adjacent pins for supply router 2018-11-14 17:06:12 -08:00
Matt Guthaus 3221d3e744 Add initial support and unit tests for 2 port SRAM 2018-11-14 17:05:23 -08:00