luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Use local setup.tcl and flatten bitcell arrays.

This commit is contained in:
Matt Guthaus 2019-04-26 14:12:51 -07:00
parent 9cead23f22
commit d23aa9a1bd
2 changed files with 6 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
compiler/verify/magic.py
View File

@ -97,10 +97,11 @@ def write_netgen_script(cell_name, sp_name):
global OPTS
setup_file = OPTS.openram_tech + "mag_lib/setup.tcl"
if os.path.exists(setup_file):
setup_file = "setup.tcl"
full_setup_file = OPTS.openram_tech + "mag_lib/" + setup_file
if os.path.exists(full_setup_file):
# Copy setup.tcl file into temp dir
shutil.copy(setup_file, OPTS.openram_temp)
shutil.copy(full_setup_file, OPTS.openram_temp)
else:
setup_file = 'nosetup'

4
technology/scn4m_subm/mag_lib/setup.tcl
View File

@ -4,8 +4,8 @@ equate class {-circuit1 nfet} {-circuit2 n}
equate class {-circuit1 pfet} {-circuit2 p}
# This circuit has symmetries and needs to be flattened to resolve them
# or the banks won't pass
#flatten class {-circuit1 bitcell_array_0}
#flatten class {-circuit1 bitcell_array_1}
flatten class {-circuit1 bitcell_array_0}
flatten class {-circuit1 bitcell_array_1}
#flatten class {-circuit1 precharge_array_0}
#flatten class {-circuit1 precharge_array_1}
#flatten class {-circuit1 precharge_array_2}