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1839 Commits

Author SHA1 Message Date
mrg bea07c2319 SRAM with RBL integration in array. 2019-07-16 09:04:58 -07:00
mrg 37c15937e2 Add multiple control logic port types. 2019-07-15 17:07:50 -07:00
jsowash 021d604832 Removed wmask from addwrite() 2019-07-15 16:48:36 -07:00
jsowash ab27c70279 Merge branch 'dev' into add_wmask 2019-07-15 14:42:23 -07:00
jsowash ea2f786dcf Redefined write_size inrecompute_sizes() to take the new word_size() 2019-07-15 14:41:26 -07:00
mrg e550d6ff10 Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
mrg 2271946eef Fix replica array pin names 2019-07-12 14:39:56 -07:00
mrg 8815ddf7f1 Remove unnecessary feasible period search. 2019-07-12 11:55:42 -07:00
mrg 9092fa4ee6 Remove multiport control logic test since it doesn't have a bitcell anymore. 2019-07-12 11:18:47 -07:00
mrg d72691f6c2 Make mirror optional argument 2019-07-12 11:14:47 -07:00
mrg a189b325ed Merge remote-tracking branch 'origin/dev' into rbl_revamp 2019-07-12 11:10:07 -07:00
mrg 80145c0a92 Only enable pdb post-mortem when not purging temp for debug. 2019-07-12 10:57:59 -07:00
mrg 17d144b5b5 Clean up multiport test options to be consistent. 2019-07-12 10:39:55 -07:00
jsowash dfa2b29b8f Begin adding wmask netlist and spice tests. 2019-07-12 10:34:29 -07:00
mrg aa552f8e96 Remove debug trace 2019-07-12 10:17:33 -07:00
mrg 043018e8ba Functional tests working with new RBL. 2019-07-12 08:42:36 -07:00
mrg 0b13225913 Single banks working with new RBL 2019-07-11 14:47:27 -07:00
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
Bin Wu c9c839ca46 fix the delay measure bug in pex tests 2019-07-10 04:39:40 -07:00
Bin Wu e4070ddad8 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2 2019-07-10 03:09:12 -07:00
jsowash 5258016c9f Changed location of port for din_reg. 2019-07-06 12:27:24 -07:00
jsowash 6fe78fe04a Removed begin end for Verilog without wmask. 2019-07-06 11:29:34 -07:00
jsowash 24bfaa3b76 Added write_size to test 16 and added a newline to Verilog with no wmask for test 25. 2019-07-05 15:55:03 -07:00
jsowash ad9193ad5a Verified 1rw mask writing and changed verilog.py accordingly. 2019-07-05 15:08:59 -07:00
mrg 9dab0be737 Single bank working with replica array. 2019-07-05 13:44:29 -07:00
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
jsowash f29631695c Finished merge 2019-07-05 11:43:31 -07:00
jsowash 150259e2ba Added write_size to control_logic_r parameters. 2019-07-05 11:40:02 -07:00
mrg f542613d78 Correct wordline_driver enable to en, not en_bar. 2019-07-05 10:31:05 -07:00
mrg bfe4213fce Port address added to entire SRAM. 2019-07-05 09:44:42 -07:00
mrg 4c6556f1bc Add port address module 2019-07-05 09:04:48 -07:00
mrg c0f9cdbc12 Create port address module 2019-07-05 09:03:52 -07:00
mrg dd62269e0b Some cleanup 2019-07-05 08:18:58 -07:00
jsowash 02a0cd71ac fixed merge conflict 2019-07-04 11:14:32 -07:00
jsowash 125112b562 Added wmask flip flop. Need work on placement still. 2019-07-04 10:34:14 -07:00
mrg 3176ae9d50 Fix pnand2 height in bank select. Unsure how it passed before. 2019-07-03 15:12:22 -07:00
Matt Guthaus f914ab0ece Re-enable replica tests 2019-07-03 14:57:47 -07:00
Matt Guthaus 0cb86b8ba2 Exclude new precharge in graph build 2019-07-03 14:46:20 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
mrg 70c83f20b6 Fixes to pass unit tests. 
Skip replica tests until freepdk45 cells are made.
Revert to previous control and row addr dff placement.
 2019-07-03 13:37:56 -07:00
mrg bc4a3ee2b7 New port_data module works in SCMOS 2019-07-03 13:17:12 -07:00
jsowash 474ac67af5 Added optional write_size and wmask. 2019-07-03 10:14:15 -07:00
mrg 244604fb0d Data port module working by itself. 2019-07-02 15:35:53 -07:00
mrg 2abe859df1 Fix shared bank offset. 2019-07-01 16:29:59 -07:00
jsowash 67c6cdf3bb Fixed error where word_size was compared to num_words and added write_size to control_logic.py 2019-07-01 15:51:40 -07:00
Bin Wu 9ce968b446 megre with dev changes 2019-06-30 00:50:18 -07:00
Bin Wu 1fcb20f846 clean pex test based on feedback 2019-06-30 00:16:04 -07:00
jsowash 242771f710 Merge branch 'dev' into add_wmask 2019-06-28 15:44:27 -07:00
jsowash 1f76afd294 Begin wmask functionality. Added wmask to verilog file and config parameters. 2019-06-28 15:43:09 -07:00
Hunter Nichols 3f5b60856a Fixed key error with analytical delay of write ports. 2019-06-28 13:49:04 -07:00
Hunter Nichols ce7e320505 Undid change to add bitcell as input to array mod. 2019-06-25 18:26:13 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 4f3340e973 Cleaned up graph additions to characterizer. 2019-06-25 16:37:35 -07:00
Hunter Nichols 33c17ac41c Moved manual delay chain declarations from tech files to options. 2019-06-25 15:45:02 -07:00
Bin Wu 8e5fa7c7ae fix the run_pex function for calibre 2019-06-25 15:06:07 -07:00
Hunter Nichols 04ce3d5f45 Split control logic into different tests to avoid factory errors. 2019-06-25 14:55:28 -07:00
Bin Wu 9ef2616d41 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into pex_fix_v2 2019-06-25 11:28:04 -07:00
Bin Wu 3f3ee9b885 add pex function for magic and openram test 2019-06-25 11:24:25 -07:00
jsowash 3bd69d2759 Added functionality to express polygons in LEF files. 2019-06-25 09:20:00 -07:00
Bin Wu 91febec3a2 add hspice and ngspice pex tests 2019-06-25 09:19:37 -07:00
Matt d22d7de195 Reapply jsowash update without spice model file 2019-06-24 08:59:58 -07:00
mrg 4523a7b9f6 Replica bitcell array working 2019-06-19 16:03:21 -07:00
Hunter Nichols 2b07db33c8 Added bitcell as input to array, but there are DRC errors now. 2019-06-17 15:31:16 -07:00
mrg 5c4df2410e Fix dummy row LVS issue 2019-06-14 15:06:04 -07:00
mrg d35f180609 Add dummy row 2019-06-14 15:05:14 -07:00
mrg 3c3456596a Add replica row with dummy cells. 2019-06-14 14:38:55 -07:00
mrg b67f06a65a Add replica column for inclusion in replica bitcell array 2019-06-14 12:15:16 -07:00
mrg d8baa5384d Remove useless comments. Add missing copyright. 2019-06-14 10:13:13 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg 8418aea95a Revert height to width 2019-06-03 15:36:14 -07:00
mrg 58f51b72f1 Merge fixes 2019-06-03 15:31:49 -07:00
mrg 7b8c2cac30 Starting single layer power router. 2019-06-03 15:28:55 -07:00
mrg bd4d965e37 Begin single layer supply router 2019-06-03 15:27:37 -07:00
mrg 4612c9c182 Move power pins before no route option 2019-06-03 15:27:37 -07:00
mrg fc12ea24e9 Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
mrg 1268a7927b Pbitcell updates. 
Fix module offset error.
Add boundary for debugging.
Line wrap code.
 2019-06-03 15:27:37 -07:00
Matt Guthaus 7cca6b4f69 Add back scn3me_subm support 
Add back scn3me_subm tech files
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-06-03 15:27:37 -07:00
mrg 301f032619 Remove +1 to induce error. 2019-05-31 10:55:17 -07:00
mrg d789f93743 Add debug runner during individual tests. 2019-05-31 10:51:42 -07:00
mrg bf86969972 Create sram subdirectory. 2019-05-31 08:56:24 -07:00
Hunter Nichols 36214792eb Removed some debug measurements that were causing failures. 2019-05-28 17:04:27 -07:00
Hunter Nichols ad229b1504 Altered indexing of objects in SRAM factory to remove duplications of items using OPTS names. Added smarter bitline name checking. 2019-05-28 16:55:09 -07:00
mrg 72f4a223c3 Move power pins before no route option 2019-05-27 16:38:47 -07:00
mrg c2cc901300 Add boundary to every module and pgate for visual debug. 2019-05-27 16:32:38 -07:00
mrg e738353b5c Pbitcell updates. 
Fix module offset error.
Add boundary for debugging.
Line wrap code.
 2019-05-27 16:19:29 -07:00
Hunter Nichols e2d1f7ab0a Added smarter name checking for the characterizer. 2019-05-27 13:08:59 -07:00
mrg 26146b6838 Fix SCN3ME_SUBM stuff. 
Update cells to be DRC clean with rule 5.5.b
Allow magic for FreePDK45 but not debugged.
Revert to older Magic tech file for SCN3ME_SUBM
 2019-05-26 22:28:16 -07:00
Hunter Nichols d08181455c Added multiport bitcell support for storage node checks 2019-05-20 22:50:03 -07:00
Hunter Nichols 099bc4e258 Added bitcell check to storage nodes. 2019-05-20 18:35:52 -07:00
Hunter Nichols 412f9bb463 Added additional check to bitline to reduce false positives. 2019-05-17 01:56:22 -07:00
Hunter Nichols 03a762d311 Replaced constant string comparisons with enums 2019-05-16 14:18:33 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Hunter Nichols a80698918b Fixed test issues, removed all bitcells not relevant for timing graph. 2019-05-15 17:17:26 -07:00
Hunter Nichols 178d3df5f5 Added graph to characterizer to get net names and perform s_en checks. Graph not working with column mux. 2019-05-14 14:44:49 -07:00
Hunter Nichols b30c20ffb5 Added graph creation to characterizer, re-arranged pin creation. 2019-05-14 01:15:50 -07:00
Hunter Nichols b4cce65889 Added incorrect read checking in characterizer. 2019-05-13 19:38:46 -07:00
mrg 3fa8c5543a Merge branch 'dev' into scn3me_subm 2019-05-08 17:52:38 -07:00
mrg a5ed9b56cd Optional m4 in design class 2019-05-08 17:51:38 -07:00
Matt Guthaus c24879162a Add back scn3me_subm tech files 2019-05-08 16:06:21 -07:00
Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Hunter Nichols 5bfc42fdbb Added quality improvements to graph: improved naming, auto vdd/gnd removal 2019-04-29 23:57:25 -07:00
Matt Guthaus 534c6b36df Use correct back end config file. 2019-04-29 10:20:27 -07:00
Matt Guthaus 8d8565bd9c Add inline_drclvs option for improved coverage 2019-04-29 09:15:46 -07:00
Matt Guthaus 978ba9d2f2 Refactor run scripts. 
Run DRC, LVS, and PEX share a run_*.sh script.
 2019-04-26 15:43:46 -07:00
Matt Guthaus 946a0aca86 Simplify DRC and LVS run scripts. 
Modified run scripts to work on local only files in the temp
directory. This assumes the files and subckts are named the
same as the clel name. Script now copies library files
to the temp directory as well.
 2019-04-26 15:17:39 -07:00
Matt Guthaus 51a97979b9 Add front and back-end test 30. 2019-04-26 15:17:19 -07:00
Matt Guthaus d23aa9a1bd Use local setup.tcl and flatten bitcell arrays. 2019-04-26 14:12:51 -07:00
Matt Guthaus 9cead23f22 Add hierarchy to netgen LVS command. 2019-04-26 13:46:34 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 0439b129bb Some pgates are designs since not a fixed height 2019-04-26 12:33:53 -07:00
Matt Guthaus 05ad4285af Cleanup pgate code. 
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
 2019-04-26 12:30:42 -07:00
Jesse Cirimelli-Low e507fbd5e9 Merge branch 'datasheet_gen' into dev 2019-04-26 12:29:37 -07:00
Matt Guthaus 3ffcad0db8 Add port makeall for removing symmetry problems in netgen 2019-04-26 09:17:52 -07:00
Hunter Nichols f35385f42a Cleaned up names, added exclusions to narrow paths for analysis. 2019-04-24 23:51:09 -07:00
Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules. 2019-04-24 14:23:22 -07:00
Matt Guthaus 59d2e45744 Move characterization on/off feedback to report_status. 2019-04-24 11:30:38 -07:00
Matt Guthaus 7f5e6dd6f8 Fix unconnected supply pin bug in supply router. 
Simplified some of the supply router pin groups so that it assumes
each group is fully connected. When computing enclosures of the
pins on the routing grid, it will remove disconnected enclosure
shapes to keep things connected.
 2019-04-24 10:54:22 -07:00
Matt Guthaus 66c703d932 Simplify router code to clean it up a bit. 2019-04-22 15:30:35 -07:00
Matt Guthaus 5b828f32cb Create auxiliary run_drc.sh and run_lvs.sh with arguments for calibre 2019-04-22 15:12:59 -07:00
Hunter Nichols 4f28295e20 Added initial graph for correct naming 2019-04-19 01:27:06 -07:00
Jesse Cirimelli-Low 49e5f97eb4 fixed bug where log would fail to generate if output folder did not exist 2019-04-17 15:02:10 -07:00
Matt Guthaus 25bc3a66ed Add far left option for contact placement in pgates. 2019-04-17 13:41:35 -07:00
Matt Guthaus a35bf29bdd Improve print output for debugging layout objects. 2019-04-17 13:41:17 -07:00
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
Hunter Nichols c1411f4227 Applied quick corner estimation to analytical delay. 2019-04-09 12:26:54 -07:00
Hunter Nichols a500d7ee3d Adjusted bitcell analytical delays for multiport cells. 2019-04-09 02:49:52 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols 1438519495 Added check to pdriver for 0 fanout which can break compute_sizes. 2019-04-03 17:53:28 -07:00
Hunter Nichols edac60d2a8 Merged with dev and fixed conflicts. 2019-04-03 16:45:01 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Matt Guthaus df4e2fead8 Return empty set instead of a list. 2019-04-01 15:59:57 -07:00
Matt Guthaus 07ecf52b9f Add giant example for front-end mode 2019-04-01 15:49:01 -07:00
Matt Guthaus 5f37677225 Convert pin map to a set for faster membership. 2019-04-01 15:45:44 -07:00
Matt Guthaus 74f904a509 Cleanup options for front-end. Improve info output. 2019-04-01 10:35:17 -07:00
Matt Guthaus c3e074c069 Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
Hunter Nichols 97777475b4 Added additions to account for custom delay chains. 2019-03-28 17:16:23 -07:00
Hunter Nichols 50d3b4cb8d Added some bitline measures to the model_checker 2019-03-19 15:03:57 -07:00
Matt Guthaus 95d96bd45d Add OPENRAM_TMP environment check 2019-03-08 11:12:30 -08:00
Matt Guthaus 0354e2dfb7 Rename config_20 to config since it is used in all tests 2019-03-08 10:47:41 -08:00
Matt Guthaus 196710ec3e Remove factory from lef and verilog tests 2019-03-08 09:22:48 -08:00
Matt Guthaus bd256d33d6 Remove syntax error 2019-03-08 08:35:18 -08:00
Matt Guthaus 7129f79dc4 Merge remote-tracking branch 'origin' into tech_reorg 2019-03-08 08:33:46 -08:00
Matt Guthaus d8f64500e6 Remove factory create from lib tests so that we can give required name 2019-03-08 08:31:26 -08:00
Hunter Nichols e39f9ee481 Merge branch 'dev' into multiport_characterization 2019-03-07 12:31:14 -08:00
Hunter Nichols 910878ed30 Removed bitline measures until hardcoded signal names are made dynamic 2019-03-07 12:30:27 -08:00
Jesse Cirimelli-Low e6311dd44a Merge branch 'datasheet_gen' into dev 2019-03-06 23:47:19 -08:00
Jesse Cirimelli-Low 4754e6851d add_db takes commline line argv for path 2019-03-06 22:21:05 -08:00
Jesse Cirimelli-Low c1770036ac made the add_db code much simpler 2019-03-06 22:20:34 -08:00
Jesse Cirimelli-Low 83e810f8b8 added sorting to deliverables output 2019-03-06 21:12:21 -08:00
Jesse Cirimelli-Low fac9ff9be6 changed add_db.py to uncommenting method 2019-03-06 20:59:52 -08:00
Matt Guthaus 95137a2c26 Wrap debug line 2019-03-06 14:24:24 -08:00
Matt Guthaus 77229d5121 Reduce verbosity 2019-03-06 14:24:18 -08:00
Matt Guthaus c4c844a8a2 Remove duplicate module name checking since we use the factory 2019-03-06 14:14:46 -08:00
Matt Guthaus 09a429aef7 Update unit tests to all use the sram_factory 2019-03-06 14:12:24 -08:00
Matt Guthaus acf2798a18 Add link to presentation in README 2019-03-06 08:29:43 -08:00
Matt Guthaus cfc14f327e Factor default corner out of import_tech 2019-03-06 07:46:30 -08:00
Matt Guthaus d178801882 Simplify tech organization and import 2019-03-06 07:41:38 -08:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols ddeb40c9bf Added lib test which generates multiple corner models. Only does process currently. 2019-03-04 16:27:10 -08:00
Hunter Nichols 7e67b741f6 Merge branch 'dev' into multiport_characterization 2019-03-04 00:43:03 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Matt Guthaus 22deab959c Fix setup_bitcell to allow user to force override the bitcell. 2019-03-03 11:58:41 -08:00
Matt Guthaus abcb1cfa2c Correct elsif to elif 2019-02-28 09:17:24 -08:00
Matt Guthaus da6aa161de Don't autodetect the bitcell if the user overrides it 2019-02-28 09:12:32 -08:00
Matt Guthaus fb7264bae2 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2019-02-28 08:44:18 -08:00
Jesse Cirimelli-Low 3802c537e5 added add_db.py to add .db files to datasheets 2019-02-27 22:20:06 -08:00
Hunter Nichols 816669b9ca Merge branch 'dev' into multiport_characterization 2019-02-26 22:48:39 -08:00
Hunter Nichols ea51cfdbb4 Removed data collection script 2019-02-26 22:46:38 -08:00
Hunter Nichols 42bc6efb21 Added additional graphing and data collection to script 2019-02-26 20:06:35 -08:00
Matt Guthaus f865e66181 Remove git_id file 2019-02-25 16:47:38 -08:00
Matt Guthaus de977732db Only warn if not unit tests 2019-02-25 16:13:54 -08:00
Matt Guthaus 1f1426b97c Add auto-detect of custom bitcells 2019-02-25 16:10:34 -08:00
Matt Guthaus c79b97eb51 Merge remote-tracking branch 'origin/dev' into multiport 2019-02-25 15:46:39 -08:00
Matt Guthaus a4b5368302 Add total size in warning for output size. 2019-02-25 14:57:18 -08:00
Matt Guthaus 638afaeb31 Remove duplicate profile stats script 2019-02-25 10:14:02 -08:00
Matt Guthaus a18071a4ff Add warning for large memory sizes 2019-02-25 10:07:05 -08:00
Jesse Cirimelli-Low 34294443d4 updated logos and css for official colors 2019-02-25 07:46:34 -08:00
Jesse Cirimelli-Low 677588290d merging with dev now that it is passing 2019-02-25 07:05:06 -08:00
Matt Guthaus a210fdda0f Fix arguments for none verification 2019-02-24 10:49:35 -08:00
Matt Guthaus 9b785cd535 Fix error in cell width. Fix escape warning. 2019-02-24 10:48:54 -08:00
Matt Guthaus 4577d380f9 Add example 1w/1r 2019-02-24 09:57:34 -08:00
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r. 2019-02-24 09:54:45 -08:00
Matt Guthaus 6c9ae1c659 Remove temp names in DRC/LVS. Extract unique doesn't actually extract. 2019-02-24 07:26:21 -08:00
Jesse Cirimelli-Low b9525e0f9e Merge branch 'dev' into datasheet_gen 2019-02-23 15:45:51 -08:00
Matt Guthaus 4da56098e7 Merge branch 'magic_lvs_ports' into dev 2019-02-22 19:02:43 -08:00
Matt Guthaus 599e5457a0 Fix all libs to have pin indices 2019-02-22 17:40:49 -08:00
Matt Guthaus 583dc4410b Revert bus bits back into pins 2019-02-22 16:22:27 -08:00
Matt Guthaus 9459839c06 Clean up output file names for lvs. Update lvs script in magic. 2019-02-22 14:38:00 -08:00
Jesse Cirimelli-Low 8c9c910855 Merge branch 'datasheet_gen' into dev 2019-02-22 11:41:03 -08:00
Jesse Cirimelli-Low ff09254590 fixed analytical flag 2019-02-22 08:19:54 -08:00
Jesse Cirimelli-Low 0cabee060d fixed area rounding 2019-02-22 06:57:54 -08:00
Jesse Cirimelli-Low b4f1d53a1b fixed DRC datasheet error 2019-02-22 06:46:28 -08:00
Matt Guthaus d043c72277 Fix temp name error in openram.py 2019-02-21 11:16:21 -08:00
Matt Guthaus bb408d0a45 Add missing / in output path for log 2019-02-21 10:23:30 -08:00
Jennifer Eve Sowash 1249dcc34d Merge branch 'dev' into pdriver 2019-02-20 13:00:58 -08:00
Jennifer Eve Sowash 6d3a29328c Fixed a bug with corner_name in lib.py remaining static. 2019-02-20 12:59:40 -08:00
Jesse Cirimelli-Low 723ec9925f Merge branch 'datasheet_gen' into dev 2019-02-15 21:47:24 -08:00
Jesse Cirimelli-Low d533a8ae26 fixed logger typo 2019-02-15 21:45:05 -08:00
Jesse Cirimelli-Low e3ff9b53e9 fixed area not being found 2019-02-14 07:01:35 -08:00
Hunter Nichols 8c1fe253d5 Added variable fanouts to delay testing. 2019-02-13 22:24:58 -08:00
Jesse Cirimelli-Low 3f761afcbc Merge branch 'datasheet_gen' into dev 2019-02-13 17:43:31 -08:00
Matt Guthaus d4c21cd26e Remove extraneous character. 2019-02-13 17:41:33 -08:00
Matt Guthaus 2553439447 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2019-02-13 17:01:41 -08:00
Matt Guthaus c359bbf42a Fix deprecation warnings in regex by converting to raw strings. Add error if unable to find DRC errors in Magic. 2019-02-13 17:01:26 -08:00
Jesse Cirimelli-Low e890c0e188 fixed -v logging 2019-02-13 15:21:16 -08:00
Hunter Nichols 4faec52409 Allowed data collection and analysis to run independently. 2019-02-12 20:58:50 -08:00
Hunter Nichols a4bb481612 Added tracking for available data. 2019-02-12 16:28:37 -08:00
Jesse Cirimelli-Low 36d8d98b17 Merge branch 'dev' into datasheet_gen 2019-02-08 12:05:04 -08:00
Hunter Nichols 9e23e6584a Made variance plot look slightly better. 2019-02-07 15:30:47 -08:00
Hunter Nichols 5e9851c5f1 Merge branch 'dev' into multiport_characterization 2019-02-07 14:31:26 -08:00
Hunter Nichols ebf43298c0 Added mean/variance plotting 2019-02-07 14:26:48 -08:00
Matt Guthaus d9efb682dd Do not clean up if preserve temp in local_drc_check 2019-02-07 11:08:34 -08:00
Jesse Cirimelli-Low bfc20a9aa9 removes debug corners 2019-02-07 06:38:07 -08:00
Jesse Cirimelli-Low be4b7697cb Merge branch 'dev' into datasheet_gen 2019-02-07 06:35:57 -08:00
Jesse Cirimelli-Low 6cde6beafa added documetation to functions 2019-02-07 06:33:39 -08:00
Hunter Nichols d0edda93ad Added more variance analysis for the delay data 2019-02-07 02:27:22 -08:00
Jesse Cirimelli-Low e131af2cc3 power added to datasheet (finally) 2019-02-06 20:31:22 -08:00
Hunter Nichols 690055174d Fixed bug in control logic test with port configs. 2019-02-06 20:09:01 -08:00
Hunter Nichols 56e79c050b Changed test values to fix tests. 2019-02-06 15:27:29 -08:00
Hunter Nichols 01c8405d12 Fix bitline measurement delays and adjusted default delay chain for column mux srams 2019-02-06 00:46:25 -08:00
Hunter Nichols 5f01a52113 Fixed some delay model bugs. 2019-02-05 21:15:12 -08:00
Jesse Cirimelli-Low 374e7a31eb Merge branch 'dev' into datasheet_gen 2019-02-05 17:14:58 -08:00
Hunter Nichols e3d003d410 Adjusted test values to account for recent changes. 2019-02-05 00:43:16 -08:00
Hunter Nichols 543e0a1b9a Merge branch 'dev' into multiport_characterization 2019-02-04 23:54:16 -08:00
Hunter Nichols 12723adb0c Modified some testing and initial delay chain sizes. 2019-02-04 23:38:26 -08:00
Jesse Cirimelli-Low c22025839c datasheet now indicates if analytical or characterizer is used 2019-01-31 08:28:51 -08:00
Jesse Cirimelli-Low 21868e1b60 removed expanded process names from corners 2019-01-31 08:09:00 -08:00
Hunter Nichols 8d7823e4dd Added delay ratio comparisons between model and measurements 2019-01-31 00:26:27 -08:00
Jesse Cirimelli-Low 475db65d26 added units to AREA on datasheet 2019-01-30 17:49:43 -08:00
Matt Guthaus ec1fb087b5 Check membership of keys without using keys() list 2019-01-30 13:02:34 -08:00
Hunter Nichols 45fceb1f4e Added word per row to sram config with a default arguement to fix test. 2019-01-30 11:43:47 -08:00
Matt Guthaus 74fbe8fe63 Convert source and target lists to sets for faster contains check. 2019-01-30 11:15:47 -08:00
Matt Guthaus 07f4d639eb Remove non-rectangular error and just skip them. 2019-01-30 10:25:01 -08:00
Matt Guthaus 7836929db2 Use hash of tuples instead of checking rectangle in list 2019-01-30 10:03:07 -08:00
Matt Guthaus aaf028cacf Optimize hpwl runtime. Fix error in via cost when L shape. 2019-01-30 08:49:47 -08:00
Matt Guthaus 82a09be026 Move inspect into if statement for runtime 2019-01-30 08:42:25 -08:00
Hunter Nichols c10c9e4009 Refactored some code and other additional improvements. 2019-01-29 23:02:28 -08:00
Hunter Nichols 242a63accb Fixed issues introduced by pdriver additions in model unit test 2019-01-29 16:43:30 -08:00
Hunter Nichols d1218778b1 Fixed merge conflicts 2019-01-28 22:33:08 -08:00
Matt Guthaus 1bdf4dbe4f Re-enable abort on supply error. 2019-01-28 17:07:38 -08:00
Matt Guthaus 47a3dfafee Merge branch 'driver_sizing' into dev 2019-01-28 15:12:01 -08:00
Matt Guthaus f84dc3cadc Fix hspice delay golden results 2019-01-28 10:39:09 -08:00
Jesse Cirimelli-Low ed901aba5f changed datetime to date 2019-01-28 10:29:27 -08:00
Matt Guthaus d77bba3af2 Fix clock fanout to include internal FF. Update delays in golden tests. 2019-01-28 08:48:32 -08:00
Matt Guthaus 881c449c7c Fix error in offset computation for right drivers 2019-01-28 07:53:36 -08:00
Matt Guthaus c4438584fe Move jog for wl to mid-cells rather than mid-pins. 2019-01-27 12:59:02 -08:00
Matt Guthaus 18805423e3 Simplify pdriver code. 2019-01-25 17:18:12 -08:00
Matt Guthaus beceb3fb60 Fix buggy analytical delay in pdriver 2019-01-25 16:22:59 -08:00
Matt Guthaus 01ab253925 Move gdsMill license to README 2019-01-25 15:56:12 -08:00
Matt Guthaus d2864370aa Temporarily disable abort on supply error 2019-01-25 15:43:57 -08:00
Matt Guthaus 09d6a63861 Change path to wire_path for Anaconda package conflict 2019-01-25 15:07:56 -08:00
Matt Guthaus 0c3baa5172 Added some comments to the spice files. 2019-01-25 15:00:00 -08:00
Matt Guthaus 1afd4341bd Update stage effort of clk_buf_driver 2019-01-25 14:22:37 -08:00
Matt Guthaus 6f32bac1a2 Use rx of last pdriver instance after placing instances 2019-01-25 14:17:37 -08:00
Matt Guthaus 614aa54f17 Move clkbuf output lower to avoid dff outputs 2019-01-25 14:03:52 -08:00
Matt Guthaus ddf734891a Fix pdriver width error 2019-01-25 10:26:31 -08:00
Matt Guthaus 8f56953af0 Convert wordline driver to use sized pdriver 2019-01-24 10:20:23 -08:00
Hunter Nichols ee03b4ecb8 Added some data variation checking 2019-01-24 09:25:09 -08:00
Jesse Cirimelli-Low 65c5cc9fe7 added support for more corner variations 2019-01-24 07:09:51 -08:00
Matt Guthaus 091b4e4c62 Add size commments to spize. Change pdriver stage effort. 2019-01-23 17:27:15 -08:00
Hunter Nichols d527b7da62 Added delay error calculations 2019-01-23 13:19:35 -08:00
Matt Guthaus 8a85d3141a Fix polarity problem. 2019-01-23 13:08:43 -08:00
Matt Guthaus d64d262d78 Fix pdriver instantiation. Change sizes based on word_size. 2019-01-23 12:51:28 -08:00
Matt Guthaus b58fd03083 Change pbuf/pinv to pdriver in control logic. 2019-01-23 12:03:52 -08:00
Hunter Nichols 6d3884d60d Added corner data collection. 2019-01-22 16:40:46 -08:00
Jesse Cirimelli-Low ac17e71973 removed debug print statement 2019-01-22 15:47:16 -08:00
Jesse Cirimelli-Low 886dd4d313 Merge branch 'dev' into datasheet_gen 2019-01-22 15:24:44 -08:00
Jesse Cirimelli-Low 978990f4dd cleaned up debug.py edits 2019-01-22 15:24:38 -08:00
Matt Guthaus 23718b952f Check for print statements in more files since we now use print_raw 2019-01-18 10:16:55 -08:00
Matt Guthaus f5f27073be Merge remote-tracking branch 'origin/dev' into factory 2019-01-18 09:52:18 -08:00
Hunter Nichols 5885e3b635 Removed carriage returns, adjusted signal names generation for variable delay chain size. 2019-01-18 00:23:50 -08:00
Yusu Wang c20fb2a70e replace matrix to array 2019-01-17 12:01:08 -08:00
Hunter Nichols 4ced6be6bd Added data collection and some initial data 2019-01-17 09:54:34 -08:00
Hunter Nichols 5bbc43d0a0 Added data collection of wordline and s_en measurements. 2019-01-17 01:59:41 -08:00
Jesse Cirimelli-Low 9c8090d94b added debug.info to logging 2019-01-16 19:56:23 -08:00
Matt Guthaus 7a152ea13d Move sram_factory to root dir 2019-01-16 17:06:29 -08:00
Matt Guthaus 9ecfaf16ea Add the factory class 2019-01-16 17:04:28 -08:00
Matt Guthaus 91636be642 Convert all contacts to use the sram_factory 2019-01-16 16:56:06 -08:00
Matt Guthaus 5192a01f2d Convert pgates to use ptx through the factory 2019-01-16 16:30:31 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Jesse Cirimelli-Low 25b0da404f removed EOL error in comment 2019-01-16 16:08:41 -08:00
Jesse Cirimelli-Low 41b8e8665b updated datasheet descriptors 2019-01-16 15:43:08 -08:00
Jesse Cirimelli-Low 0556b86424 html datasheet no longer dependeds on sram 2019-01-16 14:52:01 -08:00
Jesse Cirimelli-Low 192c615a38 moved library page to new repo 2019-01-16 07:33:17 -08:00
Hunter Nichols cc0be510c7 Added some data scaling and error calculation in model check. 2019-01-16 00:46:24 -08:00
Jesse Cirimelli-Low 813a551691 comment parsing 1/2 complete; page gen setup complete 2019-01-15 20:48:20 -08:00
Jesse Cirimelli-Low 903cafb336 html parsing finished 2019-01-15 19:47:48 -08:00
Hunter Nichols 6152ec7ec5 Merge branch 'dev' into multiport_characterization 2019-01-15 16:33:39 -08:00
Jesse Cirimelli-Low b66c53a99a added log file to datasheet 2019-01-13 15:02:13 -08:00
Jesse Cirimelli-Low 87380a4801 complete log file generation 2019-01-13 14:34:46 -08:00
Matt Guthaus e210ef2a41 Add assert to lef and verilog unit test. Fix verilog files in golden results. 2019-01-11 16:42:50 -08:00
Matt Guthaus a7dd62b0e5 falling_edge not negative_edge 2019-01-11 15:17:27 -08:00
Matt Guthaus 20b869f8e1 Remove tabs 2019-01-11 14:16:57 -08:00
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
Matt Guthaus f0ab155172 Change dout to negative clock edge relative 2019-01-11 09:51:05 -08:00
Hunter Nichols 21663439cc Added slews measurements to the model checker. Removed unused code in bitline delay class. 2019-01-09 22:42:34 -08:00
Jesse Cirimelli-Low a25e0f6c8c Merge branch 'dev' into datasheet_gen 2019-01-09 13:48:43 -08:00