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Fix error in offset computation for right drivers

This commit is contained in:
Matt Guthaus 2019-01-28 07:53:36 -08:00
parent c4438584fe
commit 881c449c7c
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/bank.py
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@ -1088,7 +1088,7 @@ class bank(design.design):
driver_wl_pos = self.wordline_driver_inst[port].get_pin("wl_{}".format(row)).lc()
bitcell_wl_pos = self.bitcell_array_inst.get_pin(self.wl_names[port]+"_{}".format(row)).rc()
mid1 = driver_wl_pos.scale(0,1) + vector(0.5*self.wordline_driver_inst[port].lx() + 0.5*self.bitcell_array_inst.rx(),0)
mid2 = mid1.scale(1,0)+bitcell_wl_pos.scale(0.5,1)
mid2 = mid1.scale(1,0)+bitcell_wl_pos.scale(0,1)
self.add_path("metal1", [driver_wl_pos, mid1, mid2, bitcell_wl_pos])
def route_column_address_lines(self, port):