mirror of https://github.com/VLSIDA/OpenRAM.git
Fix deprecation warnings in regex by converting to raw strings. Add error if unable to find DRC errors in Magic.
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@ -126,9 +126,9 @@ def run_drc(cell_name, gds_name, extract=False, final_verification=False):
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f.close()
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# those lines should be the last 3
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results = results[-3:]
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geometries = int(re.split("\W+", results[0])[5])
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rulechecks = int(re.split("\W+", results[1])[4])
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errors = int(re.split("\W+", results[2])[5])
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geometries = int(re.split(r'\W+', results[0])[5])
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rulechecks = int(re.split(r'\W+', results[1])[4])
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n errors = int(re.split(r'\W+', results[2])[5])
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# always display this summary
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if errors > 0:
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@ -227,7 +227,7 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
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incorrect = list(filter(test.search, results))
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# Errors begin with "Error:"
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test = re.compile("\s+Error:")
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test = re.compile(r'\s+Error:')
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errors = list(filter(test.search, results))
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for e in errors:
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debug.error(e.strip("\n"))
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@ -363,7 +363,7 @@ def correct_port(name, output_file_name, ref_file_name):
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pex_file.seek(match_index_start)
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rest_text = pex_file.read()
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# locate the end of circuit definition line
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match = re.search("\* \n", rest_text)
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match = re.search(r'\* \n', rest_text)
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match_index_end = match.start()
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# store the unchanged part of pex file in memory
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pex_file.seek(0)
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@ -140,11 +140,15 @@ def run_drc(cell_name, gds_name, extract=True, final_verification=False):
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debug.error("Unable to retrieve DRC results file. Is magic set up?",1)
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results = f.readlines()
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f.close()
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errors=1
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# those lines should be the last 3
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for line in results:
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if "Total DRC errors found:" in line:
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errors = int(re.split(": ", line)[1])
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break
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else:
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debug.error("Unable to find the total error line in Magic output.",1)
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# always display this summary
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if errors > 0:
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