mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' into multiport_characterization
This commit is contained in:
commit
7e67b741f6
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@ -165,21 +165,25 @@ def setup_bitcell():
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"""
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global OPTS
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if (OPTS.num_rw_ports==1 and OPTS.num_w_ports==0 and OPTS.num_r_ports==0):
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OPTS.bitcell = "bitcell"
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OPTS.replica_bitcell = "replica_bitcell"
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# If we have non-1rw ports, figure out the right bitcell to use
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else:
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ports = ""
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if OPTS.num_rw_ports>0:
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ports += "{}rw_".format(OPTS.num_rw_ports)
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if OPTS.num_w_ports>0:
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ports += "{}w_".format(OPTS.num_w_ports)
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if OPTS.num_r_ports>0:
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ports += "{}r".format(OPTS.num_r_ports)
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# If we have non-1rw ports,
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# and the user didn't over-ride the bitcell manually,
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# figure out the right bitcell to use
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if (OPTS.bitcell=="bitcell" and OPTS.replica_bitcell=="replica_bitcell"):
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if (OPTS.num_rw_ports==1 and OPTS.num_w_ports==0 and OPTS.num_r_ports==0):
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OPTS.bitcell = "bitcell"
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OPTS.replica_bitcell = "replica_bitcell"
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else:
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ports = ""
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if OPTS.num_rw_ports>0:
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ports += "{}rw_".format(OPTS.num_rw_ports)
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if OPTS.num_w_ports>0:
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ports += "{}w_".format(OPTS.num_w_ports)
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if OPTS.num_r_ports>0:
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ports += "{}r".format(OPTS.num_r_ports)
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OPTS.bitcell = "bitcell_"+ports
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OPTS.replica_bitcell = "replica_bitcell_"+ports
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OPTS.bitcell = "bitcell_"+ports
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OPTS.replica_bitcell = "replica_bitcell_"+ports
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# See if a custom bitcell exists
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from importlib import find_loader
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@ -193,8 +197,8 @@ def setup_bitcell():
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OPTS.replica_bitcell = "replica_pbitcell"
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if not OPTS.is_unit_test:
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debug.warning("Using the parameterized bitcell which may have suboptimal density.")
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else:
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debug.info(1,"Using custom bitcell: {}".format(OPTS.bitcell))
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debug.info(1,"Using bitcell: {}".format(OPTS.bitcell))
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def get_tool(tool_type, preferences, default_name=None):
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@ -1,5 +0,0 @@
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import pstats
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p = pstats.Stats('profile.dat')
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p.strip_dirs()
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p.sort_stats('cumulative')
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p.print_stats(50)
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