luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Correct elsif to elif

This commit is contained in:
Matt Guthaus 2019-02-28 09:17:24 -08:00
parent da6aa161de
commit abcb1cfa2c
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
compiler/globals.py
View File

@ -171,7 +171,7 @@ def setup_bitcell():
# If we have non-1rw ports,
# and the user didn't over-ride the bitcell manually,
# figure out the right bitcell to use
elsif (OPTs.bitcell=="bitcell" and OPTS.replica_bitcell=="replica_bitcell"):
elif (OPTs.bitcell=="bitcell" and OPTS.replica_bitcell=="replica_bitcell"):
ports = ""
if OPTS.num_rw_ports>0:
ports += "{}rw_".format(OPTS.num_rw_ports)