mirror of https://github.com/VLSIDA/OpenRAM.git
Move characterization on/off feedback to report_status.
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7f5e6dd6f8
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59d2e45744
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@ -477,11 +477,20 @@ def report_status():
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debug.print_raw("Netlist only mode (no physical design is being done, netlist_only=False to disable).")
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if not OPTS.route_supplies:
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debug.print_raw("Design supply routing skipped for run-time (incomplete GDS will not be saved, route_supplies=True to enable).")
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debug.print_raw("Design supply routing skipped for run-time (incomplete GDS will not be saved) (route_supplies=True to enable).")
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if not OPTS.inline_lvsdrc:
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debug.print_raw("DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to enable).")
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if not OPTS.check_lvsdrc:
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debug.print_raw("DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).")
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if OPTS.analytical_delay:
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debug.print_raw("Characterization is disabled (using analytical delay models) (analytical_delay=False to enable).")
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else:
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if OPTS.spice_name!="":
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debug.print_raw("Performing simulation-based characterization with {}".format(OPTS.spice_name))
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if OPTS.trim_netlist:
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debug.print_raw("Trimming netlist to speed up characterization (trim_netlist=False to disable).")
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@ -102,13 +102,6 @@ class sram():
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start_time = datetime.datetime.now()
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from characterizer import lib
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debug.print_raw("LIB: Characterizing... ")
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if OPTS.analytical_delay:
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debug.print_raw("Using analytical delay models (no characterization)")
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else:
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if OPTS.spice_name!="":
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debug.print_raw("Performing simulation-based characterization with {}".format(OPTS.spice_name))
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if OPTS.trim_netlist:
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debug.print_raw("Trimming netlist to speed up characterization.")
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lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
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print_time("Characterization", datetime.datetime.now(), start_time)
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