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Fix error in cell width. Fix escape warning.

This commit is contained in:
Matt Guthaus 2019-02-24 10:48:54 -08:00
parent 4577d380f9
commit 9b785cd535
2 changed files with 3 additions and 3 deletions
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2
compiler/verify/magic.py
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@ -45,7 +45,7 @@ def write_magic_script(cell_name, gds_name, extract=False, final_verification=Fa
#f.write("load {}_new\n".format(cell_name))
#f.write("cellname rename {0}_new {0}\n".format(cell_name))
#f.write("load {}\n".format(cell_name))
f.write("cellname delete \(UNNAMED\)\n")
f.write("cellname delete \\(UNNAMED\\)\n")
f.write("writeall force\n")
f.write("select top cell\n")
f.write("expand\n")

4
technology/freepdk45/sp_lib/cell_1w_1r.sp vendored
View File

@ -6,8 +6,8 @@ MM7 RA_to_R_left Q_bar gnd gnd NMOS_VTG W=180.0n L=50n m=1
MM6 RA_to_R_left wl1 bl1 gnd NMOS_VTG W=180.0n L=50n m=1
MM5 Q wl0 bl0 gnd NMOS_VTG W=135.00n L=50n m=1
MM4 Q_bar wl0 br0 gnd NMOS_VTG W=135.00n L=50n m=1
MM1 Q Q_bar gnd gnd NMOS_VTG W=270.0n L=50n m=1
MM0 Q_bar Q gnd gnd NMOS_VTG W=270.0n L=50n m=1
MM1 Q Q_bar gnd gnd NMOS_VTG W=205.0n L=50n m=1
MM0 Q_bar Q gnd gnd NMOS_VTG W=205.0n L=50n m=1
MM3 Q Q_bar vdd vdd PMOS_VTG W=90n L=50n m=1
MM2 Q_bar Q vdd vdd PMOS_VTG W=90n L=50n m=1
.ENDS