Added more accurate bitline delay capacitance estimations

compiler/modules/bank.py

@@ -1224,6 +1224,7 @@ class bank(design.design):
 
         #FIXME: Array delay is the same for every port.
         word_driver_slew =  0
+        port = 0
         if self.words_per_row > 1:
             bitline_ext_load = self.column_mux_array[port].get_drain_cin()
         else:
@@ -1234,7 +1235,7 @@ class bank(design.design):
         bitcell_array_slew = 0
         #This also essentially creates the same delay for each port. Good structure, no substance
         if self.words_per_row > 1:
-            sa_load = self.sense_amp_array.get_drain_load()
+            sa_load = self.sense_amp_array.get_drain_cin()
             column_mux_delay = self.column_mux_array[port].analytical_delay(corner, 
                                                                             bitcell_array_slew,
                                                                             sa_load)

compiler/modules/bitcell_array.py

@@ -132,11 +132,12 @@ class bitcell_array(design.design):
     
     def analytical_delay(self, corner, slew, load):
         """Returns relative delay of the bitline in the bitcell array"""
+        from tech import parameter
         #The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
         #The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
-        drain_parasitics = .5 #each bitcell adds half a parasitic to the delay
-        wire_parasitics = .05 * drain_parasitics #Wires add 5% to this.
-        bitline_load = (drain_parasitics+wire_parasitics)*self.row_size * logical_effort.logical_effort.pinv
+        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
+        wire_unit_load = .05 * drain_load #Wires add 5% to this.
+        bitline_load = (drain_load+wire_unit_load)*self.row_size
         return [self.cell.analytical_delay(corner, slew, load+bitline_load)]
     
     def analytical_power(self, corner, load):

compiler/modules/sense_amp_array.py

@@ -147,6 +147,7 @@ class sense_amp_array(design.design):
         
     def get_drain_cin(self):
         """Get the relative capacitance of the drain of the PMOS isolation TX"""
-        #Estimated as half a parasitic delay.
-        drain_parasitics = .5
-        return drain_parasitics * logical_effort.logical_effort.pinv  
+        from tech import parameter
+        #Bitcell drain load being used to estimate PMOS drain load
+        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
+        return drain_load

compiler/modules/single_level_column_mux_array.py

@@ -216,28 +216,18 @@ class single_level_column_mux_array(design.design):
                 self.add_via(layers=("metal1", "via1", "metal2"),
                              offset= br_out_offset,
                              rotate=90)
-
-    def analytical_delay(self, corner, vdd, slew, load=0.0):
-        from tech import spice, parameter
-        proc,vdd,temp = corner
-        r = spice["min_tx_r"]/(self.mux.ptx_width/parameter["min_tx_size"])
-        #Drains of mux transistors make up capacitance. 
-        c_para = spice["min_tx_drain_c"]*(self.mux.ptx_width/parameter["min_tx_size"])*self.words_per_row#ff
-        volt_swing = spice["v_threshold_typical"]/vdd
-        
-        result = self.cal_delay_with_rc(corner, r = r, c =  c_para+load, slew = slew, swing = volt_swing)
-        return self.return_delay(result.delay, result.slew)            
-            
-
+       
     def analytical_delay(self, corner, slew, load):
+        from tech import parameter
         """Returns relative delay that the column mux adds"""
         #Single level column mux will add parasitic loads from other mux pass transistors and the sense amp.
-        drain_parasitics = .5 #Assumed parasitics from unused TXs
-        array_load = drain_parasitics*self.words_per_row*logical_effort.logical_effort.pinv
+        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
+        array_load = drain_load*self.words_per_row
         return [self.mux.analytical_delay(corner, slew, load+array_load)]
         
     def get_drain_cin(self):
         """Get the relative capacitance of the drain of the NMOS pass TX"""
-        #Estimated as half a parasitic delay.
-        drain_parasitics = .5
-        return drain_parasitics * logical_effort.logical_effort.pinv      
+        from tech import parameter
+        #Bitcell drain load being used to estimate mux NMOS drain load
+        drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
+        return drain_load      

compiler/pgates/single_level_column_mux.py

@@ -5,6 +5,7 @@ from vector import vector
 import contact
 from globals import OPTS
 from sram_factory import factory
+import logical_effort
 
 class single_level_column_mux(design.design):
     """

technology/freepdk45/tech/tech.py

@@ -349,6 +349,7 @@ parameter["sa_en_nmos_size"] = .27          #micro-meters
 parameter["sa_inv_pmos_size"] = .54          #micro-meters
 parameter["sa_inv_nmos_size"] = .27          #micro-meters
 parameter["rbl_height_percentage"] = .5     #Height of RBL compared to bitcell array 
+parameter['bitcell_drain_cap'] = 0.1        #In Femto-Farad, approximation of drain capacitance
 
 ###################################################
 ##END Spice Simulation Parameters

technology/scn4m_subm/tech/tech.py

@@ -315,6 +315,7 @@ parameter["sa_en_nmos_size"] = 9*_lambda_
 parameter["sa_inv_pmos_size"] = 18*_lambda_
 parameter["sa_inv_nmos_size"] = 9*_lambda_
 parameter["rbl_height_percentage"] = .5     #Height of RBL compared to bitcell array 
+parameter['bitcell_drain_cap'] = 0.2        #In Femto-Farad, approximation of drain capacitance
 
 ###################################################
 ##END Spice Simulation Parameters