Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

compiler/datasheet/assets/datasheet.css

@@ -19,8 +19,8 @@
     padding-top: 11px;
     padding-bottom: 11px;
     text-align: left;
-    background-color: 	#004184;
-    color: #F1B521;
+    background-color: 	#003C6C;
+    color: #FDC700;
 }
 
 

compiler/datasheet/datasheet.py

@@ -35,11 +35,10 @@ class datasheet():
 
         # Add openram logo
         openram_logo = 0
-        with open(os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/datasheet/assets/openram_logo_placeholder.png', "rb") as image_file:
+        with open(os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/datasheet/assets/OpenRAM_logo.png', "rb") as image_file:
             openram_logo = base64.b64encode(image_file.read())
 
-        self.html += '<a href="https://vlsida.soe.ucsc.edu/"><img src="data:image/png;base64,{0}" alt="VLSIDA"></a>'.format(str(vlsi_logo)[
-                                                                                                                            2:-1])
+        self.html += '<a href="https://vlsida.soe.ucsc.edu/"><img src="data:image/png;base64,{0}" alt="VLSIDA"></a><a href ="https://github.com/VLSIDA/OpenRAM"><img src ="data:image/png;base64,{1}" alt = "OpenRAM"></a>'.format(str(vlsi_logo)[2:-1], str(openram_logo)[2:-1])
 
         self.html += '<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">' + \
             self.name + '.html' + '</p>'
@@ -53,7 +52,7 @@ class datasheet():
         # print port table
         self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration</p>'
         self.html += self.io_table.to_html()
-        
+
         # print operating condidition information
         self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Operating Conditions</p>'
         self.html += self.operating_table.to_html()
@@ -61,8 +60,8 @@ class datasheet():
         # check if analytical model is being used
         self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Timing Data</p>'
         model = ''
-        if self.ANALYTICAL_MODEL:
-            model = "analytical model: results may not be percise"
+        if self.ANALYTICAL_MODEL == 'True':
+            model = "analytical model: results may not be precise"
         else:
             model = "spice characterizer"
         # display timing data

compiler/datasheet/datasheet_gen.py

@@ -105,16 +105,16 @@ def parse_characterizer_csv(f, pages):
 
             DATETIME = row[col]
             col += 1
+          
+            ANALYTICAL_MODEL = row[col]
+            col += 1
 
             DRC = row[col]
             col += 1
 
             LVS = row[col]
             col += 1
-
-            ANALYTICAL_MODEL = row[col]
-            col += 1
-
+ 
             AREA = row[col]
             col += 1
 
@@ -615,7 +615,7 @@ def parse_characterizer_csv(f, pages):
                 new_sheet.io_table.add_row(['NUM_R_PORTS', NUM_R_PORTS])
                 new_sheet.io_table.add_row(['NUM_W_PORTS', NUM_W_PORTS])
                 new_sheet.io_table.add_row(
-                    ['Area (&microm<sup>2</sup>)', AREA])
+                    ['Area (&microm<sup>2</sup>)', str(round(float(AREA)))])
 
 
 class datasheet_gen():

compiler/example_configs/example_config_1rw_1r_scn4m_subm.py

@@ -1,8 +1,6 @@
 word_size = 2
 num_words = 16
 
-bitcell = "bitcell_1rw_1r"
-replica_bitcell = "replica_bitcell_1rw_1r"
 num_rw_ports = 1
 num_r_ports = 1
 num_w_ports = 0

compiler/example_configs/example_config_1w_1r_scn4m_subm.py

@@ -1,8 +1,6 @@
 word_size = 2
 num_words = 16
 
-bitcell = "bitcell_1w_1r"
-replica_bitcell = "replica_bitcell_1w_1r"
 num_rw_ports = 1
 num_r_ports = 1
 num_w_ports = 0

compiler/git_id

@@ -1 +0,0 @@
-468eb9a4a038201c2b0004fe6e4ae9b2d37fdd57

compiler/globals.py

@@ -132,6 +132,8 @@ def init_openram(config_file, is_unit_test=True):
 
     from sram_factory import factory
     factory.reset()
+
+    setup_bitcell()
     
     # Reset the static duplicate name checker for unit tests.
     import hierarchy_design
@@ -157,6 +159,42 @@ def init_openram(config_file, is_unit_test=True):
     if not CHECKPOINT_OPTS:
         CHECKPOINT_OPTS = copy.copy(OPTS)
     
+def setup_bitcell():
+    """
+    Determine the correct custom or parameterized bitcell for the design.
+    """
+    global OPTS
+
+    if (OPTS.num_rw_ports==1 and OPTS.num_w_ports==0 and OPTS.num_r_ports==0):
+        OPTS.bitcell = "bitcell"
+        OPTS.replica_bitcell = "replica_bitcell"
+    # If we have non-1rw ports, figure out the right bitcell to use
+    else:
+        ports = ""
+        if OPTS.num_rw_ports>0:
+            ports += "{}rw_".format(OPTS.num_rw_ports)
+        if OPTS.num_w_ports>0:
+            ports += "{}w_".format(OPTS.num_w_ports)
+        if OPTS.num_r_ports>0:
+            ports += "{}r".format(OPTS.num_r_ports)
+
+        OPTS.bitcell = "bitcell_"+ports
+        OPTS.replica_bitcell = "replica_bitcell_"+ports
+
+        # See if a custom bitcell exists
+        from importlib import find_loader
+        bitcell_loader = find_loader(OPTS.bitcell)
+        replica_bitcell_loader = find_loader(OPTS.replica_bitcell)
+        # Use the pbitcell if we couldn't find a custom bitcell
+        # or its custom replica  bitcell
+        if bitcell_loader==None or replica_bitcell_loader==None:
+            # Use the pbitcell (and give a warning if not in unit test mode)
+            OPTS.bitcell = "pbitcell"
+            OPTS.replica_bitcell = "replica_pbitcell"
+            if not OPTS.is_unit_test:
+                debug.warning("Using the parameterized bitcell which may have suboptimal density.")
+        else:
+            debug.info(1,"Using custom bitcell: {}".format(OPTS.bitcell))    
 
 
 def get_tool(tool_type, preferences, default_name=None):
@@ -250,7 +288,8 @@ def read_config(config_file, is_unit_test=True):
                                                          OPTS.num_words,
                                                          ports,
                                                          OPTS.tech_name)
-    
+
+        
 
         
 def end_openram():
@@ -417,7 +456,11 @@ def report_status():
         debug.error("Tech name must be specified in config file.")
 
     debug.print_raw("Technology: {0}".format(OPTS.tech_name))
-    debug.print_raw("Total size: {} bits".format(OPTS.word_size*OPTS.num_words*OPTS.num_banks))
+    total_size = OPTS.word_size*OPTS.num_words*OPTS.num_banks
+    debug.print_raw("Total size: {} bits".format(total_size))
+    if total_size>=2**14:
+        debug.warning("Requesting such a large memory size ({0}) will have a large run-time. ".format(total_size) +
+                      "Consider using multiple smaller banks.")
     debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
                                                           OPTS.num_words,
                                                           OPTS.num_banks))