mirror of https://github.com/VLSIDA/OpenRAM.git
Exclude new precharge in graph build
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8b0b2e2817
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0cb86b8ba2
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@ -1014,9 +1014,9 @@ class bank(design.design):
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def graph_exclude_precharge(self):
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"""Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
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for inst in self.precharge_array_inst:
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if inst != None:
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self.graph_inst_exclude.add(inst)
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for port in self.read_ports:
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if self.port_data[port]:
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self.port_data[port].graph_exclude_precharge()
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def get_cell_name(self, inst_name, row, col):
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"""Gets the spice name of the target bitcell."""
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@ -494,4 +494,7 @@ class port_data(design.design):
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self.add_path("metal2",[bottom_br, vector(bottom_br.x,yoffset),
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vector(top_br.x,yoffset), top_br])
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def graph_exclude_precharge(self):
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"""Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
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if self.precharge_array_inst:
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self.graph_inst_exclude.add(self.precharge_array_inst)
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