Fix dummy row LVS issue

compiler/bitcells/dummy_bitcell.py

@@ -0,0 +1,48 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import design
+import debug
+import utils
+from tech import GDS,layer,parameter,drc
+import logical_effort
+
+class dummy_bitcell(design.design):
+    """
+    A single bit cell (6T, 8T, etc.)  This module implements the
+    single memory cell used in the design. It is a hand-made cell, so
+    the layout and netlist should be available in the technology
+    library.
+    """
+
+    pin_names = ["bl", "br", "wl", "vdd", "gnd"]
+    (width,height) = utils.get_libcell_size("dummy_cell_6t", GDS["unit"], layer["boundary"])
+    pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_6t", GDS["unit"])
+
+    def __init__(self, name=""):
+        # Ignore the name argument
+        design.design.__init__(self, "dummy_cell_6t")
+        debug.info(2, "Create dummy bitcell")
+
+        self.width = dummy_bitcell.width
+        self.height = dummy_bitcell.height
+        self.pin_map = dummy_bitcell.pin_map
+
+    def analytical_power(self, corner, load):
+        """Bitcell power in nW. Only characterizes leakage."""
+        from tech import spice
+        leakage = spice["bitcell_leakage"]
+        dynamic = 0 #temporary
+        total_power = self.return_power(dynamic, leakage)
+        return total_power
+
+    def get_wl_cin(self):
+        """Return the relative capacitance of the access transistor gates"""
+        #This is a handmade cell so the value must be entered in the tech.py file or estimated.
+        #Calculated in the tech file by summing the widths of all the related gates and dividing by the minimum width.
+        access_tx_cin = parameter["6T_access_size"]/drc["minwidth_tx"]
+        return 2*access_tx_cin

technology/scn4m_subm/mag_lib/dummy_cell_6t.mag

@@ -1,6 +1,6 @@
 magic
 tech scmos
-timestamp 1536091415
+timestamp 1560540221
 << nwell >>
 rect -8 29 42 51
 << pwell >>
@@ -92,17 +92,18 @@ rect 32 16 36 22
 rect -2 6 17 9
 rect 21 6 36 9
 rect -2 5 36 6
+rect 6 -2 10 2
+rect 20 -2 24 2
 << m2contact >>
 rect 15 44 19 48
 rect -2 29 2 33
 rect 32 29 36 33
-rect 6 -2 10 2
-rect 20 -2 24 2
 << metal2 >>
 rect -2 33 2 48
 rect -2 -2 2 29
-rect 6 2 10 48
-rect 24 -2 28 48
+rect 6 -2 10 48
+rect 24 2 28 48
+rect 20 -2 28 2
 rect 32 33 36 48
 rect 32 -2 36 29
 << bb >>

technology/scn4m_subm/mag_lib/setup.tcl

@@ -4,6 +4,7 @@ equate class {-circuit1 nfet} {-circuit2 n}
 equate class {-circuit1 pfet} {-circuit2 p}
 # This circuit has symmetries and needs to be flattened to resolve them
 # or the banks won't pass
+flatten class {-circuit1 dummy_cell_6t}
 flatten class {-circuit1 bitcell_array_0}
 flatten class {-circuit1 bitcell_array_1}
 #flatten class {-circuit1 precharge_array_0}

technology/scn4m_subm/sp_lib/dummy_cell_6t.sp

@@ -1,7 +1,6 @@
 
-*********************** "cell_6t" ******************************
-.SUBCKT cell_6t bl br wl vdd gnd
-* SPICE3 file created from cell_6t.ext - technology: scmos
+*********************** "dummy_cell_6t" ******************************
+.SUBCKT dummy_cell_6t bl br wl vdd gnd
 
 * Inverter 1
 M1000 Q Qbar vdd vdd p w=0.6u l=0.8u