mirror of https://github.com/VLSIDA/OpenRAM.git
Begin single layer supply router
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mrg
parent
4612c9c182
commit
bd4d965e37
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@ -26,16 +26,17 @@ class design(hierarchy_design):
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self.setup_drc_constants()
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self.setup_multiport_constants()
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from tech import layer
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self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(self.m1_space, self.m2_space)
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self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space, self.m3_space)
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if contact.m3m4:
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if "metal4" in layer:
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self.m3_pitch = max(contact.m3m4.width,contact.m3m4.height) + max(self.m3_space, self.m4_space)
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else:
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self.m3_pitch = self.m2_pitch
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def setup_drc_constants(self):
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""" These are some DRC constants used in many places in the compiler."""
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from tech import drc
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from tech import drc,layer
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self.well_width = drc("minwidth_well")
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self.poly_width = drc("minwidth_poly")
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self.poly_space = drc("poly_to_poly")
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@ -45,7 +46,7 @@ class design(hierarchy_design):
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self.m2_space = drc("metal2_to_metal2")
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self.m3_width = drc("minwidth_metal3")
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self.m3_space = drc("metal3_to_metal3")
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if contact.m3m4:
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if "metal4" in layer:
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self.m4_width = drc("minwidth_metal4")
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self.m4_space = drc("metal4_to_metal4")
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self.active_width = drc("minwidth_active")
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@ -42,6 +42,7 @@ class design_rules():
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return rule
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else:
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debug.error("Must call complex DRC rule {} with arguments.".format(b),-1)
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@ -839,6 +839,15 @@ class router(router_tech):
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self.rg.add_target(pin_in_tracks)
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def add_pin_component_target_except(self, pin_name, index):
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"""
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This will mark the grids for all *other* pin components as a target.
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Marking as source or target also clears blockage status.
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"""
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for i in range(self.num_pin_components(pin_name)):
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if i != index:
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self.add_pin_component_target(pin_name, i)
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def set_component_blockages(self, pin_name, value=True):
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"""
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Block all of the pin components.
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@ -24,19 +24,28 @@ class router_tech:
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"""
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self.layers = layers
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self.rail_track_width = rail_track_width
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(self.horiz_layer_name, self.via_layer_name, self.vert_layer_name) = self.layers
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# This is the minimum routed track spacing
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via_connect = contact(self.layers, (1, 1))
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max_via_size = max(via_connect.width,via_connect.height)
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self.horiz_layer_number = layer[self.horiz_layer_name]
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self.vert_layer_number = layer[self.vert_layer_name]
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if self.rail_track_width>1:
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print(self.layers,len(self.layers))
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if len(self.layers)==1:
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self.horiz_layer_name = self.vert_layer_name = self.layers[0]
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self.horiz_layer_number = self.vert_layer_number = layer[self.layers[0]]
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(self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_supply_layer_width_space(1)
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(self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_supply_layer_width_space(0)
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self.horiz_track_width = self.horiz_layer_minwidth + self.horiz_layer_spacing
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self.vert_track_width = self.vert_layer_minwidth + self.vert_layer_spacing
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else:
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(self.horiz_layer_name, self.via_layer_name, self.vert_layer_name) = self.layers
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via_connect = contact(self.layers, (1, 1))
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max_via_size = max(via_connect.width,via_connect.height)
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self.horiz_layer_number = layer[self.horiz_layer_name]
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self.vert_layer_number = layer[self.vert_layer_name]
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(self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_supply_layer_width_space(1)
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(self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_supply_layer_width_space(0)
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# For supplies, we will make the wire wider than the vias
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self.vert_layer_minwidth = max(self.vert_layer_minwidth, max_via_size)
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self.horiz_layer_minwidth = max(self.horiz_layer_minwidth, max_via_size)
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@ -44,13 +53,6 @@ class router_tech:
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self.horiz_track_width = self.horiz_layer_minwidth + self.horiz_layer_spacing
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self.vert_track_width = self.vert_layer_minwidth + self.vert_layer_spacing
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else:
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(self.vert_layer_minwidth, self.vert_layer_spacing) = self.get_layer_width_space(1)
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(self.horiz_layer_minwidth, self.horiz_layer_spacing) = self.get_layer_width_space(0)
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self.horiz_track_width = max_via_size + self.horiz_layer_spacing
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self.vert_track_width = max_via_size + self.vert_layer_spacing
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# We'll keep horizontal and vertical tracks the same for simplicity.
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self.track_width = max(self.horiz_track_width,self.vert_track_width)
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debug.info(1,"Track width: {:.3f}".format(self.track_width))
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@ -80,24 +82,6 @@ class router_tech:
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else:
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debug.error("Invalid zindex {}".format(zindex),-1)
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def get_layer_width_space(self, zindex, width=0, length=0):
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"""
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Return the width and spacing of a given layer
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and wire of a given width and length.
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"""
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if zindex==1:
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layer_name = self.vert_layer_name
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elif zindex==0:
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layer_name = self.horiz_layer_name
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else:
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debug.error("Invalid zindex for track", -1)
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min_width = drc("minwidth_{0}".format(layer_name), width, length)
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min_spacing = drc(str(layer_name)+"_to_"+str(layer_name), width, length)
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return (min_width,min_spacing)
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def get_supply_layer_width_space(self, zindex):
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"""
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These are the width and spacing of a supply layer given a supply rail
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@ -20,7 +20,7 @@ from datetime import datetime
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import grid
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import grid_utils
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class supply_router(router):
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class supply_grid_router(router):
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"""
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A router class to read an obstruction map from a gds and
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routes a grid to connect the supply on the two layers.
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@ -391,7 +391,7 @@ class supply_router(router):
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# Add the single component of the pin as the source
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# which unmarks it as a blockage too
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self.add_pin_component_source(pin_name,index)
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self.add_pin_component_source(pin_name, index)
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# Add all of the rails as targets
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# Don't add the other pins, but we could?
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@ -0,0 +1,176 @@
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# See LICENSE for licensing information.
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#
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#Copyright (c) 2016-2019 Regents of the University of California and The Board
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#of Regents for the Oklahoma Agricultural and Mechanical College
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#(acting for and on behalf of Oklahoma State University)
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#All rights reserved.
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#
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import gdsMill
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import tech
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import math
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import debug
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from globals import OPTS,print_time
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from contact import contact
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from pin_group import pin_group
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from pin_layout import pin_layout
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from vector3d import vector3d
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from router import router
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from direction import direction
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from datetime import datetime
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import grid
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import grid_utils
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class supply_tree_router(router):
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"""
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A router class to read an obstruction map from a gds and
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routes a grid to connect the supply on the two layers.
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"""
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def __init__(self, layers, design, gds_filename=None):
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"""
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This will route on layers in design. It will get the blockages from
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either the gds file name or the design itself (by saving to a gds file).
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"""
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# Power rail width in minimum wire widths
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self.rail_track_width = 3
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router.__init__(self, layers, design, gds_filename, self.rail_track_width)
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def create_routing_grid(self):
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"""
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Create a sprase routing grid with A* expansion functions.
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"""
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size = self.ur - self.ll
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debug.info(1,"Size: {0} x {1}".format(size.x,size.y))
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import supply_grid
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self.rg = supply_grid.supply_grid(self.ll, self.ur, self.track_width)
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def route(self, vdd_name="vdd", gnd_name="gnd"):
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"""
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Route the two nets in a single layer)
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"""
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debug.info(1,"Running supply router on {0} and {1}...".format(vdd_name, gnd_name))
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self.vdd_name = vdd_name
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self.gnd_name = gnd_name
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# Clear the pins if we have previously routed
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if (hasattr(self,'rg')):
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self.clear_pins()
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else:
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# Creat a routing grid over the entire area
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# FIXME: This could be created only over the routing region,
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# but this is simplest for now.
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self.create_routing_grid()
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# Get the pin shapes
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start_time = datetime.now()
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self.find_pins_and_blockages([self.vdd_name, self.gnd_name])
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print_time("Finding pins and blockages",datetime.now(), start_time, 3)
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# Add the supply rails in a mesh network and connect H/V with vias
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start_time = datetime.now()
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# Block everything
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self.prepare_blockages(self.gnd_name)
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self.prepare_blockages(self.vdd_name)
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# Route the supply pins to the supply rails
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# Route vdd first since we want it to be shorter
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start_time = datetime.now()
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self.route_pins(vdd_name)
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self.route_pins(gnd_name)
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print_time("Maze routing supplies",datetime.now(), start_time, 3)
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#self.write_debug_gds("final.gds",False)
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# Did we route everything??
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if not self.check_all_routed(vdd_name):
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return False
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if not self.check_all_routed(gnd_name):
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return False
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return True
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def check_all_routed(self, pin_name):
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"""
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Check that all pin groups are routed.
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"""
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for pg in self.pin_groups[pin_name]:
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if not pg.is_routed():
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return False
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def prepare_blockages(self, pin_name):
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"""
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Reset and add all of the blockages in the design.
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Names is a list of pins to add as a blockage.
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"""
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debug.info(3,"Preparing blockages.")
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# Start fresh. Not the best for run-time, but simpler.
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self.clear_blockages()
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# This adds the initial blockges of the design
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#print("BLOCKING:",self.blocked_grids)
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self.set_blockages(self.blocked_grids,True)
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# Block all of the pin components (some will be unblocked if they're a source/target)
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# Also block the previous routes
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for name in self.pin_groups:
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blockage_grids = {y for x in self.pin_groups[name] for y in x.grids}
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self.set_blockages(blockage_grids,True)
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blockage_grids = {y for x in self.pin_groups[name] for y in x.blockages}
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self.set_blockages(blockage_grids,True)
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# FIXME: These duplicate a bit of work
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# These are the paths that have already been routed.
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self.set_blockages(self.path_blockages)
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# Don't mark the other components as targets since we want to route
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# directly to a rail, but unblock all the source components so we can
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# route over them
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blockage_grids = {y for x in self.pin_groups[pin_name] for y in x.grids}
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self.set_blockages(blockage_grids,False)
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def route_pins(self, pin_name):
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"""
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This will route each of the remaining pin components to the other pins.
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After it is done, the cells are added to the pin blockage list.
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"""
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remaining_components = sum(not x.is_routed() for x in self.pin_groups[pin_name])
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debug.info(1,"Maze routing {0} with {1} pin components to connect.".format(pin_name,
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remaining_components))
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for index,pg in enumerate(self.pin_groups[pin_name]):
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if pg.is_routed():
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continue
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debug.info(3,"Routing component {0} {1}".format(pin_name, index))
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# Clear everything in the routing grid.
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self.rg.reinit()
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# This is inefficient since it is non-incremental, but it was
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# easier to debug.
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self.prepare_blockages(pin_name)
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# Add the single component of the pin as the source
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# which unmarks it as a blockage too
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self.add_pin_component_source(pin_name,index)
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# Marks all pin components except index as target
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self.add_pin_component_target_except(pin_name,index)
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# Actually run the A* router
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if not self.run_router(detour_scale=5):
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self.write_debug_gds("debug_route.gds",False)
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#if index==3 and pin_name=="vdd":
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# self.write_debug_gds("route.gds",False)
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@ -134,14 +134,22 @@ class sram_base(design, verilog, lef):
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for inst in self.insts:
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self.copy_power_pins(inst,"vdd")
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self.copy_power_pins(inst,"gnd")
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# Do not route the power supply
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import tech
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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return
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from supply_router import supply_router as router
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layer_stack =("metal3","via3","metal4")
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rtr=router(layer_stack, self)
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elif "metal4" in tech.layer:
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# Route a M3/M4 grid
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from supply_grid_router import supply_grid_router as router
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rtr=router(("metal3","via3","metal4"), self)
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elif "metal3" in tech.layer:
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from supply_tree_router import supply_tree_router as router
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rtr=router(("metal3",), self)
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rtr.route()
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