mirror of https://github.com/VLSIDA/OpenRAM.git
Add back scn3me_subm tech files
This commit is contained in:
Matt Guthaus
parent
0f03553689
commit
c24879162a
|
|
@ -8,7 +8,7 @@
|
|||
import hierarchy_design
|
||||
import debug
|
||||
import utils
|
||||
from tech import drc
|
||||
from tech import drc,layer
|
||||
from vector import vector
|
||||
|
||||
|
||||
|
|
@ -196,5 +196,8 @@ active = factory.create(module_type="contact", layer_stack=("active", "contact",
|
|||
poly = factory.create(module_type="contact", layer_stack=("poly", "contact", "metal1"), directions=("V","H"))
|
||||
m1m2 = factory.create(module_type="contact", layer_stack=("metal1", "via1", "metal2"), directions=("H","V"))
|
||||
m2m3 = factory.create(module_type="contact", layer_stack=("metal2", "via2", "metal3"), directions=("V","H"))
|
||||
m3m4 = factory.create(module_type="contact", layer_stack=("metal3", "via3", "metal4"), directions=("H","V"))
|
||||
if "metal4" in layer.keys():
|
||||
m3m4 = factory.create(module_type="contact", layer_stack=("metal3", "via3", "metal4"), directions=("H","V"))
|
||||
else:
|
||||
m3m4 = None
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,22 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
#
|
||||
word_size = 1
|
||||
num_words = 16
|
||||
|
||||
tech_name = "scn3me_subm"
|
||||
process_corners = ["TT"]
|
||||
supply_voltages = [5.0]
|
||||
temperatures = [25]
|
||||
|
||||
route_supplies = True
|
||||
check_lvsdrc = True
|
||||
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
#
|
||||
word_size = 1
|
||||
num_words = 16
|
||||
|
||||
tech_name = "scn3me_subm"
|
||||
process_corners = ["TT"]
|
||||
supply_voltages = [5.0]
|
||||
temperatures = [25]
|
||||
|
||||
route_supplies = True
|
||||
check_lvsdrc = True
|
||||
inline_lvsdrc = True
|
||||
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
#
|
||||
word_size = 1
|
||||
num_words = 16
|
||||
|
||||
tech_name = "scn3me_subm"
|
||||
process_corners = ["TT"]
|
||||
supply_voltages = [5.0]
|
||||
temperatures = [25]
|
||||
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
# See LICENSE for licensing information.
|
||||
#
|
||||
#Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
#of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
#(acting for and on behalf of Oklahoma State University)
|
||||
#All rights reserved.
|
||||
#
|
||||
#!/usr/bin/python
|
||||
"""
|
||||
This type of setup script should be placed in the setup_scripts directory in the trunk
|
||||
"""
|
||||
|
||||
import sys
|
||||
import os
|
||||
|
||||
TECHNOLOGY = "scn3me_subm"
|
||||
|
||||
|
||||
##########################
|
||||
# CDK paths
|
||||
|
||||
# os.environ["CDK_DIR"] = CDK_DIR #PDK path
|
||||
# os.environ["SYSTEM_CDS_LIB_DIR"] = "{0}/cdssetup".format(CDK_DIR)
|
||||
# os.environ["CDS_SITE"] = CDK_DIR
|
||||
os.environ["MGC_TMPDIR"] = "/tmp"
|
||||
|
||||
###########################
|
||||
# OpenRAM Paths
|
||||
|
||||
|
||||
try:
|
||||
DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME"))
|
||||
except:
|
||||
OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
|
||||
DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech"
|
||||
os.environ["DRCLVS_HOME"] = DRCLVS_HOME
|
||||
|
||||
# try:
|
||||
# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
|
||||
# except:
|
||||
OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
|
||||
os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY)
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,5 @@
|
|||
path sys +$::env(OPENRAM_TECH)/scn3me_subm/tech
|
||||
tech load SCN3ME_SUBM.30 -noprompt
|
||||
scalegrid 1 4
|
||||
set GND gnd
|
||||
set VDD vdd
|
||||
Binary file not shown.
|
|
@ -0,0 +1,142 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1542220294
|
||||
<< nwell >>
|
||||
rect 0 46 54 75
|
||||
<< pwell >>
|
||||
rect 0 0 54 46
|
||||
<< ntransistor >>
|
||||
rect 14 33 16 37
|
||||
rect 22 29 24 37
|
||||
rect 30 29 32 37
|
||||
rect 38 33 40 37
|
||||
rect 14 17 16 23
|
||||
rect 22 17 24 23
|
||||
rect 30 17 32 23
|
||||
rect 38 17 40 23
|
||||
<< ptransistor >>
|
||||
rect 22 54 24 57
|
||||
rect 30 54 32 57
|
||||
<< ndiffusion >>
|
||||
rect 13 33 14 37
|
||||
rect 16 33 17 37
|
||||
rect 21 33 22 37
|
||||
rect 17 29 22 33
|
||||
rect 24 29 25 37
|
||||
rect 29 29 30 37
|
||||
rect 32 33 33 37
|
||||
rect 37 33 38 37
|
||||
rect 40 33 41 37
|
||||
rect 32 29 37 33
|
||||
rect 9 21 14 23
|
||||
rect 13 17 14 21
|
||||
rect 16 17 22 23
|
||||
rect 24 17 25 23
|
||||
rect 29 17 30 23
|
||||
rect 32 17 38 23
|
||||
rect 40 21 45 23
|
||||
rect 40 17 41 21
|
||||
<< pdiffusion >>
|
||||
rect 21 54 22 57
|
||||
rect 24 54 25 57
|
||||
rect 29 54 30 57
|
||||
rect 32 54 33 57
|
||||
<< ndcontact >>
|
||||
rect 9 33 13 37
|
||||
rect 17 33 21 37
|
||||
rect 25 29 29 37
|
||||
rect 33 33 37 37
|
||||
rect 41 33 45 37
|
||||
rect 25 17 29 23
|
||||
<< pdcontact >>
|
||||
rect 17 54 21 58
|
||||
rect 33 54 37 58
|
||||
<< psubstratepcontact >>
|
||||
rect 25 9 29 13
|
||||
<< polysilicon >>
|
||||
rect 22 57 24 60
|
||||
rect 30 57 32 60
|
||||
rect 22 44 24 54
|
||||
rect 30 51 32 54
|
||||
rect 31 47 32 51
|
||||
rect 14 37 16 44
|
||||
rect 22 40 23 44
|
||||
rect 22 37 24 40
|
||||
rect 30 37 32 47
|
||||
rect 38 37 40 44
|
||||
rect 14 31 16 33
|
||||
rect 38 31 40 33
|
||||
rect 14 23 16 24
|
||||
rect 22 23 24 29
|
||||
rect 30 23 32 29
|
||||
rect 38 23 40 24
|
||||
rect 14 15 16 17
|
||||
rect 22 15 24 17
|
||||
rect 30 15 32 17
|
||||
rect 38 15 40 17
|
||||
<< polycontact >>
|
||||
rect 27 47 31 51
|
||||
rect 10 40 14 44
|
||||
rect 23 40 27 44
|
||||
rect 40 40 44 44
|
||||
rect 12 24 16 28
|
||||
rect 38 24 42 28
|
||||
<< metal1 >>
|
||||
rect 0 68 25 72
|
||||
rect 29 68 54 72
|
||||
rect 0 61 54 65
|
||||
rect 10 44 14 61
|
||||
rect 17 51 20 54
|
||||
rect 17 47 27 51
|
||||
rect 17 37 20 47
|
||||
rect 34 44 37 54
|
||||
rect 27 40 37 44
|
||||
rect 40 44 44 61
|
||||
rect 34 37 37 40
|
||||
rect 6 33 9 37
|
||||
rect 45 33 48 37
|
||||
rect 25 23 29 29
|
||||
rect 25 13 29 17
|
||||
rect 0 9 25 13
|
||||
rect 29 9 54 13
|
||||
rect 0 2 16 6
|
||||
rect 20 2 34 6
|
||||
rect 38 2 54 6
|
||||
<< m2contact >>
|
||||
rect 2 33 6 37
|
||||
rect 48 33 52 37
|
||||
rect 16 24 20 28
|
||||
rect 34 24 38 28
|
||||
rect 16 2 20 6
|
||||
rect 34 2 38 6
|
||||
<< pdm12contact >>
|
||||
rect 25 54 29 58
|
||||
<< ndm12contact >>
|
||||
rect 9 17 13 21
|
||||
rect 41 17 45 21
|
||||
<< nsm12contact >>
|
||||
rect 25 68 29 72
|
||||
<< metal2 >>
|
||||
rect 2 37 6 72
|
||||
rect 2 0 6 33
|
||||
rect 9 21 13 72
|
||||
rect 25 58 29 68
|
||||
rect 9 0 13 17
|
||||
rect 16 6 20 24
|
||||
rect 34 6 38 24
|
||||
rect 41 21 45 72
|
||||
rect 41 0 45 17
|
||||
rect 48 37 52 72
|
||||
rect 48 0 52 33
|
||||
<< comment >>
|
||||
rect 0 0 54 70
|
||||
<< labels >>
|
||||
rlabel metal1 19 63 19 63 1 wl0
|
||||
rlabel metal1 19 70 19 70 5 vdd
|
||||
rlabel metal1 27 4 27 4 1 wl1
|
||||
rlabel psubstratepcontact 27 11 27 11 1 gnd
|
||||
rlabel metal2 4 7 4 7 2 bl0
|
||||
rlabel metal2 11 7 11 7 1 bl1
|
||||
rlabel metal2 43 7 43 7 1 br1
|
||||
rlabel metal2 50 7 50 7 8 br0
|
||||
<< end >>
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1536091415
|
||||
<< nwell >>
|
||||
rect -8 29 42 51
|
||||
<< pwell >>
|
||||
rect -8 -8 42 29
|
||||
<< ntransistor >>
|
||||
rect 7 10 9 18
|
||||
rect 29 10 31 18
|
||||
rect 10 3 14 5
|
||||
rect 24 3 28 5
|
||||
<< ptransistor >>
|
||||
rect 7 37 11 40
|
||||
rect 27 37 31 40
|
||||
<< ndiffusion >>
|
||||
rect -2 16 7 18
|
||||
rect 2 12 7 16
|
||||
rect -2 10 7 12
|
||||
rect 9 14 10 18
|
||||
rect 9 10 14 14
|
||||
rect 28 14 29 18
|
||||
rect 24 10 29 14
|
||||
rect 31 16 36 18
|
||||
rect 31 12 32 16
|
||||
rect 31 10 36 12
|
||||
rect 10 5 14 10
|
||||
rect 24 5 28 10
|
||||
rect 10 2 14 3
|
||||
rect 24 2 28 3
|
||||
<< pdiffusion >>
|
||||
rect 2 37 7 40
|
||||
rect 11 37 12 40
|
||||
rect 26 37 27 40
|
||||
rect 31 37 32 40
|
||||
<< ndcontact >>
|
||||
rect -2 12 2 16
|
||||
rect 10 14 14 18
|
||||
rect 24 14 28 18
|
||||
rect 32 12 36 16
|
||||
rect 10 -2 14 2
|
||||
rect 24 -2 28 2
|
||||
<< pdcontact >>
|
||||
rect -2 36 2 40
|
||||
rect 12 36 16 40
|
||||
rect 22 36 26 40
|
||||
rect 32 36 36 40
|
||||
<< psubstratepcontact >>
|
||||
rect -2 22 2 26
|
||||
rect 32 22 36 26
|
||||
<< nsubstratencontact >>
|
||||
rect 32 44 36 48
|
||||
<< polysilicon >>
|
||||
rect 7 40 11 42
|
||||
rect 27 40 31 42
|
||||
rect 7 35 11 37
|
||||
rect 7 21 9 35
|
||||
rect 27 34 31 37
|
||||
rect 15 33 31 34
|
||||
rect 19 32 31 33
|
||||
rect 7 20 21 21
|
||||
rect 7 19 24 20
|
||||
rect 7 18 9 19
|
||||
rect 29 18 31 32
|
||||
rect 7 8 9 10
|
||||
rect 17 5 21 6
|
||||
rect 29 8 31 10
|
||||
rect -2 3 10 5
|
||||
rect 14 3 24 5
|
||||
rect 28 3 36 5
|
||||
<< polycontact >>
|
||||
rect 15 29 19 33
|
||||
rect 21 20 25 24
|
||||
rect 17 6 21 10
|
||||
<< metal1 >>
|
||||
rect -2 44 15 48
|
||||
rect 19 44 32 48
|
||||
rect -2 40 2 44
|
||||
rect 32 40 36 44
|
||||
rect 11 36 12 40
|
||||
rect 26 36 27 40
|
||||
rect -2 26 2 29
|
||||
rect -2 16 2 22
|
||||
rect 11 18 15 36
|
||||
rect 23 24 27 36
|
||||
rect 25 20 27 24
|
||||
rect 14 14 15 18
|
||||
rect 23 18 27 20
|
||||
rect 32 26 36 29
|
||||
rect 23 14 24 18
|
||||
rect 32 16 36 22
|
||||
rect -2 6 17 9
|
||||
rect 21 6 36 9
|
||||
rect -2 5 36 6
|
||||
<< m2contact >>
|
||||
rect 15 44 19 48
|
||||
rect -2 29 2 33
|
||||
rect 32 29 36 33
|
||||
rect 6 -2 10 2
|
||||
rect 20 -2 24 2
|
||||
<< metal2 >>
|
||||
rect -2 33 2 48
|
||||
rect -2 -2 2 29
|
||||
rect 6 2 10 48
|
||||
rect 24 -2 28 48
|
||||
rect 32 33 36 48
|
||||
rect 32 -2 36 29
|
||||
<< bb >>
|
||||
rect 0 0 34 46
|
||||
<< labels >>
|
||||
rlabel metal2 0 0 0 0 1 gnd
|
||||
rlabel metal2 34 0 34 0 1 gnd
|
||||
rlabel m2contact 17 46 17 46 5 vdd
|
||||
rlabel metal2 8 43 8 43 1 bl
|
||||
rlabel metal2 26 43 26 43 1 br
|
||||
rlabel metal1 4 7 4 7 1 wl
|
||||
<< end >>
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
magic -dnull -noconsole << EOF
|
||||
load dff
|
||||
gds write dff.gds
|
||||
load cell_6t
|
||||
gds write cell_6t.gds
|
||||
load replica_cell_6t
|
||||
gds write replica_cell_6t.gds
|
||||
load sense_amp
|
||||
gds write sense_amp.gds
|
||||
load tri_gate
|
||||
gds write tri_gate.gds
|
||||
load write_driver
|
||||
gds write write_driver.gds
|
||||
EOF
|
||||
|
|
@ -0,0 +1,279 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1536089597
|
||||
<< nwell >>
|
||||
rect 0 48 109 103
|
||||
<< pwell >>
|
||||
rect 0 -3 109 48
|
||||
<< ntransistor >>
|
||||
rect 11 6 13 26
|
||||
rect 19 6 21 16
|
||||
rect 24 6 26 16
|
||||
rect 33 6 35 16
|
||||
rect 38 6 40 16
|
||||
rect 47 6 49 16
|
||||
rect 63 6 65 16
|
||||
rect 68 6 70 16
|
||||
rect 78 6 80 16
|
||||
rect 83 6 85 16
|
||||
rect 91 6 93 26
|
||||
<< ptransistor >>
|
||||
rect 11 54 13 94
|
||||
rect 19 74 21 94
|
||||
rect 25 74 27 94
|
||||
rect 33 74 35 94
|
||||
rect 39 74 41 94
|
||||
rect 47 74 49 94
|
||||
rect 63 74 65 94
|
||||
rect 68 74 70 94
|
||||
rect 78 84 80 94
|
||||
rect 83 84 85 94
|
||||
rect 91 54 93 94
|
||||
<< ndiffusion >>
|
||||
rect 6 25 11 26
|
||||
rect 10 6 11 25
|
||||
rect 13 25 18 26
|
||||
rect 13 6 14 25
|
||||
rect 86 25 91 26
|
||||
rect 18 6 19 16
|
||||
rect 21 6 24 16
|
||||
rect 26 15 33 16
|
||||
rect 26 6 28 15
|
||||
rect 32 6 33 15
|
||||
rect 35 6 38 16
|
||||
rect 40 15 47 16
|
||||
rect 40 6 41 15
|
||||
rect 45 6 47 15
|
||||
rect 49 15 54 16
|
||||
rect 49 6 50 15
|
||||
rect 58 15 63 16
|
||||
rect 62 6 63 15
|
||||
rect 65 6 68 16
|
||||
rect 70 15 78 16
|
||||
rect 70 6 72 15
|
||||
rect 76 6 78 15
|
||||
rect 80 6 83 16
|
||||
rect 85 6 86 16
|
||||
rect 90 6 91 25
|
||||
rect 93 25 98 26
|
||||
rect 93 6 94 25
|
||||
<< pdiffusion >>
|
||||
rect 6 93 11 94
|
||||
rect 10 54 11 93
|
||||
rect 13 55 14 94
|
||||
rect 18 74 19 94
|
||||
rect 21 74 25 94
|
||||
rect 27 93 33 94
|
||||
rect 27 74 28 93
|
||||
rect 32 74 33 93
|
||||
rect 35 74 39 94
|
||||
rect 41 93 47 94
|
||||
rect 41 74 42 93
|
||||
rect 46 74 47 93
|
||||
rect 49 93 54 94
|
||||
rect 49 74 50 93
|
||||
rect 58 93 63 94
|
||||
rect 62 74 63 93
|
||||
rect 65 74 68 94
|
||||
rect 70 93 78 94
|
||||
rect 70 74 72 93
|
||||
rect 76 84 78 93
|
||||
rect 80 84 83 94
|
||||
rect 85 93 91 94
|
||||
rect 85 84 86 93
|
||||
rect 76 74 77 84
|
||||
rect 13 54 18 55
|
||||
rect 90 54 91 93
|
||||
rect 93 93 98 94
|
||||
rect 93 54 94 93
|
||||
<< ndcontact >>
|
||||
rect 6 6 10 25
|
||||
rect 14 6 18 25
|
||||
rect 28 6 32 15
|
||||
rect 41 6 45 15
|
||||
rect 50 6 54 15
|
||||
rect 58 6 62 15
|
||||
rect 72 6 76 15
|
||||
rect 86 6 90 25
|
||||
rect 94 6 98 25
|
||||
<< pdcontact >>
|
||||
rect 6 54 10 93
|
||||
rect 14 55 18 94
|
||||
rect 28 74 32 93
|
||||
rect 42 74 46 93
|
||||
rect 50 74 54 93
|
||||
rect 58 74 62 93
|
||||
rect 72 74 76 93
|
||||
rect 86 54 90 93
|
||||
rect 94 54 98 93
|
||||
<< psubstratepcontact >>
|
||||
rect 102 6 106 10
|
||||
<< nsubstratencontact >>
|
||||
rect 102 89 106 93
|
||||
<< polysilicon >>
|
||||
rect 11 94 13 96
|
||||
rect 19 94 21 96
|
||||
rect 25 94 27 96
|
||||
rect 33 94 35 96
|
||||
rect 39 94 41 96
|
||||
rect 47 94 49 96
|
||||
rect 63 94 65 96
|
||||
rect 68 94 70 96
|
||||
rect 78 94 80 96
|
||||
rect 83 94 85 96
|
||||
rect 91 94 93 96
|
||||
rect 11 37 13 54
|
||||
rect 19 46 21 74
|
||||
rect 11 26 13 33
|
||||
rect 19 16 21 42
|
||||
rect 25 38 27 74
|
||||
rect 33 54 35 74
|
||||
rect 33 29 35 50
|
||||
rect 24 27 35 29
|
||||
rect 39 71 41 74
|
||||
rect 24 16 26 27
|
||||
rect 39 23 41 67
|
||||
rect 47 61 49 74
|
||||
rect 63 73 65 74
|
||||
rect 54 71 65 73
|
||||
rect 34 19 35 23
|
||||
rect 33 16 35 19
|
||||
rect 38 19 39 23
|
||||
rect 38 16 40 19
|
||||
rect 47 16 49 57
|
||||
rect 53 19 55 67
|
||||
rect 68 63 70 74
|
||||
rect 78 67 80 84
|
||||
rect 76 65 80 67
|
||||
rect 63 61 70 63
|
||||
rect 61 24 63 33
|
||||
rect 68 31 70 61
|
||||
rect 83 53 85 84
|
||||
rect 79 51 85 53
|
||||
rect 78 31 80 47
|
||||
rect 91 45 93 54
|
||||
rect 89 41 93 45
|
||||
rect 68 29 75 31
|
||||
rect 61 22 70 24
|
||||
rect 53 17 65 19
|
||||
rect 63 16 65 17
|
||||
rect 68 16 70 22
|
||||
rect 73 19 75 29
|
||||
rect 78 27 79 31
|
||||
rect 73 17 80 19
|
||||
rect 78 16 80 17
|
||||
rect 83 16 85 31
|
||||
rect 91 26 93 41
|
||||
rect 11 4 13 6
|
||||
rect 19 4 21 6
|
||||
rect 24 4 26 6
|
||||
rect 33 4 35 6
|
||||
rect 38 4 40 6
|
||||
rect 47 4 49 6
|
||||
rect 63 4 65 6
|
||||
rect 68 4 70 6
|
||||
rect 78 4 80 6
|
||||
rect 83 4 85 6
|
||||
rect 91 4 93 6
|
||||
<< polycontact >>
|
||||
rect 17 42 21 46
|
||||
rect 10 33 14 37
|
||||
rect 31 50 35 54
|
||||
rect 25 34 29 38
|
||||
rect 39 67 43 71
|
||||
rect 45 57 49 61
|
||||
rect 30 19 34 23
|
||||
rect 39 19 43 23
|
||||
rect 53 67 57 71
|
||||
rect 59 59 63 63
|
||||
rect 74 61 78 65
|
||||
rect 59 33 63 37
|
||||
rect 77 47 81 51
|
||||
rect 85 41 89 45
|
||||
rect 79 27 83 31
|
||||
<< metal1 >>
|
||||
rect 0 97 109 103
|
||||
rect 14 94 18 97
|
||||
rect 6 93 10 94
|
||||
rect 28 93 32 94
|
||||
rect 22 74 28 77
|
||||
rect 42 93 46 97
|
||||
rect 50 93 54 94
|
||||
rect 58 93 62 97
|
||||
rect 71 93 77 94
|
||||
rect 71 74 72 93
|
||||
rect 76 74 77 93
|
||||
rect 86 93 90 97
|
||||
rect 50 71 53 74
|
||||
rect 43 68 53 71
|
||||
rect 26 57 45 60
|
||||
rect 52 60 59 63
|
||||
rect 52 54 55 60
|
||||
rect 71 56 74 65
|
||||
rect 10 50 31 52
|
||||
rect 35 51 55 54
|
||||
rect 62 53 74 56
|
||||
rect 94 93 98 94
|
||||
rect 102 93 106 97
|
||||
rect 6 49 34 50
|
||||
rect 21 43 38 46
|
||||
rect 18 34 25 37
|
||||
rect 62 37 65 53
|
||||
rect 94 51 98 54
|
||||
rect 81 48 94 51
|
||||
rect 74 41 85 44
|
||||
rect 29 34 59 37
|
||||
rect 6 25 10 26
|
||||
rect 14 25 18 26
|
||||
rect 31 23 34 34
|
||||
rect 63 34 65 37
|
||||
rect 94 31 98 47
|
||||
rect 83 28 98 31
|
||||
rect 94 25 98 28
|
||||
rect 43 19 53 22
|
||||
rect 50 16 53 19
|
||||
rect 22 15 32 16
|
||||
rect 22 13 28 15
|
||||
rect 41 15 46 16
|
||||
rect 45 6 46 15
|
||||
rect 50 15 54 16
|
||||
rect 58 15 62 16
|
||||
rect 70 15 77 16
|
||||
rect 70 13 72 15
|
||||
rect 71 6 72 13
|
||||
rect 76 6 77 15
|
||||
rect 14 3 18 6
|
||||
rect 41 3 46 6
|
||||
rect 58 3 62 6
|
||||
rect 86 3 90 6
|
||||
rect 102 3 106 6
|
||||
rect 0 -3 109 3
|
||||
<< m2contact >>
|
||||
rect 22 70 26 74
|
||||
rect 70 70 74 74
|
||||
rect 22 57 26 61
|
||||
rect 6 50 10 54
|
||||
rect 38 43 42 47
|
||||
rect 14 33 18 37
|
||||
rect 94 47 98 51
|
||||
rect 70 40 74 44
|
||||
rect 6 26 10 30
|
||||
rect 22 16 26 20
|
||||
rect 70 16 74 20
|
||||
<< metal2 >>
|
||||
rect 22 61 26 70
|
||||
rect 6 30 10 50
|
||||
rect 22 20 26 57
|
||||
rect 70 44 74 70
|
||||
rect 70 20 74 40
|
||||
<< bb >>
|
||||
rect 0 0 109 100
|
||||
<< labels >>
|
||||
rlabel m2contact 15 34 15 34 4 clk
|
||||
rlabel m2contact 40 45 40 45 4 D
|
||||
rlabel m2contact 96 49 96 49 4 Q
|
||||
rlabel metal1 32 98 32 98 4 vdd
|
||||
rlabel metal1 44 1 44 1 4 gnd
|
||||
<< properties >>
|
||||
string path 0.000 0.000 900.000 0.000 900.000 900.000 0.000 900.000 0.000 0.000
|
||||
<< end >>
|
||||
|
|
@ -0,0 +1,294 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1536089622
|
||||
<< nwell >>
|
||||
rect -2 0 18 200
|
||||
<< pwell >>
|
||||
rect 18 0 40 200
|
||||
<< ntransistor >>
|
||||
rect 24 178 27 180
|
||||
rect 24 162 27 164
|
||||
rect 24 138 27 140
|
||||
rect 24 130 27 132
|
||||
rect 24 112 27 114
|
||||
rect 24 93 27 95
|
||||
rect 24 77 27 79
|
||||
rect 24 50 27 52
|
||||
rect 24 42 27 44
|
||||
rect 24 24 27 26
|
||||
<< ptransistor >>
|
||||
rect 6 178 12 180
|
||||
rect 6 162 12 164
|
||||
rect 6 138 12 140
|
||||
rect 6 130 12 132
|
||||
rect 6 112 12 114
|
||||
rect 6 93 12 95
|
||||
rect 6 77 12 79
|
||||
rect 6 50 12 52
|
||||
rect 6 42 12 44
|
||||
rect 6 24 12 26
|
||||
<< ndiffusion >>
|
||||
rect 24 180 27 181
|
||||
rect 24 177 27 178
|
||||
rect 24 164 27 165
|
||||
rect 24 161 27 162
|
||||
rect 28 157 32 161
|
||||
rect 24 140 27 141
|
||||
rect 24 137 27 138
|
||||
rect 24 132 27 133
|
||||
rect 24 129 27 130
|
||||
rect 24 114 27 115
|
||||
rect 24 111 27 112
|
||||
rect 24 95 27 96
|
||||
rect 24 92 27 93
|
||||
rect 24 79 27 80
|
||||
rect 24 76 27 77
|
||||
rect 28 72 32 76
|
||||
rect 24 52 27 53
|
||||
rect 24 49 27 50
|
||||
rect 24 44 27 45
|
||||
rect 24 41 27 42
|
||||
rect 24 26 27 27
|
||||
rect 24 23 27 24
|
||||
<< pdiffusion >>
|
||||
rect 6 180 12 181
|
||||
rect 6 177 12 178
|
||||
rect 6 164 12 165
|
||||
rect 6 161 12 162
|
||||
rect 6 140 12 141
|
||||
rect 6 137 12 138
|
||||
rect 6 132 12 133
|
||||
rect 6 129 12 130
|
||||
rect 6 114 12 115
|
||||
rect 6 111 12 112
|
||||
rect 6 95 12 96
|
||||
rect 6 92 12 93
|
||||
rect 6 79 12 80
|
||||
rect 6 76 12 77
|
||||
rect 6 52 12 53
|
||||
rect 6 49 12 50
|
||||
rect 6 44 12 45
|
||||
rect 6 41 12 42
|
||||
rect 6 26 12 27
|
||||
rect 6 23 12 24
|
||||
rect 8 18 12 19
|
||||
<< ndcontact >>
|
||||
rect 24 181 28 185
|
||||
rect 24 173 28 177
|
||||
rect 24 165 28 169
|
||||
rect 24 157 28 161
|
||||
rect 24 141 28 145
|
||||
rect 24 133 28 137
|
||||
rect 24 125 28 129
|
||||
rect 24 115 28 119
|
||||
rect 24 107 28 111
|
||||
rect 24 96 28 100
|
||||
rect 24 88 28 92
|
||||
rect 24 80 28 84
|
||||
rect 24 72 28 76
|
||||
rect 24 53 28 57
|
||||
rect 24 45 28 49
|
||||
rect 24 37 28 41
|
||||
rect 24 27 28 31
|
||||
rect 24 19 28 23
|
||||
<< pdcontact >>
|
||||
rect 6 181 12 185
|
||||
rect 6 173 12 177
|
||||
rect 6 165 12 169
|
||||
rect 6 157 12 161
|
||||
rect 6 141 12 145
|
||||
rect 6 133 12 137
|
||||
rect 6 125 12 129
|
||||
rect 6 115 12 119
|
||||
rect 6 107 12 111
|
||||
rect 6 96 12 100
|
||||
rect 6 88 12 92
|
||||
rect 6 80 12 84
|
||||
rect 6 72 12 76
|
||||
rect 6 53 12 57
|
||||
rect 6 45 12 49
|
||||
rect 6 37 12 41
|
||||
rect 6 27 12 31
|
||||
rect 6 19 12 23
|
||||
<< psubstratepcontact >>
|
||||
rect 32 157 36 161
|
||||
rect 32 72 36 76
|
||||
<< nsubstratencontact >>
|
||||
rect 8 14 12 18
|
||||
<< polysilicon >>
|
||||
rect 4 178 6 180
|
||||
rect 12 178 24 180
|
||||
rect 27 178 29 180
|
||||
rect 17 173 19 178
|
||||
rect 4 162 6 164
|
||||
rect 12 163 24 164
|
||||
rect 12 162 17 163
|
||||
rect 21 162 24 163
|
||||
rect 27 162 29 164
|
||||
rect 3 148 13 150
|
||||
rect 3 140 5 148
|
||||
rect 3 138 6 140
|
||||
rect 12 138 14 140
|
||||
rect 17 138 24 140
|
||||
rect 27 138 29 140
|
||||
rect 17 132 19 138
|
||||
rect 3 130 6 132
|
||||
rect 12 130 19 132
|
||||
rect 22 130 24 132
|
||||
rect 27 130 31 132
|
||||
rect 3 114 5 130
|
||||
rect 29 122 31 130
|
||||
rect 20 120 31 122
|
||||
rect 3 112 6 114
|
||||
rect 12 112 24 114
|
||||
rect 27 112 29 114
|
||||
rect 4 93 6 95
|
||||
rect 12 93 24 95
|
||||
rect 27 93 29 95
|
||||
rect 19 89 21 93
|
||||
rect 4 77 6 79
|
||||
rect 12 78 24 79
|
||||
rect 12 77 17 78
|
||||
rect 21 77 24 78
|
||||
rect 27 77 29 79
|
||||
rect 3 60 13 62
|
||||
rect 3 52 5 60
|
||||
rect 3 50 6 52
|
||||
rect 12 50 14 52
|
||||
rect 17 50 24 52
|
||||
rect 27 50 29 52
|
||||
rect 17 44 19 50
|
||||
rect 3 42 6 44
|
||||
rect 12 42 19 44
|
||||
rect 22 42 24 44
|
||||
rect 27 42 31 44
|
||||
rect 3 26 5 42
|
||||
rect 29 34 31 42
|
||||
rect 20 32 31 34
|
||||
rect 3 24 6 26
|
||||
rect 12 24 24 26
|
||||
rect 27 24 29 26
|
||||
rect 16 14 18 24
|
||||
<< polycontact >>
|
||||
rect 16 169 20 173
|
||||
rect 17 159 21 163
|
||||
rect 13 148 17 152
|
||||
rect 16 118 20 122
|
||||
rect 15 108 19 112
|
||||
rect 17 85 21 89
|
||||
rect 17 74 21 78
|
||||
rect 13 60 17 64
|
||||
rect 16 30 20 34
|
||||
rect 15 10 19 14
|
||||
<< metal1 >>
|
||||
rect 16 182 24 185
|
||||
rect -2 173 6 177
|
||||
rect 28 173 36 177
|
||||
rect -2 164 2 173
|
||||
rect 12 166 20 169
|
||||
rect 2 160 6 161
|
||||
rect -2 157 6 160
|
||||
rect 33 161 36 173
|
||||
rect -2 111 2 157
|
||||
rect 28 157 32 161
|
||||
rect 12 142 24 145
|
||||
rect 12 134 20 137
|
||||
rect 12 126 20 129
|
||||
rect 20 118 24 119
|
||||
rect 16 116 24 118
|
||||
rect -2 107 6 111
|
||||
rect 33 111 36 153
|
||||
rect -2 92 2 107
|
||||
rect 28 107 36 111
|
||||
rect 12 97 24 100
|
||||
rect 33 92 36 107
|
||||
rect -2 88 6 92
|
||||
rect -2 76 2 88
|
||||
rect 28 88 36 92
|
||||
rect 6 84 20 85
|
||||
rect 12 82 20 84
|
||||
rect -2 72 6 76
|
||||
rect 33 76 36 88
|
||||
rect -2 41 2 72
|
||||
rect 28 72 32 76
|
||||
rect 12 54 24 57
|
||||
rect 12 46 20 49
|
||||
rect 12 38 20 41
|
||||
rect -2 22 2 37
|
||||
rect 20 30 24 31
|
||||
rect 16 28 24 30
|
||||
rect 33 23 36 68
|
||||
rect -2 19 6 22
|
||||
rect 28 20 36 23
|
||||
rect 8 18 12 19
|
||||
rect -2 10 15 11
|
||||
rect 19 10 36 11
|
||||
rect -2 8 36 10
|
||||
<< m2contact >>
|
||||
rect 12 181 16 185
|
||||
rect 20 166 24 170
|
||||
rect -2 160 2 164
|
||||
rect 17 155 21 159
|
||||
rect 32 153 36 157
|
||||
rect 6 145 10 149
|
||||
rect 17 148 21 152
|
||||
rect 20 133 24 137
|
||||
rect 20 125 24 129
|
||||
rect 12 115 16 119
|
||||
rect 15 104 19 108
|
||||
rect 6 100 10 104
|
||||
rect 20 81 24 85
|
||||
rect 17 70 21 74
|
||||
rect 32 68 36 72
|
||||
rect 6 57 10 61
|
||||
rect 17 60 21 64
|
||||
rect 20 45 24 49
|
||||
rect -2 37 2 41
|
||||
rect 20 37 24 41
|
||||
rect 12 27 16 31
|
||||
<< metal2 >>
|
||||
rect 6 185 10 200
|
||||
rect 15 196 19 200
|
||||
rect 15 192 24 196
|
||||
rect 6 181 12 185
|
||||
rect 6 149 9 181
|
||||
rect 20 170 24 192
|
||||
rect 21 155 27 159
|
||||
rect 18 143 21 148
|
||||
rect 13 140 21 143
|
||||
rect 13 119 16 140
|
||||
rect 24 133 27 155
|
||||
rect 5 100 6 104
|
||||
rect 5 61 8 100
|
||||
rect 15 93 19 104
|
||||
rect 11 90 19 93
|
||||
rect 11 67 14 90
|
||||
rect 24 81 27 129
|
||||
rect 21 70 27 74
|
||||
rect 11 64 16 67
|
||||
rect 5 57 6 61
|
||||
rect 13 60 17 64
|
||||
rect 13 31 16 60
|
||||
rect 24 45 27 70
|
||||
rect 24 8 27 41
|
||||
rect 19 4 27 8
|
||||
rect 15 0 19 4
|
||||
<< m3contact >>
|
||||
rect 15 4 19 8
|
||||
<< metal3 >>
|
||||
rect 14 8 20 9
|
||||
rect 14 4 15 8
|
||||
rect 19 4 20 8
|
||||
rect 14 3 20 4
|
||||
<< bb >>
|
||||
rect 0 0 34 200
|
||||
<< labels >>
|
||||
rlabel metal1 0 8 0 8 2 clk
|
||||
rlabel metal3 15 4 15 4 1 din
|
||||
rlabel metal2 6 196 6 196 5 dout_bar
|
||||
rlabel metal2 15 196 15 196 5 dout
|
||||
rlabel m2contact 34 70 34 70 1 gnd
|
||||
rlabel m2contact 34 154 34 154 1 gnd
|
||||
rlabel m2contact 0 162 0 162 3 vdd
|
||||
rlabel m2contact 0 38 0 38 3 vdd
|
||||
<< end >>
|
||||
Binary file not shown.
|
|
@ -0,0 +1,145 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1542221056
|
||||
<< nwell >>
|
||||
rect 0 46 54 75
|
||||
<< pwell >>
|
||||
rect 0 0 54 46
|
||||
<< ntransistor >>
|
||||
rect 14 33 16 37
|
||||
rect 22 29 24 37
|
||||
rect 30 29 32 37
|
||||
rect 38 33 40 37
|
||||
rect 14 17 16 23
|
||||
rect 22 17 24 23
|
||||
rect 30 17 32 23
|
||||
rect 38 17 40 23
|
||||
<< ptransistor >>
|
||||
rect 22 54 24 57
|
||||
rect 30 54 32 57
|
||||
<< ndiffusion >>
|
||||
rect 13 33 14 37
|
||||
rect 16 33 17 37
|
||||
rect 21 33 22 37
|
||||
rect 17 29 22 33
|
||||
rect 24 29 25 37
|
||||
rect 29 29 30 37
|
||||
rect 32 33 33 37
|
||||
rect 37 33 38 37
|
||||
rect 40 33 41 37
|
||||
rect 32 29 37 33
|
||||
rect 9 21 14 23
|
||||
rect 13 17 14 21
|
||||
rect 16 17 22 23
|
||||
rect 24 17 25 23
|
||||
rect 29 17 30 23
|
||||
rect 32 17 38 23
|
||||
rect 40 21 45 23
|
||||
rect 40 17 41 21
|
||||
<< pdiffusion >>
|
||||
rect 21 54 22 57
|
||||
rect 24 54 25 57
|
||||
rect 29 54 30 57
|
||||
rect 32 54 33 57
|
||||
<< ndcontact >>
|
||||
rect 9 33 13 37
|
||||
rect 17 33 21 37
|
||||
rect 25 29 29 37
|
||||
rect 33 33 37 37
|
||||
rect 41 33 45 37
|
||||
rect 9 17 13 21
|
||||
rect 25 17 29 23
|
||||
rect 41 17 45 21
|
||||
<< pdcontact >>
|
||||
rect 17 54 21 58
|
||||
rect 25 54 29 58
|
||||
rect 33 54 37 58
|
||||
<< psubstratepcontact >>
|
||||
rect 25 9 29 13
|
||||
<< nsubstratencontact >>
|
||||
rect 25 68 29 72
|
||||
<< polysilicon >>
|
||||
rect 22 57 24 60
|
||||
rect 30 57 32 60
|
||||
rect 22 44 24 54
|
||||
rect 30 51 32 54
|
||||
rect 31 47 32 51
|
||||
rect 14 37 16 44
|
||||
rect 22 40 23 44
|
||||
rect 22 37 24 40
|
||||
rect 30 37 32 47
|
||||
rect 38 37 40 44
|
||||
rect 14 31 16 33
|
||||
rect 38 31 40 33
|
||||
rect 14 23 16 24
|
||||
rect 22 23 24 29
|
||||
rect 30 23 32 29
|
||||
rect 38 23 40 24
|
||||
rect 14 15 16 17
|
||||
rect 22 15 24 17
|
||||
rect 30 15 32 17
|
||||
rect 38 15 40 17
|
||||
<< polycontact >>
|
||||
rect 27 47 31 51
|
||||
rect 10 40 14 44
|
||||
rect 23 40 27 44
|
||||
rect 40 40 44 44
|
||||
rect 12 24 16 28
|
||||
rect 38 24 42 28
|
||||
<< metal1 >>
|
||||
rect 0 68 25 72
|
||||
rect 29 68 54 72
|
||||
rect 0 61 54 65
|
||||
rect 10 44 14 61
|
||||
rect 29 54 33 58
|
||||
rect 17 51 20 54
|
||||
rect 17 47 27 51
|
||||
rect 17 37 20 47
|
||||
rect 34 44 37 54
|
||||
rect 27 40 37 44
|
||||
rect 40 44 44 61
|
||||
rect 34 37 37 40
|
||||
rect 6 33 9 37
|
||||
rect 45 33 48 37
|
||||
rect 25 23 29 29
|
||||
rect 25 13 29 17
|
||||
rect 0 9 25 13
|
||||
rect 29 9 54 13
|
||||
rect 0 2 16 6
|
||||
rect 20 2 34 6
|
||||
rect 38 2 54 6
|
||||
<< m2contact >>
|
||||
rect 25 68 29 72
|
||||
rect 25 54 29 58
|
||||
rect 2 33 6 37
|
||||
rect 48 33 52 37
|
||||
rect 16 24 20 28
|
||||
rect 34 24 38 28
|
||||
rect 9 17 13 21
|
||||
rect 41 17 45 21
|
||||
rect 16 2 20 6
|
||||
rect 34 2 38 6
|
||||
<< metal2 >>
|
||||
rect 2 37 6 72
|
||||
rect 2 0 6 33
|
||||
rect 9 21 13 72
|
||||
rect 25 58 29 68
|
||||
rect 9 0 13 17
|
||||
rect 16 6 20 24
|
||||
rect 34 6 38 24
|
||||
rect 41 21 45 72
|
||||
rect 41 0 45 17
|
||||
rect 48 37 52 72
|
||||
rect 48 0 52 33
|
||||
<< comment >>
|
||||
rect 0 0 54 70
|
||||
<< labels >>
|
||||
rlabel metal1 19 63 19 63 1 wl0
|
||||
rlabel metal1 19 70 19 70 5 vdd
|
||||
rlabel metal1 27 4 27 4 1 wl1
|
||||
rlabel psubstratepcontact 27 11 27 11 1 gnd
|
||||
rlabel metal2 4 7 4 7 2 bl0
|
||||
rlabel metal2 11 7 11 7 1 bl1
|
||||
rlabel metal2 43 7 43 7 1 br1
|
||||
rlabel metal2 50 7 50 7 8 br0
|
||||
<< end >>
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1536091380
|
||||
<< nwell >>
|
||||
rect -8 29 42 51
|
||||
<< pwell >>
|
||||
rect -8 -8 42 29
|
||||
<< ntransistor >>
|
||||
rect 7 10 9 18
|
||||
rect 29 10 31 18
|
||||
rect 10 3 14 5
|
||||
rect 24 3 28 5
|
||||
<< ptransistor >>
|
||||
rect 7 37 11 40
|
||||
rect 27 37 31 40
|
||||
<< ndiffusion >>
|
||||
rect -2 16 7 18
|
||||
rect 2 12 7 16
|
||||
rect -2 10 7 12
|
||||
rect 9 14 10 18
|
||||
rect 9 10 14 14
|
||||
rect 28 14 29 18
|
||||
rect 24 10 29 14
|
||||
rect 31 16 36 18
|
||||
rect 31 12 32 16
|
||||
rect 31 10 36 12
|
||||
rect 10 5 14 10
|
||||
rect 24 5 28 10
|
||||
rect 10 2 14 3
|
||||
rect 24 2 28 3
|
||||
<< pdiffusion >>
|
||||
rect 2 37 7 40
|
||||
rect 11 37 12 40
|
||||
rect 26 37 27 40
|
||||
rect 31 37 32 40
|
||||
<< ndcontact >>
|
||||
rect -2 12 2 16
|
||||
rect 10 14 14 18
|
||||
rect 24 14 28 18
|
||||
rect 32 12 36 16
|
||||
rect 10 -2 14 2
|
||||
rect 24 -2 28 2
|
||||
<< pdcontact >>
|
||||
rect -2 36 2 40
|
||||
rect 12 36 16 40
|
||||
rect 22 36 26 40
|
||||
rect 32 36 36 40
|
||||
<< psubstratepcontact >>
|
||||
rect -2 22 2 26
|
||||
rect 32 22 36 26
|
||||
<< nsubstratencontact >>
|
||||
rect 32 44 36 48
|
||||
<< polysilicon >>
|
||||
rect 7 40 11 42
|
||||
rect 27 40 31 42
|
||||
rect 7 35 11 37
|
||||
rect 7 21 9 35
|
||||
rect 27 34 31 37
|
||||
rect 15 33 31 34
|
||||
rect 19 32 31 33
|
||||
rect 7 20 21 21
|
||||
rect 7 19 24 20
|
||||
rect 7 18 9 19
|
||||
rect 29 18 31 32
|
||||
rect 7 8 9 10
|
||||
rect 17 5 21 6
|
||||
rect 29 8 31 10
|
||||
rect -2 3 10 5
|
||||
rect 14 3 24 5
|
||||
rect 28 3 36 5
|
||||
<< polycontact >>
|
||||
rect 15 29 19 33
|
||||
rect 21 20 25 24
|
||||
rect 17 6 21 10
|
||||
<< metal1 >>
|
||||
rect -2 44 15 48
|
||||
rect 19 44 32 48
|
||||
rect -2 40 2 44
|
||||
rect 32 40 36 44
|
||||
rect 11 36 12 40
|
||||
rect 26 36 27 40
|
||||
rect -2 26 2 29
|
||||
rect 11 22 15 36
|
||||
rect 23 24 27 36
|
||||
rect -2 18 15 22
|
||||
rect 25 20 27 24
|
||||
rect -2 16 2 18
|
||||
rect 14 14 15 18
|
||||
rect 23 18 27 20
|
||||
rect 32 26 36 29
|
||||
rect 23 14 24 18
|
||||
rect 32 16 36 22
|
||||
rect -2 6 17 9
|
||||
rect 21 6 36 9
|
||||
rect -2 5 36 6
|
||||
<< m2contact >>
|
||||
rect 15 44 19 48
|
||||
rect -2 29 2 33
|
||||
rect 32 29 36 33
|
||||
rect 6 -2 10 2
|
||||
rect 20 -2 24 2
|
||||
<< metal2 >>
|
||||
rect -2 33 2 48
|
||||
rect -2 -2 2 29
|
||||
rect 6 2 10 48
|
||||
rect 24 -2 28 48
|
||||
rect 32 33 36 48
|
||||
rect 32 -2 36 29
|
||||
<< bb >>
|
||||
rect 0 0 34 46
|
||||
<< labels >>
|
||||
rlabel metal2 0 0 0 0 1 gnd
|
||||
rlabel metal2 34 0 34 0 1 gnd
|
||||
rlabel m2contact 17 46 17 46 5 vdd
|
||||
rlabel metal2 8 43 8 43 1 bl
|
||||
rlabel metal2 26 43 26 43 1 br
|
||||
rlabel metal1 4 7 4 7 1 wl
|
||||
<< end >>
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1536089670
|
||||
<< nwell >>
|
||||
rect 0 0 40 102
|
||||
<< pwell >>
|
||||
rect 0 102 40 163
|
||||
<< ntransistor >>
|
||||
rect 21 130 23 139
|
||||
rect 12 108 14 117
|
||||
rect 20 108 22 117
|
||||
<< ptransistor >>
|
||||
rect 12 78 14 96
|
||||
rect 20 78 22 96
|
||||
rect 11 20 13 44
|
||||
rect 27 20 29 44
|
||||
<< ndiffusion >>
|
||||
rect 20 130 21 139
|
||||
rect 23 130 24 139
|
||||
rect 11 108 12 117
|
||||
rect 14 108 15 117
|
||||
rect 19 108 20 117
|
||||
rect 22 108 23 117
|
||||
<< pdiffusion >>
|
||||
rect 7 94 12 96
|
||||
rect 11 80 12 94
|
||||
rect 7 78 12 80
|
||||
rect 14 94 20 96
|
||||
rect 14 80 15 94
|
||||
rect 19 80 20 94
|
||||
rect 14 78 20 80
|
||||
rect 22 94 27 96
|
||||
rect 22 80 23 94
|
||||
rect 22 78 27 80
|
||||
rect 10 20 11 44
|
||||
rect 13 20 14 44
|
||||
rect 26 20 27 44
|
||||
rect 29 20 30 44
|
||||
<< ndcontact >>
|
||||
rect 16 130 20 139
|
||||
rect 24 130 28 139
|
||||
rect 7 108 11 117
|
||||
rect 15 108 19 117
|
||||
rect 23 108 27 117
|
||||
<< pdcontact >>
|
||||
rect 7 80 11 94
|
||||
rect 15 80 19 94
|
||||
rect 23 80 27 94
|
||||
rect 6 20 10 44
|
||||
rect 14 20 18 44
|
||||
rect 22 20 26 44
|
||||
rect 30 20 34 44
|
||||
<< psubstratepcontact >>
|
||||
rect 32 137 36 141
|
||||
<< nsubstratencontact >>
|
||||
rect 27 70 31 74
|
||||
<< polysilicon >>
|
||||
rect 21 139 23 149
|
||||
rect 21 129 23 130
|
||||
rect 3 127 23 129
|
||||
rect 3 47 5 127
|
||||
rect 12 122 34 124
|
||||
rect 12 117 14 122
|
||||
rect 20 117 22 119
|
||||
rect 12 96 14 108
|
||||
rect 20 96 22 108
|
||||
rect 32 105 34 122
|
||||
rect 30 101 34 105
|
||||
rect 12 76 14 78
|
||||
rect 20 69 22 78
|
||||
rect 13 67 22 69
|
||||
rect 9 55 11 65
|
||||
rect 32 55 34 101
|
||||
rect 33 51 34 55
|
||||
rect 3 45 13 47
|
||||
rect 11 44 13 45
|
||||
rect 27 44 29 46
|
||||
rect 11 19 13 20
|
||||
rect 27 19 29 20
|
||||
rect 11 17 29 19
|
||||
<< polycontact >>
|
||||
rect 20 149 24 153
|
||||
rect 26 101 30 105
|
||||
rect 9 65 13 69
|
||||
rect 9 51 13 55
|
||||
rect 29 51 33 55
|
||||
<< metal1 >>
|
||||
rect -2 149 20 153
|
||||
rect 24 149 36 153
|
||||
rect 28 133 32 137
|
||||
rect 16 117 19 130
|
||||
rect 7 94 11 108
|
||||
rect 23 105 27 108
|
||||
rect 23 101 26 105
|
||||
rect 7 69 11 80
|
||||
rect 15 94 19 96
|
||||
rect 15 78 19 80
|
||||
rect 23 94 27 101
|
||||
rect 23 78 27 80
|
||||
rect 15 75 18 78
|
||||
rect 15 74 31 75
|
||||
rect 15 72 27 74
|
||||
rect 7 65 9 69
|
||||
rect 6 44 9 54
|
||||
rect 33 51 34 55
|
||||
rect 31 44 34 51
|
||||
rect 3 20 6 23
|
||||
rect 3 15 7 20
|
||||
<< m2contact >>
|
||||
rect 32 133 36 137
|
||||
rect 27 66 31 70
|
||||
rect 13 44 17 48
|
||||
rect 22 44 26 48
|
||||
rect 3 11 7 15
|
||||
<< metal2 >>
|
||||
rect 10 48 14 163
|
||||
rect 20 48 24 163
|
||||
rect 32 129 36 133
|
||||
rect 27 62 31 66
|
||||
rect 10 44 13 48
|
||||
rect 20 44 22 48
|
||||
rect 3 0 7 11
|
||||
rect 10 0 14 44
|
||||
rect 20 0 24 44
|
||||
<< bb >>
|
||||
rect 0 0 34 163
|
||||
<< labels >>
|
||||
flabel metal1 0 149 0 149 4 FreeSans 26 0 0 0 en
|
||||
rlabel metal2 34 131 34 131 1 gnd
|
||||
rlabel metal2 29 64 29 64 1 vdd
|
||||
rlabel metal2 12 161 12 161 5 bl
|
||||
rlabel metal2 22 161 22 161 5 br
|
||||
rlabel metal2 5 3 5 3 1 dout
|
||||
<< properties >>
|
||||
string path 270.000 468.000 270.000 486.000 288.000 486.000 288.000 468.000 270.000 468.000
|
||||
<< end >>
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# Setup file for netgen
|
||||
ignore class c
|
||||
equate class {-circuit1 nfet} {-circuit2 n}
|
||||
equate class {-circuit1 pfet} {-circuit2 p}
|
||||
# This circuit has symmetries and needs to be flattened to resolve them
|
||||
# or the banks won't pass
|
||||
flatten class {-circuit1 precharge_array_1}
|
||||
flatten class {-circuit1 precharge_array_2}
|
||||
flatten class {-circuit1 precharge_array_3}
|
||||
flatten class {-circuit1 precharge_array_4}
|
||||
property {-circuit1 nfet} remove as ad ps pd
|
||||
property {-circuit1 pfet} remove as ad ps pd
|
||||
property {-circuit2 n} remove as ad ps pd
|
||||
property {-circuit2 p} remove as ad ps pd
|
||||
permute transistors
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1536089695
|
||||
<< nwell >>
|
||||
rect -2 45 38 73
|
||||
<< pwell >>
|
||||
rect -2 0 38 45
|
||||
<< ntransistor >>
|
||||
rect 9 27 11 31
|
||||
rect 17 27 19 31
|
||||
rect 25 27 27 31
|
||||
<< ptransistor >>
|
||||
rect 9 53 11 61
|
||||
rect 17 53 19 61
|
||||
rect 25 53 27 61
|
||||
<< ndiffusion >>
|
||||
rect 8 27 9 31
|
||||
rect 11 27 12 31
|
||||
rect 16 27 17 31
|
||||
rect 19 27 20 31
|
||||
rect 24 27 25 31
|
||||
rect 27 27 28 31
|
||||
<< pdiffusion >>
|
||||
rect 8 53 9 61
|
||||
rect 11 53 12 61
|
||||
rect 16 53 17 61
|
||||
rect 19 53 20 61
|
||||
rect 24 53 25 61
|
||||
rect 27 53 28 61
|
||||
<< ndcontact >>
|
||||
rect 4 27 8 31
|
||||
rect 12 27 16 31
|
||||
rect 20 27 24 31
|
||||
rect 28 27 32 31
|
||||
<< pdcontact >>
|
||||
rect 4 53 8 61
|
||||
rect 12 53 16 61
|
||||
rect 20 53 24 61
|
||||
rect 28 53 32 61
|
||||
<< psubstratepcontact >>
|
||||
rect 12 19 16 23
|
||||
<< nsubstratencontact >>
|
||||
rect 12 65 16 69
|
||||
<< polysilicon >>
|
||||
rect 25 63 35 65
|
||||
rect 9 61 11 63
|
||||
rect 17 61 19 63
|
||||
rect 25 61 27 63
|
||||
rect 9 50 11 53
|
||||
rect 9 31 11 46
|
||||
rect 17 42 19 53
|
||||
rect 25 51 27 53
|
||||
rect 17 31 19 38
|
||||
rect 25 31 27 33
|
||||
rect 9 25 11 27
|
||||
rect 17 25 19 27
|
||||
rect 25 16 27 27
|
||||
rect 33 8 35 63
|
||||
rect 32 6 35 8
|
||||
<< polycontact >>
|
||||
rect 9 46 13 50
|
||||
rect 16 38 20 42
|
||||
rect 25 12 29 16
|
||||
rect 28 4 32 8
|
||||
<< metal1 >>
|
||||
rect 16 65 23 69
|
||||
rect 12 61 16 65
|
||||
rect 3 53 4 61
|
||||
rect 3 42 6 53
|
||||
rect 13 46 15 50
|
||||
rect 3 38 16 42
|
||||
rect 3 31 6 38
|
||||
rect 29 31 32 53
|
||||
rect 3 27 4 31
|
||||
rect 12 23 16 27
|
||||
rect 16 19 24 23
|
||||
rect 0 12 25 16
|
||||
rect 29 12 36 16
|
||||
rect 0 4 28 8
|
||||
rect 32 4 36 8
|
||||
<< m2contact >>
|
||||
rect 23 65 27 69
|
||||
rect 15 46 19 50
|
||||
rect 25 34 29 38
|
||||
rect 24 19 28 23
|
||||
<< metal2 >>
|
||||
rect 15 34 25 38
|
||||
rect 15 0 19 34
|
||||
<< bb >>
|
||||
rect 0 0 34 73
|
||||
<< labels >>
|
||||
rlabel metal1 0 12 0 12 3 en
|
||||
rlabel metal1 0 4 0 4 2 en_bar
|
||||
rlabel metal2 16 1 16 1 1 out
|
||||
rlabel m2contact 26 21 26 21 1 gnd
|
||||
rlabel m2contact 25 67 25 67 1 vdd
|
||||
rlabel m2contact 17 48 17 48 1 in
|
||||
<< end >>
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
magic
|
||||
tech scmos
|
||||
timestamp 1536089714
|
||||
<< nwell >>
|
||||
rect -3 101 37 138
|
||||
rect -3 0 37 51
|
||||
<< pwell >>
|
||||
rect -3 138 37 202
|
||||
rect -3 51 37 101
|
||||
<< ntransistor >>
|
||||
rect 9 177 11 189
|
||||
rect 17 177 19 189
|
||||
rect 15 162 27 164
|
||||
rect 9 144 11 148
|
||||
rect 17 144 19 148
|
||||
rect 10 82 12 89
|
||||
rect 18 82 20 89
|
||||
rect 8 57 10 64
|
||||
rect 16 57 18 64
|
||||
rect 24 60 26 64
|
||||
<< ptransistor >>
|
||||
rect 9 125 11 132
|
||||
rect 17 125 19 132
|
||||
rect 10 107 12 114
|
||||
rect 18 107 20 114
|
||||
rect 8 38 10 45
|
||||
rect 16 38 18 45
|
||||
rect 24 38 26 45
|
||||
<< ndiffusion >>
|
||||
rect 8 177 9 189
|
||||
rect 11 177 12 189
|
||||
rect 16 177 17 189
|
||||
rect 19 177 20 189
|
||||
rect 15 164 27 165
|
||||
rect 15 161 27 162
|
||||
rect 12 157 15 160
|
||||
rect 12 156 16 157
|
||||
rect 8 144 9 148
|
||||
rect 11 144 12 148
|
||||
rect 16 144 17 148
|
||||
rect 19 144 20 148
|
||||
rect 9 82 10 89
|
||||
rect 12 82 13 89
|
||||
rect 17 82 18 89
|
||||
rect 20 82 21 89
|
||||
rect 25 82 26 86
|
||||
rect 7 57 8 64
|
||||
rect 10 57 11 64
|
||||
rect 15 57 16 64
|
||||
rect 18 57 19 64
|
||||
rect 23 60 24 64
|
||||
rect 26 60 27 64
|
||||
<< pdiffusion >>
|
||||
rect 8 125 9 132
|
||||
rect 11 125 12 132
|
||||
rect 16 125 17 132
|
||||
rect 19 125 20 132
|
||||
rect 12 122 16 125
|
||||
rect 9 107 10 114
|
||||
rect 12 107 13 114
|
||||
rect 17 107 18 114
|
||||
rect 20 107 21 114
|
||||
rect 7 38 8 45
|
||||
rect 10 38 11 45
|
||||
rect 15 38 16 45
|
||||
rect 18 38 19 45
|
||||
rect 23 38 24 45
|
||||
rect 26 38 27 45
|
||||
rect 3 35 7 38
|
||||
<< ndcontact >>
|
||||
rect 4 177 8 189
|
||||
rect 12 177 16 189
|
||||
rect 20 177 24 189
|
||||
rect 15 165 27 169
|
||||
rect 15 157 27 161
|
||||
rect 4 144 8 148
|
||||
rect 12 144 16 148
|
||||
rect 20 144 24 148
|
||||
rect 5 82 9 89
|
||||
rect 13 82 17 89
|
||||
rect 21 82 25 89
|
||||
rect 3 57 7 64
|
||||
rect 11 57 15 64
|
||||
rect 19 57 23 64
|
||||
rect 27 60 31 64
|
||||
<< pdcontact >>
|
||||
rect 4 125 8 132
|
||||
rect 12 125 16 132
|
||||
rect 20 125 24 132
|
||||
rect 5 107 9 114
|
||||
rect 13 107 17 114
|
||||
rect 21 107 25 114
|
||||
rect 3 38 7 45
|
||||
rect 11 38 15 45
|
||||
rect 19 38 23 45
|
||||
rect 27 38 31 45
|
||||
<< psubstratepcontact >>
|
||||
rect 12 152 16 156
|
||||
rect 26 82 30 86
|
||||
<< nsubstratencontact >>
|
||||
rect 12 118 16 122
|
||||
rect 3 31 7 35
|
||||
<< polysilicon >>
|
||||
rect 9 194 30 196
|
||||
rect 9 189 11 194
|
||||
rect 17 189 19 191
|
||||
rect 28 185 30 194
|
||||
rect 9 175 11 177
|
||||
rect 17 172 19 177
|
||||
rect 6 170 19 172
|
||||
rect 6 167 8 170
|
||||
rect 13 162 15 164
|
||||
rect 27 162 33 164
|
||||
rect 9 148 11 150
|
||||
rect 17 148 19 150
|
||||
rect 9 132 11 144
|
||||
rect 17 132 19 144
|
||||
rect 9 124 11 125
|
||||
rect 2 122 11 124
|
||||
rect 17 124 19 125
|
||||
rect 17 122 28 124
|
||||
rect 2 75 4 122
|
||||
rect 10 114 12 116
|
||||
rect 18 114 20 116
|
||||
rect 10 89 12 107
|
||||
rect 18 106 20 107
|
||||
rect 16 104 20 106
|
||||
rect 16 92 18 104
|
||||
rect 26 100 28 122
|
||||
rect 27 96 28 100
|
||||
rect 16 90 20 92
|
||||
rect 18 89 20 90
|
||||
rect 10 81 12 82
|
||||
rect 10 79 13 81
|
||||
rect 2 71 3 75
|
||||
rect 11 71 13 79
|
||||
rect 18 79 20 82
|
||||
rect 18 77 23 79
|
||||
rect 31 71 33 162
|
||||
rect 11 69 33 71
|
||||
rect 11 67 13 69
|
||||
rect 8 65 13 67
|
||||
rect 8 64 10 65
|
||||
rect 16 64 18 66
|
||||
rect 24 64 26 66
|
||||
rect 8 45 10 57
|
||||
rect 16 52 18 57
|
||||
rect 24 52 26 60
|
||||
rect 16 50 26 52
|
||||
rect 16 45 18 50
|
||||
rect 24 45 26 50
|
||||
rect 8 28 10 38
|
||||
rect 16 14 18 38
|
||||
rect 24 36 26 38
|
||||
<< polycontact >>
|
||||
rect 28 181 32 185
|
||||
rect 4 163 8 167
|
||||
rect 23 96 27 100
|
||||
rect 3 71 7 75
|
||||
rect 23 75 27 79
|
||||
rect 7 24 11 28
|
||||
rect 15 10 19 14
|
||||
<< metal1 >>
|
||||
rect 5 192 10 196
|
||||
rect 5 189 8 192
|
||||
rect 32 181 33 185
|
||||
rect 13 169 16 177
|
||||
rect 13 165 15 169
|
||||
rect 4 148 8 163
|
||||
rect 12 157 15 161
|
||||
rect 12 156 16 157
|
||||
rect 12 148 16 152
|
||||
rect 4 132 8 144
|
||||
rect 20 142 24 144
|
||||
rect 30 142 33 181
|
||||
rect 20 138 33 142
|
||||
rect 20 132 24 138
|
||||
rect 12 122 16 125
|
||||
rect 13 114 17 118
|
||||
rect 5 104 9 107
|
||||
rect 21 104 25 107
|
||||
rect 5 101 25 104
|
||||
rect 5 89 9 101
|
||||
rect 21 100 25 101
|
||||
rect 21 96 23 100
|
||||
rect 25 82 26 90
|
||||
rect 4 64 7 71
|
||||
rect 27 64 31 79
|
||||
rect 3 51 7 57
|
||||
rect 3 48 15 51
|
||||
rect 11 45 15 48
|
||||
rect 27 45 31 60
|
||||
rect 3 35 7 38
|
||||
rect 19 35 23 38
|
||||
rect 7 31 19 35
|
||||
rect 0 24 7 28
|
||||
rect 11 24 36 28
|
||||
<< m2contact >>
|
||||
rect 10 192 14 196
|
||||
rect 20 189 24 193
|
||||
rect 23 153 27 157
|
||||
rect 16 118 20 122
|
||||
rect 26 86 30 90
|
||||
rect 19 64 23 68
|
||||
rect 19 31 23 35
|
||||
rect 15 6 19 10
|
||||
<< metal2 >>
|
||||
rect 10 196 14 202
|
||||
rect 20 193 24 202
|
||||
rect 20 177 24 189
|
||||
rect 15 0 19 6
|
||||
<< bb >>
|
||||
rect 0 0 34 202
|
||||
<< labels >>
|
||||
rlabel metal2 15 1 15 1 1 din
|
||||
rlabel metal1 2 25 2 25 3 en
|
||||
rlabel metal2 12 200 12 200 5 bl
|
||||
rlabel metal2 22 200 22 200 5 br
|
||||
rlabel m2contact 21 66 21 66 1 gnd
|
||||
rlabel m2contact 28 88 28 88 1 gnd
|
||||
rlabel m2contact 21 33 21 33 1 vdd
|
||||
rlabel m2contact 18 120 18 120 1 vdd
|
||||
rlabel m2contact 25 155 25 155 1 gnd
|
||||
<< end >>
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
*********************************************
|
||||
* Transistor Models
|
||||
* Note: These models are approximate
|
||||
* and should be substituted with actual
|
||||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
|
||||
+ NSUB=6E16 U0=461 K1=0.5705 TOX=13.9n VERSION=3.3.0)
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
*********************************************
|
||||
* Transistor Models
|
||||
* Note: These models are approximate
|
||||
* and should be substituted with actual
|
||||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
|
||||
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
*********************************************
|
||||
* Transistor Models
|
||||
* Note: These models are approximate
|
||||
* and should be substituted with actual
|
||||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
|
||||
+ NSUB=6E16 U0=458 K1=0.5705 TOX=13.9n VERSION=3.3.0)
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
*********************************************
|
||||
* Transistor Models
|
||||
* Note: These models are approximate
|
||||
* and should be substituted with actual
|
||||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
|
||||
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
*********************************************
|
||||
* Transistor Models
|
||||
* Note: These models are approximate
|
||||
* and should be substituted with actual
|
||||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL n NMOS (LEVEL=49 VTHO=0.669845
|
||||
+ NSUB=6E16 U0=460 K1=0.5705 TOX=13.9n VERSION=3.3.0)
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
*********************************************
|
||||
* Transistor Models
|
||||
* Note: These models are approximate
|
||||
* and should be substituted with actual
|
||||
* models from MOSIS or SCN3ME
|
||||
*********************************************
|
||||
|
||||
.MODEL p PMOS (LEVEL=49 VTHO=-0.322431
|
||||
+ NSUB=6E16 U0=212 K1=0.0821 TOX=13.9n VERSION=3.3.0)
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
*********************** "cell_6t" ******************************
|
||||
.SUBCKT cell_6t bl br wl vdd gnd
|
||||
M_1 Q Qb vdd vdd p W='0.9u' L=1.2u
|
||||
M_2 Qb Q vdd vdd p W='0.9u' L=1.2u
|
||||
M_3 br wl Qb gnd n W='1.2u' L=0.6u
|
||||
M_4 bl wl Q gnd n W='1.2u' L=0.6u
|
||||
M_5 Qb Q gnd gnd n W='2.4u' L=0.6u
|
||||
M_6 Q Qb gnd gnd n W='2.4u' L=0.6u
|
||||
.ENDS $ cell_6t
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
*********************** "dff" ******************************
|
||||
* Positive edge-triggered FF
|
||||
.SUBCKT dff D Q clk vdd gnd
|
||||
M0 vdd clk a_2_6# vdd p w=12u l=0.6u
|
||||
M1 a_17_74# D vdd vdd p w=6u l=0.6u
|
||||
M2 a_22_6# clk a_17_74# vdd p w=6u l=0.6u
|
||||
M3 a_31_74# a_2_6# a_22_6# vdd p w=6u l=0.6u
|
||||
M4 vdd a_34_4# a_31_74# vdd p w=6u l=0.6u
|
||||
M5 a_34_4# a_22_6# vdd vdd p w=6u l=0.6u
|
||||
M6 a_61_74# a_34_4# vdd vdd p w=6u l=0.6u
|
||||
M7 a_66_6# a_2_6# a_61_74# vdd p w=6u l=0.6u
|
||||
M8 a_76_84# clk a_66_6# vdd p w=3u l=0.6u
|
||||
M9 vdd Q a_76_84# vdd p w=3u l=0.6u
|
||||
M10 gnd clk a_2_6# gnd n w=6u l=0.6u
|
||||
M11 Q a_66_6# vdd vdd p w=12u l=0.6u
|
||||
M12 a_17_6# D gnd gnd n w=3u l=0.6u
|
||||
M13 a_22_6# a_2_6# a_17_6# gnd n w=3u l=0.6u
|
||||
M14 a_31_6# clk a_22_6# gnd n w=3u l=0.6u
|
||||
M15 gnd a_34_4# a_31_6# gnd n w=3u l=0.6u
|
||||
M16 a_34_4# a_22_6# gnd gnd n w=3u l=0.6u
|
||||
M17 a_61_6# a_34_4# gnd gnd n w=3u l=0.6u
|
||||
M18 a_66_6# clk a_61_6# gnd n w=3u l=0.6u
|
||||
M19 a_76_6# a_2_6# a_66_6# gnd n w=3u l=0.6u
|
||||
M20 gnd Q a_76_6# gnd n w=3u l=0.6u
|
||||
M21 Q a_66_6# gnd gnd n w=6u l=0.6u
|
||||
|
||||
.ENDS dff
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
*master-slave flip-flop with both output and inverted ouput
|
||||
|
||||
.subckt dlatch din dout dout_bar clk clk_bar vdd gnd
|
||||
*clk inverter
|
||||
mPff1 clk_bar clk vdd vdd p W=1.8u L=0.6u m=1
|
||||
mNff1 clk_bar clk gnd gnd n W=0.9u L=0.6u m=1
|
||||
|
||||
*transmission gate 1
|
||||
mtmP1 din clk int1 vdd p W=1.8u L=0.6u m=1
|
||||
mtmN1 din clk_bar int1 gnd n W=0.9u L=0.6u m=1
|
||||
|
||||
*foward inverter
|
||||
mPff3 dout_bar int1 vdd vdd p W=1.8u L=0.6u m=1
|
||||
mNff3 dout_bar int1 gnd gnd n W=0.9u L=0.6u m=1
|
||||
|
||||
*backward inverter
|
||||
mPff4 dout dout_bar vdd vdd p W=1.8u L=0.6u m=1
|
||||
mNf4 dout dout_bar gnd gnd n W=0.9u L=0.6u m=1
|
||||
|
||||
*transmission gate 2
|
||||
mtmP2 int1 clk_bar dout vdd p W=1.8u L=0.6u m=1
|
||||
mtmN2 int1 clk dout gnd n W=0.9u L=0.6u m=1
|
||||
.ends dlatch
|
||||
|
||||
.subckt ms_flop din dout dout_bar clk vdd gnd
|
||||
xmaster din mout mout_bar clk clk_bar vdd gnd dlatch
|
||||
xslave mout_bar dout_bar dout clk_bar clk_nn vdd gnd dlatch
|
||||
.ends flop
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
*********************** "cell_6t" ******************************
|
||||
.SUBCKT replica_cell_6t bl br wl vdd gnd
|
||||
M_1 gnd net_2 vdd vdd p W='0.9u' L=1.2u
|
||||
M_2 net_2 gnd vdd vdd p W='0.9u' L=1.2u
|
||||
M_3 br wl net_2 gnd n W='1.2u' L=0.6u
|
||||
M_4 bl wl gnd gnd n W='1.2u' L=0.6u
|
||||
M_5 net_2 gnd gnd gnd n W='2.4u' L=0.6u
|
||||
M_6 gnd net_2 gnd gnd n W='2.4u' L=0.6u
|
||||
.ENDS $ replica_cell_6t
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
*********************** "sense_amp" ******************************
|
||||
|
||||
.SUBCKT sense_amp bl br dout en vdd gnd
|
||||
M_1 dout net_1 vdd vdd p W='5.4*1u' L=0.6u
|
||||
M_2 dout net_1 net_2 gnd n W='2.7*1u' L=0.6u
|
||||
M_3 net_1 dout vdd vdd p W='5.4*1u' L=0.6u
|
||||
M_4 net_1 dout net_2 gnd n W='2.7*1u' L=0.6u
|
||||
M_5 bl en dout vdd p W='7.2*1u' L=0.6u
|
||||
M_6 br en net_1 vdd p W='7.2*1u' L=0.6u
|
||||
M_7 net_2 en gnd gnd n W='2.7*1u' L=0.6u
|
||||
.ENDS sense_amp
|
||||
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
*********************** tri_gate ******************************
|
||||
|
||||
.SUBCKT tri_gate in out en en_bar vdd gnd
|
||||
|
||||
M_1 net_2 in_inv gnd gnd n W='1.2*1u' L=0.6u
|
||||
M_2 net_3 in_inv vdd vdd p W='2.4*1u' L=0.6u
|
||||
M_3 out en_bar net_3 vdd p W='2.4*1u' L=0.6u
|
||||
M_4 out en net_2 gnd n W='1.2*1u' L=0.6u
|
||||
M_5 in_inv in vdd vdd p W='2.4*1u' L=0.6u
|
||||
M_6 in_inv in gnd gnd n W='1.2*1u' L=0.6u
|
||||
|
||||
|
||||
.ENDS
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
*********************** Write_Driver ******************************
|
||||
.SUBCKT write_driver din bl br en vdd gnd
|
||||
|
||||
**** Inverter to conver Data_in to data_in_bar ******
|
||||
* din_bar = inv(din)
|
||||
M_1 din_bar din gnd gnd n W=1.2u L=0.6u
|
||||
M_2 din_bar din vdd vdd p W=2.1u L=0.6u
|
||||
|
||||
**** 2input nand gate follwed by inverter to drive BL ******
|
||||
* din_bar_gated = nand(en, din)
|
||||
M_3 din_bar_gated en net_7 gnd n W=2.1u L=0.6u
|
||||
M_4 net_7 din gnd gnd n W=2.1u L=0.6u
|
||||
M_5 din_bar_gated en vdd vdd p W=2.1u L=0.6u
|
||||
M_6 din_bar_gated din vdd vdd p W=2.1u L=0.6u
|
||||
* din_bar_gated_bar = inv(din_bar_gated)
|
||||
M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=2.1u L=0.6u
|
||||
M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=1.2u L=0.6u
|
||||
|
||||
**** 2input nand gate follwed by inverter to drive BR******
|
||||
* din_gated = nand(en, din_bar)
|
||||
M_9 din_gated en vdd vdd p W=2.1u L=0.6u
|
||||
M_10 din_gated en net_8 gnd n W=2.1u L=0.6u
|
||||
M_11 net_8 din_bar gnd gnd n W=2.1u L=0.6u
|
||||
M_12 din_gated din_bar vdd vdd p W=2.1u L=0.6u
|
||||
* din_gated_bar = inv(din_gated)
|
||||
M_13 din_gated_bar din_gated vdd vdd p W=2.1u L=0.6u
|
||||
M_14 din_gated_bar din_gated gnd gnd n W=1.2u L=0.6u
|
||||
|
||||
************************************************
|
||||
* pull down with en enable
|
||||
M_15 bl din_gated_bar net_5 gnd n W=3.6u L=0.6u
|
||||
M_16 br din_bar_gated_bar net_5 gnd n W=3.6u L=0.6u
|
||||
M_17 net_5 en gnd gnd n W=3.6u L=0.6u
|
||||
|
||||
|
||||
|
||||
.ENDS $ write_driver
|
||||
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
# SUE version MMI_SUE5.0.7
|
||||
|
||||
proc SCHEMATIC_cell_6t {} {
|
||||
make inout -name BL -origin {190 360}
|
||||
make inout -name BR -origin {830 360}
|
||||
make input -name WL -origin {240 120}
|
||||
make global -orient RXY -name vdd -origin {520 160}
|
||||
make global -name gnd -origin {510 600}
|
||||
make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230}
|
||||
make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230}
|
||||
make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360}
|
||||
make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360}
|
||||
make nmos -W 2.4u -L 0.6u -origin {630 490}
|
||||
make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490}
|
||||
make_wire 630 550 630 530
|
||||
make_wire 400 530 400 550
|
||||
make_wire 400 190 400 170
|
||||
make_wire 630 170 630 190
|
||||
make_wire 400 360 400 270
|
||||
make_wire 310 360 400 360
|
||||
make_wire 630 360 630 450
|
||||
make_wire 630 360 700 360
|
||||
make_wire 270 300 270 120
|
||||
make_wire 270 120 740 120
|
||||
make_wire 740 120 740 300
|
||||
make_wire 230 360 190 360
|
||||
make_wire 780 360 830 360
|
||||
make_wire 510 550 400 550
|
||||
make_wire 510 550 630 550
|
||||
make_wire 510 550 510 600
|
||||
make_wire 520 170 400 170
|
||||
make_wire 520 170 630 170
|
||||
make_wire 520 160 520 170
|
||||
make_wire 240 120 270 120
|
||||
make_wire 460 290 630 290
|
||||
make_wire 460 290 460 490
|
||||
make_wire 460 290 460 230
|
||||
make_wire 630 290 630 360
|
||||
make_wire 630 290 630 270
|
||||
make_wire 570 420 400 420
|
||||
make_wire 570 420 570 490
|
||||
make_wire 570 420 570 230
|
||||
make_wire 400 420 400 360
|
||||
make_wire 400 420 400 450
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
# SUE version MMI_SUE5.0.7
|
||||
|
||||
proc SCHEMATIC_ms_flop {} {
|
||||
make pmos -orient R90X -W 1.8u -L 0.6u -origin {40 250}
|
||||
make nmos -orient R270 -W 0.9u -L 0.6u -origin {40 380}
|
||||
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {-270 540}
|
||||
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {310 310}
|
||||
make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {430 730}
|
||||
make pmos -orient R90X -W 1.8u -L 0.6u -origin {190 670}
|
||||
make nmos -orient R270 -W 0.9u -L 0.6u -origin {190 780}
|
||||
make input -name clk -origin {-380 540}
|
||||
make input -name din -origin {-370 320}
|
||||
make pmos -orient R90X -W 1.8u -L 0.6u -origin {720 250}
|
||||
make nmos -orient R270 -W 0.9u -L 0.6u -origin {720 380}
|
||||
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {990 310}
|
||||
make pmos -orient R90X -W 1.8u -L 0.6u -origin {870 670}
|
||||
make nmos -orient R270 -W 0.9u -L 0.6u -origin {870 780}
|
||||
make inverter -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {620 540}
|
||||
make output -name dout -origin {1410 310}
|
||||
make output -name dout_bar -origin {1430 930}
|
||||
make inverter -orient RX -WP 1.8u -LP 0.6u -WN 0.9u -LN 0.6u -origin {1110 730}
|
||||
make_wire -330 160 40 160
|
||||
make_wire 40 160 40 190
|
||||
make_wire -370 320 0 320
|
||||
make_wire 360 310 480 310
|
||||
make_wire 460 730 480 730
|
||||
make_wire 230 730 380 730
|
||||
make_wire 100 310 100 720
|
||||
make_wire 100 720 150 720
|
||||
make_wire 100 310 80 310
|
||||
make_wire 100 310 280 310
|
||||
make_wire 0 250 0 320
|
||||
make_wire 0 320 0 380
|
||||
make_wire 80 250 80 310
|
||||
make_wire 80 310 80 380
|
||||
make_wire 40 440 40 540
|
||||
make_wire -330 840 190 840
|
||||
make_wire 230 670 230 730
|
||||
make_wire 230 730 230 780
|
||||
make_wire 150 670 150 720
|
||||
make_wire 150 720 150 780
|
||||
make_wire 190 540 190 610
|
||||
make_wire -330 540 -330 840
|
||||
make_wire -220 540 40 540
|
||||
make_wire 40 540 190 540
|
||||
make_wire -380 540 -330 540
|
||||
make_wire -330 540 -300 540
|
||||
make_wire -330 540 -330 160
|
||||
make_wire 720 160 720 190
|
||||
make_wire 1140 730 1160 730
|
||||
make_wire 780 310 780 720
|
||||
make_wire 780 720 830 720
|
||||
make_wire 780 310 760 310
|
||||
make_wire 780 310 960 310
|
||||
make_wire 680 320 680 380
|
||||
make_wire 760 250 760 310
|
||||
make_wire 760 310 760 380
|
||||
make_wire 720 440 720 540
|
||||
make_wire 910 670 910 730
|
||||
make_wire 910 730 910 780
|
||||
make_wire 830 670 830 720
|
||||
make_wire 830 720 830 780
|
||||
make_wire 870 540 870 610
|
||||
make_wire 720 540 870 540
|
||||
make_wire 670 540 720 540
|
||||
make_wire 480 310 480 730
|
||||
make_wire 1160 310 1160 730
|
||||
make_wire 530 540 530 160
|
||||
make_wire 530 160 720 160
|
||||
make_wire 530 540 190 540
|
||||
make_wire 530 540 590 540
|
||||
make_wire 530 540 530 840
|
||||
make_wire 530 840 870 840
|
||||
make_wire 680 310 480 310
|
||||
make_wire 680 310 680 250
|
||||
make_wire 680 310 680 320
|
||||
make_wire 950 730 910 730
|
||||
make_wire 950 730 1060 730
|
||||
make_wire 1040 310 1160 310
|
||||
make_wire 1160 310 1410 310
|
||||
make_wire 950 930 1430 930
|
||||
make_wire 950 730 950 930
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
# SUE version MMI_SUE5.0.7
|
||||
|
||||
proc SCHEMATIC_replica_cell_6t {} {
|
||||
make inout -name BL -origin {190 360}
|
||||
make inout -name BR -origin {830 360}
|
||||
make input -name WL -origin {240 120}
|
||||
make global -orient RXY -name vdd -origin {520 160}
|
||||
make global -name gnd -origin {510 600}
|
||||
make pmos -orient RY -W 0.9u -L 1.2u -origin {630 230}
|
||||
make pmos -orient RXY -W 0.9u -L 1.2u -origin {400 230}
|
||||
make nmos -orient R90 -W 1.2 -L 0.6u -origin {740 360}
|
||||
make nmos -orient R90X -W 1.2 -L 0.6u -origin {270 360}
|
||||
make nmos -W 2.4u -L 0.6u -origin {630 490}
|
||||
make nmos -orient RX -W 2.4u -L 0.6u -origin {400 490}
|
||||
make_wire 630 550 630 530
|
||||
make_wire 400 530 400 550
|
||||
make_wire 400 190 400 170
|
||||
make_wire 630 170 630 190
|
||||
make_wire 400 360 400 270
|
||||
make_wire 630 360 630 450
|
||||
make_wire 630 360 700 360
|
||||
make_wire 270 300 270 120
|
||||
make_wire 270 120 740 120
|
||||
make_wire 740 120 740 300
|
||||
make_wire 230 360 190 360
|
||||
make_wire 780 360 830 360
|
||||
make_wire 510 550 400 550
|
||||
make_wire 510 550 630 550
|
||||
make_wire 510 550 510 600
|
||||
make_wire 520 170 400 170
|
||||
make_wire 520 170 630 170
|
||||
make_wire 520 160 520 170
|
||||
make_wire 240 120 270 120
|
||||
make_wire 460 290 630 290
|
||||
make_wire 460 290 460 490
|
||||
make_wire 460 290 460 230
|
||||
make_wire 630 290 630 360
|
||||
make_wire 630 290 630 270
|
||||
make_wire 570 420 400 420
|
||||
make_wire 570 420 570 490
|
||||
make_wire 570 420 570 230
|
||||
make_wire 400 420 400 360
|
||||
make_wire 400 420 400 450
|
||||
make_wire 320 360 320 550
|
||||
make_wire 320 550 400 550
|
||||
make_wire 320 360 310 360
|
||||
make_wire 320 360 400 360
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
# SUE version MMI_SUE5.0.7
|
||||
|
||||
proc SCHEMATIC_sense_amp {} {
|
||||
make inout -name BL -origin {260 10}
|
||||
make global -orient RXY -name vdd -origin {490 170}
|
||||
make global -name gnd -origin {480 660}
|
||||
make input -name sclk -origin {180 610}
|
||||
make nmos -W 3.9u -L 0.6u -origin {600 500}
|
||||
make nmos -orient RX -W 3.9u -L 0.6u -origin {370 500}
|
||||
make pmos -orient RY -W 3u -L 0.6u -origin {600 240}
|
||||
make pmos -orient RXY -W 3u -L 0.6u -origin {370 240}
|
||||
make nmos -W 3.9u -L 0.6u -origin {480 610}
|
||||
make inout -name BR -origin {710 20}
|
||||
make pmos -W 3.9u -L 0.6u -origin {710 90}
|
||||
make pmos -orient RX -W 3.9u -L 0.6u -origin {260 90}
|
||||
make output -orient RXY -name dout -origin {110 370}
|
||||
make_wire 600 560 600 540
|
||||
make_wire 370 540 370 560
|
||||
make_wire 370 200 370 180
|
||||
make_wire 600 180 600 200
|
||||
make_wire 490 180 370 180
|
||||
make_wire 490 180 600 180
|
||||
make_wire 490 170 490 180
|
||||
make_wire 430 300 600 300
|
||||
make_wire 430 300 430 500
|
||||
make_wire 430 300 430 240
|
||||
make_wire 600 300 600 280
|
||||
make_wire 540 430 370 430
|
||||
make_wire 540 430 540 500
|
||||
make_wire 540 430 540 240
|
||||
make_wire 370 430 370 460
|
||||
make_wire 480 560 600 560
|
||||
make_wire 480 560 370 560
|
||||
make_wire 480 560 480 570
|
||||
make_wire 480 650 480 660
|
||||
make_wire 420 610 180 610
|
||||
make_wire 650 90 320 90
|
||||
make_wire 600 360 710 360
|
||||
make_wire 710 360 710 130
|
||||
make_wire 600 360 600 300
|
||||
make_wire 600 360 600 460
|
||||
make_wire 370 370 260 370
|
||||
make_wire 260 370 260 130
|
||||
make_wire 370 370 370 430
|
||||
make_wire 370 370 370 280
|
||||
make_wire 260 10 260 50
|
||||
make_wire 710 20 710 50
|
||||
make_wire 320 90 180 90
|
||||
make_wire 180 90 180 610
|
||||
make_wire 110 370 260 370
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# SUE version MMI_SUE5.0.7
|
||||
|
||||
proc SCHEMATIC_tri_gate {} {
|
||||
make global -orient RXY -name vdd -origin {630 150}
|
||||
make global -name gnd -origin {630 570}
|
||||
make input -name tri_in -origin {320 340}
|
||||
make output -name tri_out -origin {690 360}
|
||||
make input -name en -origin {570 410}
|
||||
make input -name en_bar -origin {570 310}
|
||||
make nmos -W 1.2u -L 0.6u -origin {630 490}
|
||||
make nmos -W 1.2u -L 0.6u -origin {630 410}
|
||||
make pmos -orient RY -W 2.4u -L 0.6u -origin {630 310}
|
||||
make pmos -orient RY -W 2.4u -L 0.6u -origin {630 230}
|
||||
make pmos -orient RY -W 2.4u -L 0.6u -origin {380 290}
|
||||
make nmos -W 1.2u -L 0.6u -origin {380 400}
|
||||
make_wire 570 490 470 490
|
||||
make_wire 470 230 570 230
|
||||
make_wire 630 550 380 550
|
||||
make_wire 380 550 380 440
|
||||
make_wire 630 550 630 570
|
||||
make_wire 630 550 630 530
|
||||
make_wire 630 170 380 170
|
||||
make_wire 380 170 380 250
|
||||
make_wire 630 170 630 190
|
||||
make_wire 630 170 630 150
|
||||
make_wire 320 340 320 400
|
||||
make_wire 320 340 320 290
|
||||
make_wire 380 340 470 340
|
||||
make_wire 380 340 380 330
|
||||
make_wire 380 340 380 360
|
||||
make_wire 470 340 470 490
|
||||
make_wire 470 340 470 230
|
||||
make_wire 630 360 630 350
|
||||
make_wire 630 360 630 370
|
||||
make_wire 630 360 690 360
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
# SUE version MMI_SUE5.0.7
|
||||
|
||||
proc SCHEMATIC_write_driver {} {
|
||||
make inout -name BL -origin {550 260}
|
||||
make inout -name BR -origin {830 250}
|
||||
make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {280 520}
|
||||
make nand2 -WP 2.1u -WN 2.1u -origin {90 360}
|
||||
make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {270 360}
|
||||
make nmos -W 3.6u -L 0.6u -origin {830 410}
|
||||
make nmos -W 3.6u -L 0.6u -origin {710 610}
|
||||
make global -name gnd -origin {710 690}
|
||||
make nand2 -WP 2.1u -WN 2.1u -origin {90 520}
|
||||
make nmos -W 3.6u -L 0.6u -origin {550 410}
|
||||
make input -name wen -origin {-290 340}
|
||||
make input -name din -origin {-290 380}
|
||||
make inverter -WP 2.1u -LP 0.6u -WN 1.2u -LN 0.6u -origin {-80 540}
|
||||
make_wire 160 360 240 360
|
||||
make_wire 830 250 830 370
|
||||
make_wire 550 260 550 370
|
||||
make_wire 550 450 550 560
|
||||
make_wire 550 560 710 560
|
||||
make_wire 710 560 710 570
|
||||
make_wire 710 560 830 560
|
||||
make_wire 830 560 830 450
|
||||
make_wire 710 650 710 690
|
||||
make_wire 250 520 160 520
|
||||
make_wire 770 410 770 520
|
||||
make_wire 770 520 330 520
|
||||
make_wire 320 360 490 360
|
||||
make_wire 490 360 490 410
|
||||
make_wire -180 380 -290 380
|
||||
make_wire -180 380 70 380
|
||||
make_wire -180 540 -110 540
|
||||
make_wire -180 380 -180 540
|
||||
make_wire -30 540 70 540
|
||||
make_wire 20 340 20 500
|
||||
make_wire 20 500 70 500
|
||||
make_wire 20 340 70 340
|
||||
make_wire -240 340 -240 610
|
||||
make_wire -240 610 650 610
|
||||
make_wire -240 340 20 340
|
||||
make_wire -240 340 -290 340
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
The file SCN3ME_SUBM.30.tech is from qflow 1.2 and has the following
|
||||
license information:
|
||||
---------------------------------------------------------------
|
||||
Tim Edwards
|
||||
Open Circuit Design
|
||||
v1.0 April 2013
|
||||
v1.1 May 2015
|
||||
v1.2 April 2017
|
||||
---------------------------------------------------------------
|
||||
GPL Copyright (c) 2017
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,6 @@
|
|||
"""
|
||||
Import tech specific modules.
|
||||
"""
|
||||
|
||||
from .tech import *
|
||||
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
////////////////////////////////////////////////////////////
|
||||
// DEFINE BOOLEAN LAYERS
|
||||
////////////////////////////////////////////////////////////
|
||||
LAYOUT USE DATABASE PRECISION YES
|
||||
|
||||
layer pwell 41
|
||||
layer nwell 42
|
||||
layer active 43
|
||||
layer poly 46
|
||||
layer nimplant 45
|
||||
layer pimplant 44
|
||||
layer contact 25
|
||||
layer active_contact 48
|
||||
layer poly_contact 47
|
||||
layer metal1 49
|
||||
layer via1 50
|
||||
layer metal2 51
|
||||
layer via2 61
|
||||
layer metal3 62
|
||||
layer glass 52
|
||||
layer pad 26
|
||||
|
||||
//Enabling incremental connectivity for antenna rule checks
|
||||
DRC Incremental Connect Yes
|
||||
|
||||
well = nwell OR pwell
|
||||
gate = poly AND active
|
||||
implant = nimplant OR pimplant
|
||||
fieldpoly = poly NOT active
|
||||
|
||||
contactenc1 = active OR poly
|
||||
contactenc = contactenc1 AND metal1
|
||||
diode = contact AND active
|
||||
act_poly = interact poly active
|
||||
|
||||
GROUP mask_check
|
||||
//Well.2 Well.4
|
||||
Poly.1 Poly.2 Poly.3 Poly.4 Poly.5
|
||||
Active.1 Active.2 // Active.3
|
||||
Contact.1 Contact.2 Contact.3 Contact.4
|
||||
Contact.5 Contact.6 Metal1.1 Metal1.2 Metal1.3
|
||||
|
||||
|
||||
|
||||
//Well.1 {
|
||||
//@Nwell and Pwell must not overlap
|
||||
//AND nwell pwell
|
||||
//}
|
||||
|
||||
//Well.2 {
|
||||
//@Min spacing of pwell to nwell = 0.00
|
||||
//EXTERNAL nwell pwell < 0.00
|
||||
//}
|
||||
|
||||
//Well.4 {
|
||||
//@Min width of nwell = 3.6
|
||||
//INTERNAL nwell < 3.6
|
||||
//}
|
||||
|
||||
Poly.1 {
|
||||
@Min width of poly = 0.6
|
||||
INTERNAL poly < 0.6
|
||||
}
|
||||
|
||||
Poly.2 {
|
||||
@Min spacing of gate poly = 0.9
|
||||
EXTERNAL gate < 0.9
|
||||
}
|
||||
|
||||
Poly.3 {
|
||||
@Min extension of poly past active = 0.6
|
||||
ENCLOSURE active poly < 0.6
|
||||
}
|
||||
|
||||
Poly.4 {
|
||||
@Minimum active enclosure of gate =0.6
|
||||
ENCLOSURE poly active < 0.6
|
||||
}
|
||||
|
||||
Poly.5 {
|
||||
@Minimum spacing of poly to active = 0.3
|
||||
EXTERNAL act_poly active < 0.3
|
||||
}
|
||||
|
||||
Active.1 {
|
||||
@Minimum width of active = 0.9
|
||||
INTERNAL active < 0.9
|
||||
}
|
||||
|
||||
Active.2 {
|
||||
@Minimum spacing of active areas = 0.9
|
||||
EXTERNAL active < 0.9
|
||||
}
|
||||
|
||||
//Active.3 {
|
||||
//@Minimum well enclosure of active = 1.8
|
||||
//ENCLOSURE active well < 1.8
|
||||
//}
|
||||
|
||||
Contact.1 {
|
||||
@Minimum width of contact = 0.6
|
||||
INTERNAL contact < 0.6
|
||||
}
|
||||
|
||||
Contact.2 {
|
||||
@Minimum spacing of contact = 0.9
|
||||
EXTERNAL contact < 0.9
|
||||
}
|
||||
|
||||
Contact.3 {
|
||||
@Contact must be inside metal1 and active or poly
|
||||
NOT contact contactenc
|
||||
}
|
||||
|
||||
Contact.4 {
|
||||
@Minimum active enclosure of contact = 0.3
|
||||
ENCLOSURE contact active < 0.3
|
||||
}
|
||||
|
||||
Contact.5 {
|
||||
@Minimum poly enclosure of contact = 0.3
|
||||
ENCLOSURE contact poly < 0.3
|
||||
}
|
||||
|
||||
Contact.6 {
|
||||
@Minimum spacing of contact to poly = 0.6
|
||||
EXTERNAL poly contact < 0.6
|
||||
}
|
||||
|
||||
Metal1.1 {
|
||||
@Minimum width of metal1 = 0.9
|
||||
INTERNAL metal1 < 0.9
|
||||
}
|
||||
|
||||
Metal1.2 {
|
||||
@Minimum spacing of metal1 = 0.9
|
||||
EXTERNAL metal1 < 0.9
|
||||
}
|
||||
|
||||
Metal1.3 {
|
||||
@Metal1 must extend past contact by 0.3 on two opposite sides
|
||||
RECTANGLE ENCLOSURE contact metal1
|
||||
GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE
|
||||
}
|
||||
|
||||
Metal1.4 {
|
||||
@Metal1 must extend past via1 by 0.3 on two opposite sides
|
||||
RECTANGLE ENCLOSURE via1 metal1
|
||||
GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE
|
||||
}
|
||||
|
||||
Via1.1 {
|
||||
@Minimum width of via1 = 0.6
|
||||
INTERNAL via1 < 0.6
|
||||
}
|
||||
|
||||
Via1.2 {
|
||||
@Minimum spacing of via1 = 0.6
|
||||
EXTERNAL via1 < 0.6
|
||||
}
|
||||
|
||||
Via1.3 {
|
||||
@Via1 must be inside metal1
|
||||
NOT via1 metal1
|
||||
}
|
||||
|
||||
|
||||
Metal2.1 {
|
||||
@Minimum width of metal2 = 0.9
|
||||
INTERNAL metal2 < 0.9
|
||||
}
|
||||
|
||||
Metal2.2 {
|
||||
@Minimum spacing of metal2 = 0.9
|
||||
EXTERNAL metal2 < 0.9
|
||||
}
|
||||
|
||||
Metal2.3 {
|
||||
@Metal2 must extend past via1 by 0.3 on two opposite sides
|
||||
RECTANGLE ENCLOSURE via1 metal2
|
||||
GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE
|
||||
}
|
||||
|
||||
Metal2.4 {
|
||||
@Metal2 must extend past via2 by 0.3 on two opposite sides
|
||||
RECTANGLE ENCLOSURE via2 metal2
|
||||
GOOD 0.00 0.3 OPPOSITE 0.00 0.3 OPPOSITE
|
||||
}
|
||||
|
||||
Via2.1 {
|
||||
@Minimum width of via2 = 0.6
|
||||
INTERNAL via2 < 0.6
|
||||
}
|
||||
|
||||
Via2.2 {
|
||||
@Minimum spacing of via2 = 0.9
|
||||
EXTERNAL via2 < 0.9
|
||||
}
|
||||
|
||||
Via2.3 {
|
||||
@Via2 must be inside metal2
|
||||
NOT via2 metal2
|
||||
}
|
||||
|
||||
Via2.4 {
|
||||
@Via2 must be inside metal3
|
||||
NOT via2 metal3
|
||||
}
|
||||
|
||||
Metal3.1 {
|
||||
@Minimum width of metal3 = 1.5
|
||||
INTERNAL metal3 < 1.5
|
||||
}
|
||||
|
||||
Metal3.2 {
|
||||
@Minimum spacing of metal3 = 0.9
|
||||
EXTERNAL metal3 < 0.9
|
||||
}
|
||||
|
||||
Metal3.3 {
|
||||
@Metal3 must extend past via2 by 0.6 on two opposite sides
|
||||
RECTANGLE ENCLOSURE via2 metal3
|
||||
GOOD 0.00 0.6 OPPOSITE 0.00 0.6 OPPOSITE
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
TITLE "LVS Rule File for scn3me_subm"
|
||||
|
||||
LVS POWER NAME vdd
|
||||
LVS GROUND NAME gnd GROUND
|
||||
LVS REDUCE PARALLEL MOS yes
|
||||
LVS REDUCE SERIES MOS yes
|
||||
LVS REDUCE SEMI SERIES MOS yes
|
||||
LVS FILTER UNUSED MOS no
|
||||
LVS RECOGNIZE GATES all
|
||||
LVS COMPONENT TYPE PROPERTY element
|
||||
LVS COMPONENT SUBTYPE PROPERTY model
|
||||
LVS IGNORE PORTS no
|
||||
|
||||
LVS REPORT mask.lvs.rep
|
||||
LVS REPORT OPTION N
|
||||
LVS REPORT MAXIMUM 50
|
||||
MASK RESULTS DATABASE maskdb
|
||||
|
||||
precision 1000
|
||||
resolution 250
|
||||
|
||||
TEXT LAYER metal1 metal2 metal3
|
||||
PORT LAYER TEXT metal1 metal2 metal3
|
||||
|
||||
|
||||
layer pwell 41
|
||||
layer nwell 42
|
||||
layer active 43
|
||||
layer poly 46
|
||||
layer nimplant 45
|
||||
layer pimplant 44
|
||||
layer contact 25
|
||||
layer active_contact 48
|
||||
layer poly_contact 47
|
||||
layer metal1 49
|
||||
layer via1 50
|
||||
layer metal2 51
|
||||
layer via2 61
|
||||
layer metal3 62
|
||||
layer glass 52
|
||||
layer pad 26
|
||||
|
||||
connect metal1 metal2 by via1
|
||||
connect metal2 metal3 by via2
|
||||
|
||||
pdif = active and pimplant // P-diffusion
|
||||
ndif = active and nimplant // N-diffusion
|
||||
|
||||
ngate = poly and ndif // N-Transistor
|
||||
pgate = poly and pdif // P-transistor
|
||||
|
||||
nsrcdrn = ndif not ngate // N-tansistor Source and Drain contacts diffusion region
|
||||
psrcdrn = pdif not pgate // P-tansistor Source and Drain contacts diffusion region
|
||||
|
||||
pcont = psrcdrn and pwell
|
||||
|
||||
ntapcont = active not interact pimplant
|
||||
ptapcont = active not interact nimplant
|
||||
|
||||
bulk = extent
|
||||
nsub = (bulk not pwell) and nwell
|
||||
ncont = nsrcdrn and nsub
|
||||
|
||||
connect metal1 poly psrcdrn nsrcdrn by contact mask
|
||||
connect psrcdrn pwell by pcont mask
|
||||
connect nsrcdrn nsub by ncont mask
|
||||
|
||||
ncont1= ntapcont and nsub
|
||||
pcont1= ptapcont and pwell
|
||||
connect metal1 ncont1 by contact mask
|
||||
connect metal1 pcont1 by contact mask
|
||||
connect ncont1 nsub
|
||||
connect pcont1 pwell
|
||||
|
||||
connect psrcdrn metal1 by contact
|
||||
connect nsrcdrn metal1 by contact
|
||||
|
||||
connect psrcdrn metal1 by active_contact
|
||||
connect nsrcdrn metal1 by active_contact
|
||||
|
||||
connect poly metal1 by contact
|
||||
|
||||
connect poly metal1 by poly_contact
|
||||
|
||||
device mp (p) pgate poly (G) psrcdrn (S) psrcdrn (D) nsub CMACRO FET_PROPERTIES pgate nsub
|
||||
device mn (n) ngate poly (G) nsrcdrn (S) nsrcdrn (D) pwell CMACRO FET_PROPERTIES ngate pwell
|
||||
|
||||
VARIABLE trace_delta 4e-9
|
||||
|
||||
DMACRO FET_TRACE device_type device_name {
|
||||
TRACE PROPERTY device_type(device_name) l l trace_delta ABSOLUTE
|
||||
TRACE PROPERTY device_type(device_name) w w trace_delta ABSOLUTE
|
||||
|
||||
}
|
||||
|
||||
CMACRO FET_TRACE MN n
|
||||
CMACRO FET_TRACE MP p
|
||||
|
||||
DMACRO FET_PROPERTIES seed well{
|
||||
[
|
||||
PROPERTY W, L, AS, AD, PS, PD
|
||||
|
||||
AS = area(S)
|
||||
AD = area(D)
|
||||
PS = perimeter(S)
|
||||
PD = perimeter(D)
|
||||
if ( AS == 0 ) {
|
||||
AD = area(D) / 2
|
||||
AS = AD
|
||||
PD = perimeter(D) / 2
|
||||
PS = PD
|
||||
}
|
||||
if ( AD == 0 ) {
|
||||
AS = area(S) / 2
|
||||
AD = AS
|
||||
PS = perimeter(S) / 2
|
||||
PD = PS
|
||||
}
|
||||
W = (perim_co(seed,S) + perim_co(seed,D) ) * 0.5
|
||||
L = (perim(seed) - perim_co(seed,S) - perim_in(seed,S) - perim_co(seed,D) - perim_in(seed,D) ) * 0.5
|
||||
|
||||
]
|
||||
}
|
||||
|
|
@ -0,0 +1,311 @@
|
|||
import os
|
||||
from design_rules import *
|
||||
|
||||
"""
|
||||
File containing the process technology parameters for SCMOS 3me, subm, 180nm.
|
||||
"""
|
||||
|
||||
#GDS file info
|
||||
GDS={}
|
||||
# gds units
|
||||
# gds units
|
||||
# From http://www.cnf.cornell.edu/cnf_spie9.html: "The first
|
||||
#is the size of a database unit in user units. The second is the size
|
||||
#of a database unit in meters. For example, if your library was
|
||||
#created with the default units (user unit = 1 m and 1000 database
|
||||
#units per user unit), then the first number would be 0.001 and the
|
||||
#second number would be 10-9. Typically, the first number is less than
|
||||
#1, since you use more than 1 database unit per user unit. To
|
||||
#calculate the size of a user unit in meters, divide the second number
|
||||
#by the first."
|
||||
GDS["unit"]=(0.001,1e-6)
|
||||
# default label zoom
|
||||
GDS["zoom"] = 0.5
|
||||
|
||||
|
||||
###################################################
|
||||
##GDS Layer Map
|
||||
###################################################
|
||||
|
||||
# create the GDS layer map
|
||||
layer={}
|
||||
layer["vtg"] = -1
|
||||
layer["vth"] = -1
|
||||
layer["contact"] = 47
|
||||
layer["pwell"] = 41
|
||||
layer["nwell"] = 42
|
||||
layer["active"] = 43
|
||||
layer["pimplant"] = 44
|
||||
layer["nimplant"] = 45
|
||||
layer["poly"] = 46
|
||||
layer["active_contact"] = 48
|
||||
layer["metal1"] = 49
|
||||
layer["via1"] = 50
|
||||
layer["metal2"] = 51
|
||||
layer["via2"] = 61
|
||||
layer["metal3"] = 62
|
||||
layer["text"] = 63
|
||||
layer["boundary"] = 63
|
||||
layer["blockage"] = 83
|
||||
|
||||
###################################################
|
||||
##END GDS Layer Map
|
||||
###################################################
|
||||
|
||||
###################################################
|
||||
##DRC/LVS Rules Setup
|
||||
###################################################
|
||||
_lambda_ = 0.3
|
||||
|
||||
#technology parameter
|
||||
parameter={}
|
||||
parameter["min_tx_size"] = 4*_lambda_
|
||||
parameter["beta"] = 2
|
||||
|
||||
parameter["6T_inv_nmos_size"] = 8*_lambda_
|
||||
parameter["6T_inv_pmos_size"] = 3*_lambda_
|
||||
parameter["6T_access_size"] = 4*_lambda_
|
||||
|
||||
drclvs_home=os.environ.get("DRCLVS_HOME")
|
||||
|
||||
drc = design_rules("scn3me_subm")
|
||||
|
||||
drc["body_tie_down"] = 0
|
||||
drc["has_pwell"] = True
|
||||
drc["has_nwell"] = True
|
||||
|
||||
|
||||
#grid size is 1/2 a lambda
|
||||
drc["grid"]=0.5*_lambda_
|
||||
#DRC/LVS test set_up
|
||||
drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul"
|
||||
drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul"
|
||||
drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
|
||||
|
||||
|
||||
# minwidth_tx with contact (no dog bone transistors)
|
||||
drc["minwidth_tx"] = 4*_lambda_
|
||||
drc["minlength_channel"] = 2*_lambda_
|
||||
|
||||
# 1.3 Minimum spacing between wells of same type (if both are drawn)
|
||||
drc["well_to_well"] = 6*_lambda_
|
||||
# 1.4 Minimum spacing between wells of different type (if both are drawn)
|
||||
drc["pwell_to_nwell"] = 0
|
||||
# 1.1 Minimum width
|
||||
drc["minwidth_well"] = 12*_lambda_
|
||||
|
||||
# 3.1 Minimum width
|
||||
drc["minwidth_poly"] = 2*_lambda_
|
||||
# 3.2 Minimum spacing over active
|
||||
drc["poly_to_poly"] = 3*_lambda_
|
||||
# 3.3 Minimum gate extension of active
|
||||
drc["poly_extend_active"] = 2*_lambda_
|
||||
# 5.5.b Minimum spacing between poly contact and other poly (alternative rules)
|
||||
drc["poly_to_polycontact"] = 4*_lambda_
|
||||
# ??
|
||||
drc["active_enclosure_gate"] = 0.0
|
||||
# 3.5 Minimum field poly to active
|
||||
drc["poly_to_active"] = _lambda_
|
||||
# 3.2.a Minimum spacing over field poly
|
||||
drc["poly_to_field_poly"] = 3*_lambda_
|
||||
# Not a rule
|
||||
drc["minarea_poly"] = 0.0
|
||||
|
||||
# ??
|
||||
drc["active_to_body_active"] = 4*_lambda_ # Fix me
|
||||
# 2.1 Minimum width
|
||||
drc["minwidth_active"] = 3*_lambda_
|
||||
# 2.2 Minimum spacing
|
||||
drc["active_to_active"] = 3*_lambda_
|
||||
# 2.3 Source/drain active to well edge
|
||||
drc["well_enclosure_active"] = 6*_lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["well_extend_active"] = 6*_lambda_
|
||||
# Not a rule
|
||||
drc["minarea_active"] = 0.0
|
||||
|
||||
# 4.1 Minimum select spacing to channel of transistor to ensure adequate source/drain width
|
||||
drc["implant_to_channel"] = 3*_lambda_
|
||||
# 4.2 Minimum select overlap of active
|
||||
drc["implant_enclosure_active"] = 2*_lambda_
|
||||
# 4.3 Minimum select overlap of contact
|
||||
drc["implant_enclosure_contact"] = _lambda_
|
||||
# Not a rule
|
||||
drc["implant_to_contact"] = 0
|
||||
# Not a rule
|
||||
drc["implant_to_implant"] = 0
|
||||
# Not a rule
|
||||
drc["minwidth_implant"] = 0
|
||||
|
||||
# 6.1 Exact contact size
|
||||
drc["minwidth_contact"] = 2*_lambda_
|
||||
# 5.3 Minimum contact spacing
|
||||
drc["contact_to_contact"] = 3*_lambda_
|
||||
# 6.2.b Minimum active overlap
|
||||
drc["active_enclosure_contact"] = _lambda_
|
||||
# Reserved for asymmetric enclosure
|
||||
drc["active_extend_contact"] = _lambda_
|
||||
# 5.2.b Minimum poly overlap
|
||||
drc["poly_enclosure_contact"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["poly_extend_contact"] = _lambda_
|
||||
# Reserved for other technologies
|
||||
drc["contact_to_gate"] = 2*_lambda_
|
||||
# 5.4 Minimum spacing to gate of transistor
|
||||
drc["contact_to_poly"] = 2*_lambda_
|
||||
|
||||
# 7.1 Minimum width
|
||||
drc["minwidth_metal1"] = 3*_lambda_
|
||||
# 7.2 Minimum spacing
|
||||
drc["metal1_to_metal1"] = 3*_lambda_
|
||||
# 7.3 Minimum overlap of any contact
|
||||
drc["metal1_enclosure_contact"] = _lambda_
|
||||
# Reserved for asymmetric enclosure
|
||||
drc["metal1_extend_contact"] = _lambda_
|
||||
# 8.3 Minimum overlap by metal1
|
||||
drc["metal1_enclosure_via1"] = _lambda_
|
||||
# Reserve for asymmetric enclosures
|
||||
drc["metal1_extend_via1"] = _lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal1"] = 0
|
||||
|
||||
# 8.1 Exact size
|
||||
drc["minwidth_via1"] = 2*_lambda_
|
||||
# 8.2 Minimum via1 spacing
|
||||
drc["via1_to_via1"] = 3*_lambda_
|
||||
|
||||
# 9.1 Minimum width
|
||||
drc["minwidth_metal2"] = 3*_lambda_
|
||||
# 9.2 Minimum spacing
|
||||
drc["metal2_to_metal2"] = 3*_lambda_
|
||||
# 9.3 Minimum overlap of via1
|
||||
drc["metal2_extend_via1"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal2_enclosure_via1"] = _lambda_
|
||||
# 14.3 Minimum overlap by metal2
|
||||
drc["metal2_extend_via2"] = _lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal2_enclosure_via2"] = _lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal2"] = 0
|
||||
|
||||
# 14.1 Exact size
|
||||
drc["minwidth_via2"] = 2*_lambda_
|
||||
# 14.2 Minimum spacing
|
||||
drc["via2_to_via2"] = 3*_lambda_
|
||||
|
||||
# 15.1 Minimum width
|
||||
drc["minwidth_metal3"] = 5*_lambda_
|
||||
# 15.2 Minimum spacing to metal3
|
||||
drc["metal3_to_metal3"] = 3*_lambda_
|
||||
# 15.3 Minimum overlap of via 2
|
||||
drc["metal3_extend_via2"] = 2*_lambda_
|
||||
# Reserved for asymmetric enclosures
|
||||
drc["metal3_enclosure_via2"] = 2*_lambda_
|
||||
# Not a rule
|
||||
drc["minarea_metal3"] = 0
|
||||
|
||||
###################################################
|
||||
##END DRC/LVS Rules
|
||||
###################################################
|
||||
|
||||
###################################################
|
||||
##Spice Simulation Parameters
|
||||
###################################################
|
||||
|
||||
# spice model info
|
||||
spice={}
|
||||
spice["nmos"]="n"
|
||||
spice["pmos"]="p"
|
||||
# This is a map of corners to model files
|
||||
SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
|
||||
# FIXME: Uncomment when we have the new spice models
|
||||
#spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] }
|
||||
spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
|
||||
"FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
|
||||
"FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
|
||||
"SF" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
|
||||
"SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
|
||||
"ST" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
|
||||
"TS" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
|
||||
"FT" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
|
||||
"TF" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
|
||||
}
|
||||
|
||||
|
||||
#spice stimulus related variables
|
||||
spice["feasible_period"] = 10 # estimated feasible period in ns
|
||||
spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts]
|
||||
spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts]
|
||||
spice["rise_time"] = 0.05 # rise time in [Nano-seconds]
|
||||
spice["fall_time"] = 0.05 # fall time in [Nano-seconds]
|
||||
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
|
||||
spice["nom_temperature"] = 25 # Nominal temperature (celcius)
|
||||
|
||||
#sram signal names
|
||||
#FIXME: We don't use these everywhere...
|
||||
spice["vdd_name"] = "vdd"
|
||||
spice["gnd_name"] = "gnd"
|
||||
spice["control_signals"] = ["CSB", "WEB"]
|
||||
spice["data_name"] = "DATA"
|
||||
spice["addr_name"] = "ADDR"
|
||||
spice["minwidth_tx"] = drc["minwidth_tx"]
|
||||
spice["channel"] = drc["minlength_channel"]
|
||||
spice["clk"] = "clk"
|
||||
|
||||
# analytical delay parameters
|
||||
# FIXME: These need to be updated for SCMOS, they are copied from FreePDK45.
|
||||
spice["vdd_nominal"] = 5.0 # Typical Threshold voltage in Volts
|
||||
spice["temp_nominal"] = 25.0 # Typical Threshold voltage in Volts
|
||||
spice["v_threshold_typical"] = 1.3 # Typical Threshold voltage in Volts
|
||||
spice["wire_unit_r"] = 0.075 # Unit wire resistance in ohms/square
|
||||
spice["wire_unit_c"] = 0.64 # Unit wire capacitance ff/um^2
|
||||
spice["min_tx_r"] = 9250.0 # Minimum transistor on resistance in ohms
|
||||
spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
|
||||
spice["min_tx_gate_c"] = 0.1 # Minimum transistor gate capacitance in ff
|
||||
spice["msflop_setup"] = 9 # DFF setup time in ps
|
||||
spice["msflop_hold"] = 1 # DFF hold time in ps
|
||||
spice["msflop_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
||||
spice["msflop_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["msflop_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
spice["dff_setup"] = 9 # DFF setup time in ps
|
||||
spice["dff_hold"] = 1 # DFF hold time in ps
|
||||
spice["dff_delay"] = 20.5 # DFF Clk-to-q delay in ps
|
||||
spice["dff_slew"] = 13.1 # DFF output slew in ps w/ no load
|
||||
spice["dff_in_cap"] = 9.8242 # Input capacitance of ms_flop (Din) [Femto-farad]
|
||||
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
||||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["msflop_leakage"] = 1 # Leakage power of flop in nW
|
||||
spice["flop_para_cap"] = 2 # Parasitic Output capacitance in fF
|
||||
|
||||
spice["default_event_rate"] = 100 # Default event activity of every gate. MHz
|
||||
spice["flop_transition_prob"] = .5 # Transition probability of inverter.
|
||||
spice["inv_transition_prob"] = .5 # Transition probability of inverter.
|
||||
spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input nand.
|
||||
spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand.
|
||||
spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor.
|
||||
|
||||
#Logical Effort relative values for the Handmade cells
|
||||
parameter['le_tau'] = 23 #In pico-seconds.
|
||||
parameter["min_inv_para_delay"] = .73 #In relative delay units
|
||||
parameter['cap_relative_per_ff'] = .91 #Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["static_delay_stages"] = 4
|
||||
parameter["static_fanout_per_stage"] = 3
|
||||
parameter["static_fanout_list"] = parameter["static_delay_stages"]*[parameter["static_fanout_per_stage"]]
|
||||
parameter["dff_clk_cin"] = 27.5 #In relative capacitance units
|
||||
parameter["6tcell_wl_cin"] = 2 #In relative capacitance units
|
||||
parameter["sa_en_pmos_size"] = 24*_lambda_
|
||||
parameter["sa_en_nmos_size"] = 9*_lambda_
|
||||
parameter["sa_inv_pmos_size"] = 18*_lambda_
|
||||
parameter["sa_inv_nmos_size"] = 9*_lambda_
|
||||
parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array
|
||||
parameter['bitcell_drain_cap'] = 0.2 #In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
##END Spice Simulation Parameters
|
||||
###################################################
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
;; NCSU CDK v. 1.6.0.beta
|
||||
;; Last Modified: 2007-07-12
|
||||
|
||||
The NCSU CDK is Copyright (C) NC State University, 1998, 1999, 2004,
|
||||
2006, 2007. Users are free to use or modify the NCSU CDK as appropriate as long
|
||||
as this notice appears in the modified package. The NCSU CDK is
|
||||
provided with NO WARRANTY.
|
||||
|
||||
As of version 1.5.1, all documentation for the NCSU CDK is provided
|
||||
by the NCSU EDA Wiki which can be found at:
|
||||
|
||||
http://www.eda.ncsu.edu/
|
||||
|
||||
This beta release of the kit is to be used in migrating to Cadence Virtuoso 6.1
|
||||
for OpenAccess. Details of the conversion of the CDK from the CDB version can
|
||||
be found in the file cdb2oa/OA_Conversion.txt.
|
||||
|
||||
This kit is not yet fully supported. Please post problems and solutions at
|
||||
http://www.chiptalk.org -> Forums -> NCSU CDK -> NCSU CDK 1.6.0.beta for Virtuoso 6.1
|
||||
|
|
@ -0,0 +1,714 @@
|
|||
drDefineDisplay(
|
||||
;( DisplayName )
|
||||
( display )
|
||||
)
|
||||
drDefineColor(
|
||||
;( DisplayName ColorsName Red Green Blue )
|
||||
( display white 255 255 255 )
|
||||
( display yellow 255 255 0 )
|
||||
( display silver 217 230 255 )
|
||||
( display cream 255 255 204 )
|
||||
( display pink 255 191 242 )
|
||||
( display magenta 255 0 255 )
|
||||
( display lime 0 255 0 )
|
||||
( display tan 255 230 191 )
|
||||
( display cyan 0 255 255 )
|
||||
( display cadetBlue 57 191 255 )
|
||||
( display orange 255 128 0 )
|
||||
( display red 255 51 51 )
|
||||
( display purple 153 0 230 )
|
||||
( display green 0 204 102 )
|
||||
( display brown 191 64 38 )
|
||||
( display blue 51 77 255 )
|
||||
( display slate 140 140 166 )
|
||||
( display gold 217 204 0 )
|
||||
( display maroon 230 31 13 )
|
||||
( display violet 94 0 230 )
|
||||
( display forest 38 140 107 )
|
||||
( display chocolate 128 38 38 )
|
||||
( display navy 51 51 153 )
|
||||
( display black 0 0 0 )
|
||||
( display gray 204 204 217 )
|
||||
( display winColor1 166 166 166 )
|
||||
( display winColor2 115 115 115 )
|
||||
( display winColor3 189 204 204 )
|
||||
( display winColor4 204 204 204 )
|
||||
( display winColor5 199 199 199 )
|
||||
( display blinkRed 255 0 0 t )
|
||||
( display blinkYellow 255 255 0 t )
|
||||
( display blinkWhite 255 255 255 t )
|
||||
( display winBack 224 224 224 )
|
||||
( display winFore 128 0 0 )
|
||||
( display winText 51 51 51 )
|
||||
)
|
||||
drDefineStipple(
|
||||
;( DisplayName StippleName Bitmap )
|
||||
( display dots ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display dots1 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display hLine ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) )
|
||||
( display vLine ( ( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) )
|
||||
( display cross ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) )
|
||||
( display grid ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ) ) )
|
||||
( display slash ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) )
|
||||
( display backSlash ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) )
|
||||
( display hZigZag ( ( 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 )
|
||||
( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 )
|
||||
( 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 )
|
||||
( 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 )
|
||||
( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 )
|
||||
( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 )
|
||||
( 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 )
|
||||
( 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 )
|
||||
( 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 )
|
||||
( 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 ) ) )
|
||||
( display vZigZag ( ( 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 )
|
||||
( 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 )
|
||||
( 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 )
|
||||
( 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 ) ) )
|
||||
( display hCurb ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display vCurb ( ( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) ) )
|
||||
( display brick ( ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 ) ) )
|
||||
( display dagger ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 ) ) )
|
||||
( display triangle ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 )
|
||||
( 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display x ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ) ) )
|
||||
( display stipple0 ( ( 1 ) ) )
|
||||
( display stipple1 ( ( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display stipple2 ( ( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 )
|
||||
( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 )
|
||||
( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 )
|
||||
( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 )
|
||||
( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 )
|
||||
( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 )
|
||||
( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 )
|
||||
( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 )
|
||||
( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 )
|
||||
( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 )
|
||||
( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 )
|
||||
( 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 )
|
||||
( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 )
|
||||
( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 )
|
||||
( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 )
|
||||
( 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ) ) )
|
||||
( display stipple3 ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) )
|
||||
( display stipple4 ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ) ) )
|
||||
( display stipple5 ( ( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) )
|
||||
( display stipple6 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) )
|
||||
( display stipple7 ( ( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 )
|
||||
( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 )
|
||||
( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 )
|
||||
( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 )
|
||||
( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 )
|
||||
( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 )
|
||||
( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 )
|
||||
( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 )
|
||||
( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 )
|
||||
( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 )
|
||||
( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 )
|
||||
( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 )
|
||||
( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 )
|
||||
( 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 )
|
||||
( 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 )
|
||||
( 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 ) ) )
|
||||
( display stipple8 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 ) ) )
|
||||
( display stipple9 ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 )
|
||||
( 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 ) ) )
|
||||
( display stipple10 ( ( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display stipple11 ( ( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 ) ) )
|
||||
( display dots2 ( ( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
( display dots4 ( ( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 ) ) )
|
||||
( display dats5 ( ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 )
|
||||
( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ) ) )
|
||||
)
|
||||
drDefineLineStyle(
|
||||
;( DisplayName LineStyle Size Pattern )
|
||||
( display solid 1 (1 ) )
|
||||
( display dashed 1 (1 1 1 0 0 1 1 1 ) )
|
||||
( display dots 1 (1 0 0 ) )
|
||||
( display dashDot 1 (1 1 1 0 0 1 0 0 ) )
|
||||
( display shortDash 1 (1 1 0 0 ) )
|
||||
( display doubleDash 1 (1 1 1 1 0 0 1 1 0 0 ) )
|
||||
( display hidden 1 (1 0 0 0 ) )
|
||||
( display thickLine 3 (1 1 1 ) )
|
||||
( display lineStyle0 1 (1 ) )
|
||||
( display lineStyle1 1 (1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 ) )
|
||||
)
|
||||
drDefinePacket(
|
||||
;( DisplayName PacketName Stipple LineStyle Fill Outline [FillStyle])
|
||||
( display NwellNet dots4 thickLine slate slate outlineStipple)
|
||||
( display border stipple0 solid tan tan solid )
|
||||
( display y8 stipple0 solid gold gold solid )
|
||||
( display background stipple1 lineStyle0 black black outlineStipple)
|
||||
( display y9 stipple0 solid silver silver solid )
|
||||
( display Metal3Net dots4 solid navy navy outlineStipple)
|
||||
( display A1 stipple0 lineStyle0 winBack winBack solid )
|
||||
( display pin solid lineStyle0 red red solid )
|
||||
( display XPNet blank solid yellow yellow outline )
|
||||
( display hardFence stipple0 solid red red solid )
|
||||
( display PbaseNet dots4 solid yellow yellow outlineStipple)
|
||||
( display designFlow3 stipple1 lineStyle0 pink pink outlineStipple)
|
||||
( display A2 stipple0 lineStyle0 winBack winBack solid )
|
||||
( display Unrouted1 stipple0 lineStyle1 brown brown solid )
|
||||
( display RowLbl blank solid cyan cyan outline )
|
||||
( display edgeLayerPin stipple0 solid yellow yellow solid )
|
||||
( display instance blank solid winBack red outline )
|
||||
( display Nselect dots4 solid green green outlineStipple)
|
||||
( display snap stipple0 solid yellow yellow solid )
|
||||
( display pinAnt stipple0 solid red red solid )
|
||||
( display winAttentionText solid solid winText winText solid )
|
||||
( display designFlow2 stipple1 lineStyle0 purple purple outlineStipple)
|
||||
( display Unrouted2 stipple0 lineStyle1 red red solid )
|
||||
( display hilite blank solid white white outline )
|
||||
( display P2Con solid lineStyle0 orange orange solid )
|
||||
( display designFlow1 stipple1 lineStyle0 red red outlineStipple)
|
||||
( display grid1 stipple0 solid gray gray solid )
|
||||
( display Unrouted3 stipple0 lineStyle1 pink pink solid )
|
||||
( display ViaNet x solid magenta magenta outlineStipple)
|
||||
( display select stipple0 solid tan tan solid )
|
||||
( display Poly2Net dots4 lineStyle0 orange orange outlineStipple)
|
||||
( display winText solid solid winText winText solid )
|
||||
( display Unrouted4 stipple0 lineStyle1 orange orange solid )
|
||||
( display wireLbl solid lineStyle0 cyan cyan solid )
|
||||
( display designFlow7 stipple1 lineStyle0 cyan cyan outlineStipple)
|
||||
( display align stipple0 solid tan tan solid )
|
||||
( display Poly2Pin blank solid yellow yellow outline )
|
||||
( display Unrouted5 stipple0 lineStyle1 green green solid )
|
||||
( display unset stipple0 solid forest forest solid )
|
||||
( display Poly1Net dots4 lineStyle0 red red outlineStipple)
|
||||
( display Resistor dots2 lineStyle0 cyan cyan outlineStipple)
|
||||
( display DiodeNet dots4 lineStyle0 cream cream outlineStipple)
|
||||
( display designFlow6 stipple1 lineStyle0 tan tan outlineStipple)
|
||||
( display Unrouted6 stipple0 lineStyle1 blue blue solid )
|
||||
( display resist stipple0 solid cyan cyan solid )
|
||||
( display designFlow5 stipple1 lineStyle0 silver silver outlineStipple)
|
||||
( display CapWellNet brick solid slate slate outlineStipple)
|
||||
( display Unrouted7 stipple0 lineStyle1 purple purple solid )
|
||||
( display CannotoccupyBnd blank solid red red outline )
|
||||
( display winTopShadow solid solid white white solid )
|
||||
( display designFlow4 stipple1 lineStyle0 black black outlineStipple)
|
||||
( display softFence stipple0 solid yellow yellow solid )
|
||||
( display ResistorNet dots4 solid cyan cyan outlineStipple)
|
||||
( display winError solid solid winColor5 winColor5 solid )
|
||||
( display changedLayerTl1 stipple0 solid yellow yellow solid )
|
||||
( display prBoundaryLbl stipple0 solid purple purple solid )
|
||||
( display ActXNet x solid yellow yellow outlineStipple)
|
||||
( display Pbase stipple10 lineStyle0 yellow yellow outlineStipple)
|
||||
( display Active dots2 lineStyle0 yellow yellow outlineStipple)
|
||||
( display changedLayerTl0 stipple0 solid red red solid )
|
||||
( display spike stipple0 solid purple purple solid )
|
||||
( display Metal3 grid solid navy violet outlineStipple)
|
||||
( display text blank solid white white outline )
|
||||
( display Poly1Pin stipple0 lineStyle0 red red solid )
|
||||
( display Row blank solid cyan cyan outline )
|
||||
( display Pwell stipple9 lineStyle0 slate slate outlineStipple)
|
||||
( display Metal2 stipple5 lineStyle0 magenta magenta outlineStipple)
|
||||
( display wire solid lineStyle0 cyan cyan solid )
|
||||
( display ActX solid solid yellow yellow solid )
|
||||
( display Metal1 stipple6 lineStyle0 cadetBlue cadetBlue outlineStipple)
|
||||
( display Cannotoccupy blank solid red red outline )
|
||||
( display GroupLbl stipple0 solid green green solid )
|
||||
( display axis stipple0 solid slate slate solid )
|
||||
( display SiBlockNet x dashed tan tan outlineStipple)
|
||||
( display edgeLayer stipple0 solid gray gray solid )
|
||||
( display annotate2 stipple0 solid lime lime solid )
|
||||
( display Metal1Pin stipple0 lineStyle0 blue blue solid )
|
||||
( display Diode stipple7 lineStyle0 cream cream outlineStipple)
|
||||
( display Glass X lineStyle0 white white X )
|
||||
( display ViaXNet x solid magenta magenta outlineStipple)
|
||||
( display annotate3 stipple0 solid cyan cyan solid )
|
||||
( display Poly2 dots1 lineStyle0 orange orange outlineStipple)
|
||||
( display deviceAnt stipple0 solid yellow yellow solid )
|
||||
( display winBottomShadow solid solid winColor1 winColor1 solid )
|
||||
( display PselectNet dots4 solid brown brown outlineStipple)
|
||||
( display comment stipple0 lineStyle0 winBack winBack outlineStipple)
|
||||
( display Poly1 dots lineStyle0 red red outlineStipple)
|
||||
( display Unrouted stipple0 lineStyle1 winColor5 winColor5 solid )
|
||||
( display stretch stipple0 solid yellow yellow solid )
|
||||
( display XP blank lineStyle0 winBack gold outline )
|
||||
( display annotate1 stipple0 solid pink pink solid )
|
||||
( display Group stipple2 solid green green outlineStipple)
|
||||
( display deviceLbl stipple0 solid green green solid )
|
||||
( display annotate6 stipple0 solid silver silver solid )
|
||||
( display GlassNet blank solid yellow yellow outline )
|
||||
( display Canplace blank solid cyan cyan outline )
|
||||
( display annotate7 stipple0 solid red red solid )
|
||||
( display Via2 solid solid navy navy solid )
|
||||
( display Metal2Pin stipple0 lineStyle0 magenta magenta solid )
|
||||
( display annotate4 stipple0 solid yellow yellow solid )
|
||||
( display device1 stipple1 lineStyle0 green green outlineStipple)
|
||||
( display "90" blank solid white white outline )
|
||||
( display markerWarn x solid yellow yellow outlineStipple)
|
||||
( display text2 stipple1 lineStyle0 white white outlineStipple)
|
||||
( display CapacitorNet dots4 lineStyle0 tan tan outlineStipple)
|
||||
( display designFlow stipple1 lineStyle0 green green outlineStipple)
|
||||
( display hilite1 stipple0 solid silver silver solid )
|
||||
( display device blank solid green green outline )
|
||||
( display prBoundary stipple0 solid purple purple solid )
|
||||
( display annotate5 stipple0 solid white white solid )
|
||||
( display text1 stipple0 dashed white white solid )
|
||||
( display Via solid solid magenta magenta solid )
|
||||
( display Capacitor stipple7 lineStyle0 tan tan outlineStipple)
|
||||
( display markerErr x solid white white outlineStipple)
|
||||
( display unknown stipple0 solid yellow yellow solid )
|
||||
( display annotate stipple0 solid orange orange solid )
|
||||
( display P1ConNet x solid red red outlineStipple)
|
||||
( display hilite3 stipple0 solid cyan cyan solid )
|
||||
( display winActiveBanner solid solid winColor3 winColor3 solid )
|
||||
( display pinLbl stipple0 solid red red solid )
|
||||
( display device2 stipple0 lineStyle1 green green solid )
|
||||
( display grid stipple0 solid slate slate solid )
|
||||
( display winBackground solid solid winBack winBack solid )
|
||||
( display Metal1Net dots4 lineStyle0 blue blue outlineStipple)
|
||||
( display hilite2 stipple0 solid tan tan solid )
|
||||
( display annotate8 stipple0 solid tan tan solid )
|
||||
( display hilite5 stipple0 solid lime lime solid )
|
||||
( display annotate9 stipple0 solid green green solid )
|
||||
( display Metal2Net dots4 lineStyle0 magenta magenta outlineStipple)
|
||||
( display Metal3Pin stipple0 solid navy navy solid )
|
||||
( display hilite4 stipple0 solid gray gray solid )
|
||||
( display y0 stipple0 solid gray gray solid )
|
||||
( display supply stipple0 solid lime lime solid )
|
||||
( display ActiveNet dots4 lineStyle0 yellow yellow outlineStipple)
|
||||
( display hilite7 stipple0 solid cream cream solid )
|
||||
( display y1 stipple0 solid brown brown solid )
|
||||
( display defaultPacket x solid chocolate winColor2 outlineStipple)
|
||||
( display Via2Net cross solid navy navy outlineStipple)
|
||||
( display NselectNet dots4 solid green green outlineStipple)
|
||||
( display Unrouted8 stipple0 lineStyle1 gold gold solid )
|
||||
( display hilite6 stipple0 solid orange orange solid )
|
||||
( display y2 stipple0 solid red red solid )
|
||||
( display winBorder solid solid winColor2 winColor2 solid )
|
||||
( display Nwell dats5 thickLine slate slate outlineStipple)
|
||||
( display Unrouted9 stipple0 lineStyle1 silver silver solid )
|
||||
( display hilite9 stipple0 solid pink pink solid )
|
||||
( display SiBlock blank dashed tan tan outline )
|
||||
( display y3 stipple0 solid orange orange solid )
|
||||
( display prBoundaryBnd stipple0 solid cyan cyan solid )
|
||||
( display winForeground solid solid winFore winFore solid )
|
||||
( display hilite8 stipple0 solid magenta magenta solid )
|
||||
( display y4 stipple0 solid yellow yellow solid )
|
||||
( display Pselect dots1 solid brown brown outlineStipple)
|
||||
( display winInactiveBanner solid solid winColor4 winColor4 solid )
|
||||
( display designFlow9 stipple1 lineStyle0 orange orange outlineStipple)
|
||||
( display winButton solid solid winFore winFore solid )
|
||||
( display y5 stipple0 solid green green solid )
|
||||
( display hiz stipple0 solid orange orange solid )
|
||||
( display drive stipple0 solid blue blue solid )
|
||||
( display wireFlt stipple0 dashed red red solid )
|
||||
( display instanceLbl stipple0 solid gold gold solid )
|
||||
( display P2ConNet x lineStyle0 orange orange outlineStipple)
|
||||
( display designFlow8 stipple1 lineStyle0 navy navy outlineStipple)
|
||||
( display y6 stipple0 solid blue blue solid )
|
||||
( display PwellNet dots4 lineStyle0 slate slate outlineStipple)
|
||||
( display P1Con solid solid red red solid )
|
||||
( display CapWell dagger solid slate slate outlineStipple)
|
||||
( display y7 stipple0 solid purple purple solid )
|
||||
( display ViaX solid solid magenta magenta solid )
|
||||
( display HR x solid chocolate winColor2 outlineStipple)
|
||||
( display HRnet x solid chocolate winColor2 outlineStipple)
|
||||
)
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
import os
|
||||
CWD = os.environ.get("OPENRAM_TECH") + "/scn3me_subm/tf"
|
||||
ui().importCds("default", CWD+"/display.drf", CWD+"/mosis.tf", 1000, 1, CWD+"/layers.map")
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
Pwell drawing 41 0
|
||||
Nwell drawing 42 0
|
||||
Active drawing 43 0
|
||||
Poly1 drawing 46 0
|
||||
Pselect drawing 45 0
|
||||
Nselect drawing 44 0
|
||||
contact drawing 25 0
|
||||
P1Con drawing 47 0
|
||||
ActX drawing 48 0
|
||||
Metal1 drawing 49 0
|
||||
Via drawing 50 0
|
||||
Metal2 drawing 51 0
|
||||
Via2 drawing 61 0
|
||||
Metal3 drawing 62 0
|
||||
Glass drawing 52 0
|
||||
comment drawing 63 0
|
||||
|
|
@ -0,0 +1,848 @@
|
|||
; Generated on Sep 28 16:05:23 1998
|
||||
; with @(#)$CDS: icfb.exe version 4.4.1 06/17/98 23:40 (cds10067) $
|
||||
;
|
||||
; Matt Clapp fixed: October 10, 2002
|
||||
; added via devices, deleted useless app-specific crap,
|
||||
; added lxExtractRules so undo in layout editor doesn't
|
||||
; complain.
|
||||
|
||||
|
||||
;********************************
|
||||
; LAYER DEFINITION
|
||||
;********************************
|
||||
|
||||
layerDefinitions(
|
||||
techLayers(
|
||||
;( LayerName Layer# Abbreviation )
|
||||
;( --------- ------ ------------ )
|
||||
;User-Defined Layers:
|
||||
( P2Con 3 P2Con )
|
||||
( Poly2 7 Poly2 )
|
||||
( Pbase 10 Pbase )
|
||||
( Resistor 16 Resisto )
|
||||
( Capacitor 17 Capacit )
|
||||
( Diode 18 Diode )
|
||||
( SiBlock 29 SiBlock )
|
||||
( HR 34 HR )
|
||||
( Pwell 41 Pwell )
|
||||
( Nwell 42 Nwell )
|
||||
( Active 43 Active )
|
||||
( Pselect 44 Pselect )
|
||||
( Nselect 45 Nselect )
|
||||
( Poly1 46 Poly1 )
|
||||
( P1Con 47 P1Con )
|
||||
( ActX 48 ActX )
|
||||
( Metal1 49 Metal1 )
|
||||
( Via 50 Via )
|
||||
( Metal2 51 Metal2 )
|
||||
( Glass 52 Glass )
|
||||
( CapWell 59 CapWell )
|
||||
( XP 60 XP )
|
||||
( Via2 61 Via2 )
|
||||
( Metal3 62 Metal3 )
|
||||
( A1 80 A1 )
|
||||
( A2 81 A2 )
|
||||
( comment 117 comment )
|
||||
;System-Reserved Layers:
|
||||
( Unrouted 200 Unroute )
|
||||
( Row 201 Row )
|
||||
( Group 202 Group )
|
||||
( Cannotoccupy 203 Cannoto )
|
||||
( Canplace 204 Canplac )
|
||||
( hardFence 205 hardFen )
|
||||
( softFence 206 softFen )
|
||||
( y0 207 y0 )
|
||||
( y1 208 y1 )
|
||||
( y2 209 y2 )
|
||||
( y3 210 y3 )
|
||||
( y4 211 y4 )
|
||||
( y5 212 y5 )
|
||||
( y6 213 y6 )
|
||||
( y7 214 y7 )
|
||||
( y8 215 y8 )
|
||||
( y9 216 y9 )
|
||||
( designFlow 217 designF )
|
||||
( stretch 218 stretch )
|
||||
( edgeLayer 219 edgeLay )
|
||||
( changedLayer 220 changed )
|
||||
( unset 221 unset )
|
||||
( unknown 222 unknown )
|
||||
( spike 223 spike )
|
||||
( hiz 224 hiz )
|
||||
( resist 225 resist )
|
||||
( drive 226 drive )
|
||||
( supply 227 supply )
|
||||
( wire 228 wire )
|
||||
( pin 229 pin )
|
||||
( text 230 text )
|
||||
( device 231 device )
|
||||
( border 232 border )
|
||||
( snap 233 snap )
|
||||
( align 234 align )
|
||||
( prBoundary 235 prBound )
|
||||
( instance 236 instanc )
|
||||
( annotate 237 annotat )
|
||||
( marker 238 marker )
|
||||
( select 239 select )
|
||||
( grid 251 grid )
|
||||
( axis 252 axis )
|
||||
( hilite 253 hilite )
|
||||
( background 254 backgro )
|
||||
) ;techLayers
|
||||
|
||||
techPurposes(
|
||||
;( PurposeName Purpose# Abbreviation )
|
||||
;( ----------- -------- ------------ )
|
||||
;User-Defined Purposes:
|
||||
;System-Reserved Purposes:
|
||||
( warning 234 wng )
|
||||
( tool1 235 tl1 )
|
||||
( tool0 236 tl0 )
|
||||
( label 237 lbl )
|
||||
( flight 238 flt )
|
||||
( error 239 err )
|
||||
( annotate 240 ant )
|
||||
( drawing1 241 dr1 )
|
||||
( drawing2 242 dr2 )
|
||||
( drawing3 243 dr3 )
|
||||
( drawing4 244 dr4 )
|
||||
( drawing5 245 dr5 )
|
||||
( drawing6 246 dr6 )
|
||||
( drawing7 247 dr7 )
|
||||
( drawing8 248 dr8 )
|
||||
( drawing9 249 dr9 )
|
||||
( boundary 250 bnd )
|
||||
( pin 251 pin )
|
||||
( drawing 252 drw )
|
||||
( net 253 net )
|
||||
( cell 254 cel )
|
||||
( all 255 all )
|
||||
) ;techPurposes
|
||||
|
||||
techLayerPurposePriorities(
|
||||
;layers are ordered from lowest to highest priority
|
||||
; (higher priority is drawn on top of lower priority)
|
||||
;( LayerName Purpose )
|
||||
;( --------- ------- )
|
||||
( background drawing )
|
||||
( grid drawing )
|
||||
( grid drawing1 )
|
||||
( Nwell drawing )
|
||||
( Pwell drawing )
|
||||
( CapWell drawing )
|
||||
( Pselect drawing )
|
||||
( Nselect drawing )
|
||||
( Active drawing )
|
||||
( ActX drawing )
|
||||
( SiBlock drawing )
|
||||
( HR drawing )
|
||||
( Poly1 drawing )
|
||||
( P1Con drawing )
|
||||
( Poly2 drawing )
|
||||
( P2Con drawing )
|
||||
( Metal1 drawing )
|
||||
( Via drawing )
|
||||
( Metal2 drawing )
|
||||
( Via2 drawing )
|
||||
( Metal3 drawing )
|
||||
( annotate drawing )
|
||||
( annotate drawing1 )
|
||||
( annotate drawing2 )
|
||||
( annotate drawing3 )
|
||||
( annotate drawing4 )
|
||||
( annotate drawing5 )
|
||||
( annotate drawing6 )
|
||||
( annotate drawing7 )
|
||||
( annotate drawing8 )
|
||||
( annotate drawing9 )
|
||||
( Poly1 pin )
|
||||
( Metal1 pin )
|
||||
( Metal2 pin )
|
||||
( Metal3 pin )
|
||||
( Glass drawing )
|
||||
( XP drawing )
|
||||
( prBoundary drawing )
|
||||
( prBoundary boundary )
|
||||
( instance drawing )
|
||||
( prBoundary label )
|
||||
( instance label )
|
||||
( Row drawing )
|
||||
( Nwell net )
|
||||
( align drawing )
|
||||
( Pwell net )
|
||||
( CapWell net )
|
||||
( hardFence drawing )
|
||||
( Active net )
|
||||
( softFence drawing )
|
||||
( Row label )
|
||||
( Group drawing )
|
||||
( Group label )
|
||||
( Cannotoccupy drawing )
|
||||
( Cannotoccupy boundary )
|
||||
( Canplace drawing )
|
||||
( ActX net )
|
||||
( A2 drawing )
|
||||
( A1 drawing )
|
||||
( comment drawing )
|
||||
( border drawing )
|
||||
( Pselect net )
|
||||
( Nselect net )
|
||||
( SiBlock net )
|
||||
( HR net )
|
||||
( wire drawing )
|
||||
( Poly1 net )
|
||||
( wire label )
|
||||
( P1Con net )
|
||||
( wire flight )
|
||||
( Metal1 net )
|
||||
( device annotate )
|
||||
( Metal2 net )
|
||||
( device label )
|
||||
( Via net )
|
||||
( Metal3 net )
|
||||
( Via2 net )
|
||||
( pin label )
|
||||
( text drawing )
|
||||
( pin drawing )
|
||||
( text drawing1 )
|
||||
( pin annotate )
|
||||
( device drawing )
|
||||
( axis drawing )
|
||||
( edgeLayer drawing )
|
||||
( edgeLayer pin )
|
||||
( snap drawing )
|
||||
( stretch drawing )
|
||||
( y0 drawing )
|
||||
( y1 drawing )
|
||||
( y2 drawing )
|
||||
( y3 drawing )
|
||||
( y4 drawing )
|
||||
( y5 drawing )
|
||||
( y6 drawing )
|
||||
( y7 drawing )
|
||||
( y8 drawing )
|
||||
( y9 drawing )
|
||||
( hilite drawing )
|
||||
( hilite drawing1 )
|
||||
( hilite drawing2 )
|
||||
( hilite drawing3 )
|
||||
( hilite drawing4 )
|
||||
( hilite drawing5 )
|
||||
( hilite drawing6 )
|
||||
( hilite drawing7 )
|
||||
( hilite drawing8 )
|
||||
( hilite drawing9 )
|
||||
( select drawing )
|
||||
( drive drawing )
|
||||
( hiz drawing )
|
||||
( resist drawing )
|
||||
( spike drawing )
|
||||
( supply drawing )
|
||||
( unknown drawing )
|
||||
( unset drawing )
|
||||
( designFlow drawing )
|
||||
( designFlow drawing1 )
|
||||
( designFlow drawing2 )
|
||||
( designFlow drawing3 )
|
||||
( designFlow drawing4 )
|
||||
( designFlow drawing5 )
|
||||
( designFlow drawing6 )
|
||||
( designFlow drawing7 )
|
||||
( designFlow drawing8 )
|
||||
( designFlow drawing9 )
|
||||
( changedLayer tool0 )
|
||||
( changedLayer tool1 )
|
||||
( marker warning )
|
||||
( marker error )
|
||||
( device drawing1 )
|
||||
( Pbase drawing )
|
||||
( Pbase net )
|
||||
( Resistor net )
|
||||
( Resistor drawing )
|
||||
( Capacitor net )
|
||||
( Capacitor drawing )
|
||||
( Diode net )
|
||||
( Diode drawing )
|
||||
( Poly2 net )
|
||||
( P2Con net )
|
||||
( device drawing2 )
|
||||
( Unrouted drawing )
|
||||
( text drawing2 )
|
||||
( Unrouted drawing1 )
|
||||
( Unrouted drawing2 )
|
||||
( Unrouted drawing3 )
|
||||
( Unrouted drawing4 )
|
||||
( Unrouted drawing5 )
|
||||
( Unrouted drawing6 )
|
||||
( Unrouted drawing7 )
|
||||
( Unrouted drawing8 )
|
||||
( Unrouted drawing9 )
|
||||
) ;techLayerPurposePriorities
|
||||
|
||||
techDisplays(
|
||||
;( LayerName Purpose Packet Vis Sel Con2ChgLy DrgEnbl Valid )
|
||||
;( --------- ------- ------ --- --- --------- ------- ----- )
|
||||
( background drawing background t nil nil nil nil )
|
||||
( grid drawing grid t nil nil nil nil )
|
||||
( grid drawing1 grid1 t nil nil nil nil )
|
||||
( Nwell drawing Nwell t t t t t )
|
||||
( Pwell drawing Pwell t t t t nil )
|
||||
( Active drawing Active t t t t t )
|
||||
( ActX drawing ActX t t t t t )
|
||||
( Pselect drawing Pselect t t t t t )
|
||||
( Nselect drawing Nselect t t t t t )
|
||||
( SiBlock drawing SiBlock t t t t t )
|
||||
( HR drawing HR t t t t t )
|
||||
( CapWell drawing CapWell t t t t t )
|
||||
( Poly1 drawing Poly1 t t t t t )
|
||||
( P1Con drawing P1Con t t t t t )
|
||||
( Metal1 drawing Metal1 t t t t t )
|
||||
( Via drawing Via t t t t t )
|
||||
( Metal2 drawing Metal2 t t t t t )
|
||||
( annotate drawing annotate t t nil t nil )
|
||||
( annotate drawing1 annotate1 t t nil t nil )
|
||||
( annotate drawing2 annotate2 t t nil t nil )
|
||||
( annotate drawing3 annotate3 t t nil t nil )
|
||||
( annotate drawing4 annotate4 t t nil t nil )
|
||||
( annotate drawing5 annotate5 t t nil t nil )
|
||||
( annotate drawing6 annotate6 t t nil t nil )
|
||||
( annotate drawing7 annotate7 t t nil t nil )
|
||||
( annotate drawing8 annotate8 t t nil t nil )
|
||||
( annotate drawing9 annotate9 t t nil t nil )
|
||||
( Via2 drawing Via2 t t t t t )
|
||||
( Metal3 drawing Metal3 t t t t t )
|
||||
( Glass drawing Glass t t t nil t )
|
||||
( XP drawing XP t t t nil t )
|
||||
( Metal1 pin Metal1Pin t t t nil t )
|
||||
( Metal2 pin Metal2Pin t t t nil t )
|
||||
( Metal3 pin Metal3Pin t t t nil t )
|
||||
( Poly1 pin Poly1Pin t t t nil t )
|
||||
( prBoundary drawing prBoundary t t nil t nil )
|
||||
( prBoundary boundary prBoundaryBnd t t nil t nil )
|
||||
( instance drawing instance t t nil t t )
|
||||
( prBoundary label prBoundaryLbl t t t t nil )
|
||||
( instance label instanceLbl t t t t nil )
|
||||
( Row drawing Row t t t t nil )
|
||||
( Nwell net NwellNet t t t nil nil )
|
||||
( align drawing align t t nil t nil )
|
||||
( Pwell net PwellNet t t t nil nil )
|
||||
( CapWell net CapWellNet t t t nil nil )
|
||||
( SiBlock net SiBlockNet t t t nil nil )
|
||||
( HR net HRnet t t t nil nil )
|
||||
( hardFence drawing hardFence t t t t nil )
|
||||
( Active net ActiveNet t t t nil nil )
|
||||
( softFence drawing softFence t t t t nil )
|
||||
( Row label RowLbl t t t t nil )
|
||||
( Group drawing Group t t t t nil )
|
||||
( Group label GroupLbl t t t t nil )
|
||||
( Cannotoccupy drawing Cannotoccupy t t t t nil )
|
||||
( Cannotoccupy boundary CannotoccupyBnd t t t t nil )
|
||||
( Canplace drawing Canplace t t t t nil )
|
||||
( ActX net ActXNet t t t nil nil )
|
||||
( A2 drawing A2 t t t t nil )
|
||||
( A1 drawing A1 t t t t nil )
|
||||
( comment drawing comment t t t t nil )
|
||||
( border drawing border t t t t nil )
|
||||
( Pselect net PselectNet t t t nil nil )
|
||||
( Nselect net NselectNet t t t nil nil )
|
||||
( wire drawing wire t t t t nil )
|
||||
( Poly1 net Poly1Net t t t nil nil )
|
||||
( wire label wireLbl t t t t nil )
|
||||
( P1Con net P1ConNet t t t nil nil )
|
||||
( wire flight wireFlt t t t t nil )
|
||||
( Metal1 net Metal1Net t t t nil nil )
|
||||
( device annotate deviceAnt t t t t nil )
|
||||
( Metal2 net Metal2Net t t t nil nil )
|
||||
( Metal3 net Metal3Net t t t nil nil )
|
||||
( device label deviceLbl t t t t nil )
|
||||
( Via net ViaNet t t t nil nil )
|
||||
( Via2 net Via2Net t t t nil nil )
|
||||
( pin label pinLbl t t t t nil )
|
||||
( text drawing text t t t t t )
|
||||
( pin drawing pin t t t t nil )
|
||||
( text drawing1 text1 t t t t nil )
|
||||
( pin annotate pinAnt t t t t nil )
|
||||
( device drawing device t t t t nil )
|
||||
( axis drawing axis t t t t nil )
|
||||
( edgeLayer drawing edgeLayer t t nil t nil )
|
||||
( edgeLayer pin edgeLayerPin t t nil t nil )
|
||||
( snap drawing snap t t nil t nil )
|
||||
( stretch drawing stretch t t nil t nil )
|
||||
( y0 drawing y0 t t nil t nil )
|
||||
( y1 drawing y1 t t nil t nil )
|
||||
( y2 drawing y2 t t nil t nil )
|
||||
( y3 drawing y3 t t nil t nil )
|
||||
( y4 drawing y4 t t nil t nil )
|
||||
( y5 drawing y5 t t nil t nil )
|
||||
( y6 drawing y6 t t nil t nil )
|
||||
( y7 drawing y7 t t nil t nil )
|
||||
( y8 drawing y8 t t nil t nil )
|
||||
( y9 drawing y9 t t nil t nil )
|
||||
( hilite drawing hilite t t nil t nil )
|
||||
( hilite drawing1 hilite1 t t t t nil )
|
||||
( hilite drawing2 hilite2 t t nil t nil )
|
||||
( hilite drawing3 hilite3 t t t t nil )
|
||||
( hilite drawing4 hilite4 t t t t nil )
|
||||
( hilite drawing5 hilite5 t t t t nil )
|
||||
( hilite drawing6 hilite6 t t t t nil )
|
||||
( hilite drawing7 hilite7 t t t t nil )
|
||||
( hilite drawing8 hilite8 t t t t nil )
|
||||
( hilite drawing9 hilite9 t t t t nil )
|
||||
( select drawing select t t nil t nil )
|
||||
( drive drawing drive t t t t nil )
|
||||
( hiz drawing hiz t t t t nil )
|
||||
( resist drawing resist t t t t nil )
|
||||
( spike drawing spike t t t t nil )
|
||||
( supply drawing supply t t t t nil )
|
||||
( unknown drawing unknown t t t t nil )
|
||||
( unset drawing unset t t t t nil )
|
||||
( designFlow drawing designFlow t t t nil nil )
|
||||
( designFlow drawing1 designFlow1 t t t nil nil )
|
||||
( designFlow drawing2 designFlow2 t t t nil nil )
|
||||
( designFlow drawing3 designFlow3 t t t nil nil )
|
||||
( designFlow drawing4 designFlow4 t t t nil nil )
|
||||
( designFlow drawing5 designFlow5 t t t nil nil )
|
||||
( designFlow drawing6 designFlow6 t t t nil nil )
|
||||
( designFlow drawing7 designFlow7 t t t nil nil )
|
||||
( designFlow drawing8 designFlow8 t t t nil nil )
|
||||
( designFlow drawing9 designFlow9 t t t nil nil )
|
||||
( changedLayer tool0 changedLayerTl0 nil nil nil nil nil )
|
||||
( changedLayer tool1 changedLayerTl1 nil nil t nil nil )
|
||||
( marker warning markerWarn t t t t nil )
|
||||
( marker error markerErr t t t t nil )
|
||||
( device drawing1 device1 t t t t nil )
|
||||
( Poly2 net Poly2Net t t t nil nil )
|
||||
( Poly2 drawing Poly2 t t t t t )
|
||||
( P2Con net P2ConNet t t t nil nil )
|
||||
( P2Con drawing P2Con t t t t t )
|
||||
( Pbase net PbaseNet t t t nil nil )
|
||||
( Pbase drawing Pbase t t t t t )
|
||||
( Resistor net ResistorNet t t t nil nil )
|
||||
( Resistor drawing Resistor t t t t t )
|
||||
( Capacitor net CapacitorNet t t t nil nil )
|
||||
( Capacitor drawing Capacitor t t t t t )
|
||||
( Diode net DiodeNet t t t nil nil )
|
||||
( Diode drawing Diode t t t t t )
|
||||
( device drawing2 device2 t t t t nil )
|
||||
( Unrouted drawing Unrouted t t t t nil )
|
||||
( text drawing2 text2 t t t t nil )
|
||||
( Unrouted drawing1 Unrouted1 t t t t nil )
|
||||
( Unrouted drawing2 Unrouted2 t t t t nil )
|
||||
( Unrouted drawing3 Unrouted3 t t t t nil )
|
||||
( Unrouted drawing4 Unrouted4 t t t t nil )
|
||||
( Unrouted drawing5 Unrouted5 t t t t nil )
|
||||
( Unrouted drawing6 Unrouted6 t t t t nil )
|
||||
( Unrouted drawing7 Unrouted7 t t t t nil )
|
||||
( Unrouted drawing8 Unrouted8 t t t t nil )
|
||||
( Unrouted drawing9 Unrouted9 t t t t nil )
|
||||
) ;techDisplays
|
||||
|
||||
; I don't think the following is necessary (or used!)
|
||||
techLayerProperties(
|
||||
;( PropName Layer1 [ Layer2 ] PropValue )
|
||||
( contactLimit P2Con 10000 )
|
||||
( eqPinLimit P2Con 10000 )
|
||||
( horizontalJogLength P2Con 2147483648.000000 )
|
||||
( routingGrid P2Con 1.000000 )
|
||||
( verticalJogLength P2Con 2147483648.000000 )
|
||||
( routingGrid Poly2 1.000000 )
|
||||
( contactLimit Active 10000 )
|
||||
( eqPinLimit Active 10000 )
|
||||
( horizontalJogLength Active 2147483648.000000 )
|
||||
( routingGrid Active 1.000000 )
|
||||
( verticalJogLength Active 2147483648.000000 )
|
||||
( routingGrid Poly1 1.000000 )
|
||||
( contactLimit P1Con 10000 )
|
||||
( eqPinLimit P1Con 10000 )
|
||||
( horizontalJogLength P1Con 2147483648.000000 )
|
||||
( routingGrid P1Con 1.000000 )
|
||||
( verticalJogLength P1Con 2147483648.000000 )
|
||||
( contactLimit ActX 10000 )
|
||||
( eqPinLimit ActX 10000 )
|
||||
( horizontalJogLength ActX 2147483648.000000 )
|
||||
( routingGrid ActX 1.000000 )
|
||||
( verticalJogLength ActX 2147483648.000000 )
|
||||
( routingGrid Metal1 1.000000 )
|
||||
( contactLimit Via 10000 )
|
||||
( eqPinLimit Via 10000 )
|
||||
( horizontalJogLength Via 2147483648.000000 )
|
||||
( routingGrid Via 1.000000 )
|
||||
( verticalJogLength Via 2147483648.000000 )
|
||||
( routingGrid Metal2 1.000000 )
|
||||
)
|
||||
|
||||
) ;layerDefinitions
|
||||
|
||||
|
||||
;********************************
|
||||
; DEVICE RULES
|
||||
;********************************
|
||||
|
||||
devices(
|
||||
tcCreateCDSDeviceClass()
|
||||
|
||||
symContactDevice(
|
||||
;( deviceName viaLayer viaPurpose
|
||||
( VIA Via drawing
|
||||
|
||||
; layer1 purpose1 [implant1]
|
||||
Metal1 drawing
|
||||
|
||||
; layer2 purpose2 [implant2]
|
||||
Metal2 drawing
|
||||
|
||||
; width length [( row column xPitch yPitch xBias yBias )]
|
||||
; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ )
|
||||
2 2
|
||||
|
||||
; encLayer1 encLayer2 legalRegion )
|
||||
1 1 _NA_)
|
||||
) ;symContactDevice
|
||||
|
||||
symContactDevice(
|
||||
;( deviceName viaLayer viaPurpose
|
||||
( VIA2 Via2 drawing
|
||||
|
||||
; layer1 purpose1 [implant1]
|
||||
Metal2 drawing
|
||||
|
||||
; layer2 purpose2 [implant2]
|
||||
Metal3 drawing
|
||||
|
||||
; width length [( row column xPitch yPitch xBias yBias )]
|
||||
; 2 2 ( 1 1 _NA_ _NA_ _NA_ _NA_ )
|
||||
2 2
|
||||
|
||||
; encLayer1 encLayer2 legalRegion )
|
||||
1 2 _NA_)
|
||||
) ;symContactDevice
|
||||
|
||||
) ;devices
|
||||
|
||||
|
||||
;********************************
|
||||
; LAYER RULES
|
||||
;********************************
|
||||
|
||||
layerRules(
|
||||
streamLayers(
|
||||
;( layer streamNumber dataType translate )
|
||||
;( ----- ------------ -------- --------- )
|
||||
( ("background" "drawing") 0 0 nil )
|
||||
( ("grid" "drawing") 0 0 nil )
|
||||
( ("grid" "drawing1") 0 0 nil )
|
||||
( ("Nwell" "drawing") 42 0 t )
|
||||
( ("Pwell" "drawing") 41 0 t )
|
||||
( ("Active" "drawing") 43 0 t )
|
||||
( ("ActX" "drawing") 48 0 t )
|
||||
( ("Pselect" "drawing") 44 0 t )
|
||||
( ("Nselect" "drawing") 45 0 t )
|
||||
( ("Poly1" "drawing") 46 0 t )
|
||||
( ("P1Con" "drawing") 47 0 t )
|
||||
( ("Metal1" "drawing") 49 0 t )
|
||||
( ("Metal2" "drawing") 51 0 t )
|
||||
( ("annotate" "drawing") 0 0 nil )
|
||||
( ("annotate" "drawing1") 0 0 nil )
|
||||
( ("annotate" "drawing2") 0 0 nil )
|
||||
( ("annotate" "drawing3") 0 0 nil )
|
||||
( ("annotate" "drawing4") 0 0 nil )
|
||||
( ("annotate" "drawing5") 0 0 nil )
|
||||
( ("annotate" "drawing6") 0 0 nil )
|
||||
( ("annotate" "drawing7") 0 0 nil )
|
||||
( ("annotate" "drawing8") 0 0 nil )
|
||||
( ("annotate" "drawing9") 0 0 nil )
|
||||
( ("Via" "drawing") 50 0 t )
|
||||
( ("Glass" "drawing") 52 0 t )
|
||||
( ("XP" "drawing") 60 0 t )
|
||||
( ("Metal2" "pin") 0 0 nil )
|
||||
( ("Poly1" "pin") 0 0 nil )
|
||||
( ("prBoundary" "drawing") 0 0 nil )
|
||||
( ("Metal1" "pin") 0 0 nil )
|
||||
( ("prBoundary" "boundary") 0 0 nil )
|
||||
( ("instance" "drawing") 246 0 nil )
|
||||
( ("instance" "label") 0 0 nil )
|
||||
( ("Nwell" "net") 0 0 nil )
|
||||
( ("align" "drawing") 0 0 nil )
|
||||
( ("Pwell" "net") 0 0 nil )
|
||||
( ("hardFence" "drawing") 0 0 nil )
|
||||
( ("Active" "net") 0 0 nil )
|
||||
( ("softFence" "drawing") 0 0 nil )
|
||||
( ("ActX" "net") 0 0 nil )
|
||||
( ("A2" "drawing") 5 0 nil )
|
||||
( ("A1" "drawing") 2 0 nil )
|
||||
( ("comment" "drawing") 0 0 nil )
|
||||
( ("border" "drawing") 0 0 nil )
|
||||
( ("Pselect" "net") 0 0 nil )
|
||||
( ("Nselect" "net") 0 0 nil )
|
||||
( ("wire" "drawing") 0 0 nil )
|
||||
( ("Poly1" "net") 0 0 nil )
|
||||
( ("P1Con" "net") 0 0 nil )
|
||||
( ("Metal1" "net") 0 0 nil )
|
||||
( ("Metal2" "net") 0 0 nil )
|
||||
( ("device" "label") 0 0 nil )
|
||||
( ("Via" "net") 0 0 nil )
|
||||
( ("pin" "label") 0 0 nil )
|
||||
( ("text" "drawing") 63 0 t )
|
||||
( ("pin" "drawing") 0 0 nil )
|
||||
( ("device" "drawing") 0 0 nil )
|
||||
( ("axis" "drawing") 0 0 nil )
|
||||
( ("edgeLayer" "drawing") 0 0 nil )
|
||||
( ("edgeLayer" "pin") 0 0 nil )
|
||||
( ("snap" "drawing") 0 0 nil )
|
||||
( ("stretch" "drawing") 0 0 nil )
|
||||
( ("y0" "drawing") 0 0 nil )
|
||||
( ("y1" "drawing") 0 0 nil )
|
||||
( ("y2" "drawing") 0 0 nil )
|
||||
( ("y3" "drawing") 0 0 nil )
|
||||
( ("y4" "drawing") 0 0 nil )
|
||||
( ("y5" "drawing") 0 0 nil )
|
||||
( ("y6" "drawing") 0 0 nil )
|
||||
( ("y7" "drawing") 0 0 nil )
|
||||
( ("y8" "drawing") 0 0 nil )
|
||||
( ("y9" "drawing") 0 0 nil )
|
||||
( ("hilite" "drawing") 0 0 nil )
|
||||
( ("hilite" "drawing2") 0 0 nil )
|
||||
( ("select" "drawing") 0 0 nil )
|
||||
( ("drive" "drawing") 0 0 nil )
|
||||
( ("hiz" "drawing") 0 0 nil )
|
||||
( ("resist" "drawing") 0 0 nil )
|
||||
( ("spike" "drawing") 0 0 nil )
|
||||
( ("supply" "drawing") 0 0 nil )
|
||||
( ("unknown" "drawing") 0 0 nil )
|
||||
( ("unset" "drawing") 0 0 nil )
|
||||
( ("changedLayer" "tool0") 0 0 nil )
|
||||
( ("Resistor" "net") 0 0 nil )
|
||||
( ("Resistor" "drawing") 0 0 nil )
|
||||
( ("Capacitor" "net") 0 0 nil )
|
||||
( ("Capacitor" "drawing") 0 0 nil )
|
||||
( ("Diode" "net") 0 0 nil )
|
||||
( ("Diode" "drawing") 0 0 nil )
|
||||
( ("Poly2" "net") 0 0 nil )
|
||||
( ("Poly2" "drawing") 0 0 nil )
|
||||
( ("P2Con" "net") 0 0 nil )
|
||||
( ("P2Con" "drawing") 0 0 nil )
|
||||
( ("Pbase" "drawing") 0 0 nil )
|
||||
( ("Pbase" "net") 0 0 nil )
|
||||
( P2Con 0 0 nil )
|
||||
( Poly2 0 0 nil )
|
||||
( Pwell 0 0 nil )
|
||||
( Nwell 0 0 nil )
|
||||
( Active 0 0 nil )
|
||||
( Pselect 0 0 nil )
|
||||
( Nselect 0 0 nil )
|
||||
( Poly1 0 0 nil )
|
||||
( P1Con 0 0 nil )
|
||||
( ActX 0 0 nil )
|
||||
( Metal1 0 0 nil )
|
||||
( Via 0 0 nil )
|
||||
( Metal2 0 0 nil )
|
||||
( Glass 0 0 nil )
|
||||
( XP 0 0 nil )
|
||||
( ("Via2" "drawing") 50 0 t )
|
||||
( ("Via2" "net") 0 0 nil )
|
||||
( ("Metal3" "drawing") 50 0 t )
|
||||
( ("Metal3" "net") 0 0 nil )
|
||||
( ("Metal3" "pin") 0 0 nil )
|
||||
( ("CapWell" "drawing") 0 0 nil )
|
||||
( ("CapWell" "net") 0 0 nil )
|
||||
( ("SiBlock" "drawing") 0 0 nil )
|
||||
( ("SiBlock" "net") 0 0 nil )
|
||||
( ("HR" "drawing") 0 0 nil )
|
||||
( ("HR" "net") 0 0 nil )
|
||||
) ;streamLayers
|
||||
|
||||
viaLayers(
|
||||
;( layer1 viaLayer layer2 )
|
||||
;( ------ -------- ------ )
|
||||
( Metal2 Via2 Metal3 )
|
||||
( Metal1 Via Metal2 )
|
||||
( Active ActX Poly1 )
|
||||
( Poly1 P1Con Metal1 )
|
||||
( Poly2 P2Con Metal1 )
|
||||
) ;viaLayers
|
||||
|
||||
) ;layerRules
|
||||
|
||||
|
||||
;********************************
|
||||
; PHYSICAL RULES
|
||||
;********************************
|
||||
|
||||
physicalRules(
|
||||
orderedSpacingRules(
|
||||
;( rule layer1 layer2 value )
|
||||
;( ---- ------ ------ ----- )
|
||||
( minEnclosure "prBoundary" "Metal1" 0.0 )
|
||||
( minEnclosure "Metal2" "Via" 1.0 )
|
||||
( minEnclosure "Metal1" "Via" 1.0 )
|
||||
( minEnclosure "Metal1" "P1Con" 1.0 )
|
||||
( minEnclosure "Metal1" "ActX" 1.0 )
|
||||
( minEnclosure "Nselect" "Active" 2.0 )
|
||||
( minEnclosure "Pselect" "Active" 2.0 )
|
||||
( minEnclosure "Active" "ActX" 1.0 )
|
||||
( minEnclosure "Pwell" "Active" 5.0 )
|
||||
( minEnclosure "Nwell" "Active" 5.0 )
|
||||
) ;orderedSpacingRules
|
||||
|
||||
spacingRules(
|
||||
;( rule layer1 layer2 value )
|
||||
;( ---- ------ ------ ----- )
|
||||
( minSpacing "P2Con" 2.0 )
|
||||
( minSpacing "Poly2" 3.0 )
|
||||
( minSpacing "Pwell" 9.0 )
|
||||
( minSpacing "Nwell" 9.0 )
|
||||
( minSpacing "Active" 3.0 )
|
||||
( minSpacing "Pselect" 2.0 )
|
||||
( minSpacing "Nselect" 2.0 )
|
||||
( minSpacing "Poly1" 2.0 )
|
||||
( minSpacing "P1Con" 2.0 )
|
||||
( minSpacing "ActX" 2.0 )
|
||||
( minSpacing "Metal1" 3.0 )
|
||||
( minSpacing "Via" 3.0 )
|
||||
( minSpacing "Via2" 3.0 )
|
||||
( minSpacing "Metal2" 3.0 )
|
||||
( minSpacing "Metal3" 4.0 )
|
||||
( minSpacing "Glass" 75.0 )
|
||||
( minSpacing "XP" 100.0 )
|
||||
( minSpacing "Metal2" 4.0 )
|
||||
( minSpacing "P1Con" "Via" 2.0 )
|
||||
( minSpacing "ActX" "Via" 2.0 )
|
||||
( minSpacing "ActX" "P2Con" 2.0 )
|
||||
( minSpacing "Poly2" "P2Con" 4.0 )
|
||||
( minSpacing "Poly1" "P1Con" 4.0 )
|
||||
( minSpacing "ActX" "P1Con" 2.0 )
|
||||
( minSpacing "Active" "P1Con" 2.0 )
|
||||
( minSpacing "Active" "Poly2" 2.0 )
|
||||
( minSpacing "Poly1" "Poly2" 2.0 )
|
||||
( minSpacing "Active" "Poly1" 2.0 )
|
||||
( minSpacing "ActX" "Poly1" 2.0 )
|
||||
( minSpacing "Pselect" "Nselect" 0.0 )
|
||||
( minSpacing "Nwell" "Pwell" 9.0 )
|
||||
( minWidth "P2Con" 2.0 )
|
||||
( minWidth "Poly2" 3.0 )
|
||||
( minWidth "Pwell" 10.0 )
|
||||
( minWidth "Nwell" 10.0 )
|
||||
( minWidth "Active" 3.0 )
|
||||
( minWidth "Pselect" 2.0 )
|
||||
( minWidth "Nselect" 2.0 )
|
||||
( minWidth "Poly1" 2.0 )
|
||||
( minWidth "P1Con" 2.0 )
|
||||
( minWidth "ActX" 2.0 )
|
||||
( minWidth "Metal1" 4.0 )
|
||||
( minWidth "Via" 2.0 )
|
||||
( minWidth "Metal2" 4.0 )
|
||||
( minWidth "Glass" 75.0 )
|
||||
( minWidth "XP" 100.0 )
|
||||
( minWidth "Metal3" 6.0 )
|
||||
) ;spacingRules
|
||||
|
||||
mfgGridResolution(
|
||||
( 1.000000 )
|
||||
) ;mfgGridResolution
|
||||
|
||||
) ;physicalRules
|
||||
|
||||
|
||||
;********************************
|
||||
; ELECTRICAL RULES
|
||||
;********************************
|
||||
|
||||
electricalRules(
|
||||
characterizationRules(
|
||||
;( rule layer1 layer2 value )
|
||||
;( ---- ------ ------ ----- )
|
||||
( areaCap "P2Con" 0.0 )
|
||||
( areaCap "Poly2" 0.0 )
|
||||
( areaCap "Active" 0.0 )
|
||||
( areaCap "Poly1" 6e-05 )
|
||||
( areaCap "P1Con" 0.0 )
|
||||
( areaCap "ActX" 0.0 )
|
||||
( areaCap "Metal1" 2.6e-05 )
|
||||
( areaCap "Via" 0.0 )
|
||||
( areaCap "Metal2" 1.6e-05 )
|
||||
( edgeCapacitance "P2Con" 0.0 )
|
||||
( edgeCapacitance "Poly2" 0.0 )
|
||||
( edgeCapacitance "Active" 0.0 )
|
||||
( edgeCapacitance "Poly1" 0.0 )
|
||||
( edgeCapacitance "P1Con" 0.0 )
|
||||
( edgeCapacitance "ActX" 0.0 )
|
||||
( edgeCapacitance "Metal1" 0.0 )
|
||||
( edgeCapacitance "Via" 0.0 )
|
||||
( edgeCapacitance "Metal2" 0.0 )
|
||||
( sheetRes "P2Con" 0.0 )
|
||||
( sheetRes "Poly2" 0.0 )
|
||||
( sheetRes "Active" 0.0 )
|
||||
( sheetRes "Poly1" 23.0 )
|
||||
( sheetRes "P1Con" 0.0 )
|
||||
( sheetRes "ActX" 0.0 )
|
||||
( sheetRes "Metal1" 0.04 )
|
||||
( sheetRes "Via" 0.0 )
|
||||
( sheetRes "Metal2" 0.07 )
|
||||
( currentDensity "P2Con" 1.0 )
|
||||
( currentDensity "Poly2" 1.0 )
|
||||
( currentDensity "Active" 1.0 )
|
||||
( currentDensity "Poly1" 1.0 )
|
||||
( currentDensity "P1Con" 1.0 )
|
||||
( currentDensity "ActX" 1.0 )
|
||||
( currentDensity "Metal1" 1.0 )
|
||||
( currentDensity "Via" 1.0 )
|
||||
( currentDensity "Metal2" 1.0 )
|
||||
) ;characterizationRules
|
||||
|
||||
) ;electricalRules
|
||||
|
||||
|
||||
;********************************
|
||||
; LAYOUT EDITOR RULES
|
||||
;********************************
|
||||
; specifies the ordering of the layers in the LSW
|
||||
|
||||
leRules(
|
||||
leLswLayers(
|
||||
;( layer purpose )
|
||||
; ----- ------- )
|
||||
( Nwell drawing )
|
||||
( Pselect drawing )
|
||||
( Nselect drawing )
|
||||
( Active drawing )
|
||||
( ActX drawing )
|
||||
( Poly1 drawing )
|
||||
( P1Con drawing )
|
||||
( Metal1 drawing )
|
||||
( Via drawing )
|
||||
( Metal2 drawing )
|
||||
( Via2 drawing )
|
||||
( Metal3 drawing )
|
||||
( Poly1 pin )
|
||||
( Metal1 pin )
|
||||
( Metal2 pin )
|
||||
( Metal3 pin )
|
||||
( Poly2 drawing )
|
||||
( P2Con drawing )
|
||||
( instance drawing )
|
||||
( text drawing )
|
||||
( CapWell drawing )
|
||||
( SiBlock drawing )
|
||||
( HR drawing )
|
||||
( Pbase drawing )
|
||||
( Resistor drawing )
|
||||
( Capacitor drawing )
|
||||
( Diode drawing )
|
||||
( Glass drawing )
|
||||
( XP drawing )
|
||||
|
||||
) ;leLswLayers
|
||||
) ;leRules
|
||||
|
||||
|
||||
;********************************
|
||||
; VIRTUOSO XL RULES
|
||||
;********************************
|
||||
; specifies the ordering of the layers in the LSW
|
||||
|
||||
lxRules(
|
||||
lxExtractLayers(
|
||||
(Metal1 Metal2 Metal3)
|
||||
) ;lxExtractLayers
|
||||
) ;lxRules
|
||||
|
||||
|
|
@ -9,7 +9,7 @@ import os
|
|||
from design_rules import *
|
||||
|
||||
"""
|
||||
File containing the process technology parameters for SCMOS 3me, subm, 180nm.
|
||||
File containing the process technology parameters for SCMOS 4m, 0.35um
|
||||
"""
|
||||
|
||||
#GDS file info
|
||||
|
|
|
|||
Loading…
Reference in New Issue