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OpenRAM
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Remove +1 to induce error.

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mrg 2019-05-31 10:55:17 -07:00
parent d789f93743
commit 301f032619
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/bank.py
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@ -352,7 +352,7 @@ class bank(design.design):
self.addr_size = self.col_addr_size + self.row_addr_size
debug.check(self.num_rows*self.num_cols==self.word_size*self.num_words,"Invalid bank sizes.")
debug.check(1+self.addr_size==self.col_addr_size + self.row_addr_size,"Invalid address break down.")
debug.check(self.addr_size==self.col_addr_size + self.row_addr_size,"Invalid address break down.")
# Width for the vdd/gnd rails
self.supply_rail_width = 4*self.m2_width