mirror of https://github.com/VLSIDA/OpenRAM.git
Begin adding wmask netlist and spice tests.
This commit is contained in:
jsowash
parent
5258016c9f
commit
dfa2b29b8f
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@ -37,13 +37,27 @@ class functional(simulation):
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#self.set_feasible_period(sram, spfile, corner)
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self.set_stimulus_variables()
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self.create_signal_names()
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self.initilize_wmask()
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# Number of checks can be changed
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self.num_cycles = 2
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self.stored_words = {}
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self.write_check = []
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self.read_check = []
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def initilize_wmask(self):
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self.wmask = [None]*self.num_wmask
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self.num_wmask = int(self.word_size/self.write_size)
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self.wmask_enabled = False
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if self.word_size !=self.write_size:
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self.wmask_enabled = True
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# initialize first wmask bit to 1, otherwise 0
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for bit in range(self.num_wmask):
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if bit == 0:
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self.wmask[self.num_wmask-1 - bit] = 1
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else:
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self.wmask[self.num_wmask-1 - bit] = 0
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print(self.wmask)
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def run(self, feasible_period=None):
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if feasible_period: #period defaults to tech.py feasible period otherwise.
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@ -71,23 +85,44 @@ class functional(simulation):
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check = 0
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# First cycle idle
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comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, 0, self.t_current)
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comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, 0, self.wmask, self.t_current)
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self.add_noop_all_ports(comment, "0"*self.addr_size, "0"*self.word_size)
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# Write at least once
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addr = self.gen_addr()
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word = self.gen_data()
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comment = self.gen_cycle_comment("write", word, addr, 0, self.t_current)
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self.add_write(comment, addr, word, 0)
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self.stored_words[addr] = word
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comment = self.gen_cycle_comment("write", word, addr, 0, self.wmask, self.t_current)
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self.add_write(comment, addr, word, self.wmask, 0)
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if self.wmask_enabled:
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old_word = ""
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if self.stored_words.get(addr) == None:
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for i in range(self.word_size):
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old_word += "X"
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else:
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old_word = self.stored_words[addr]
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for bit in self.wmask:
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# Don't write the bits of the new word to the address
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if self.wmask[bit] == 0:
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lower = bit * self.write_size
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upper = lower + self.write_size - 1
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if bit == self.num_wmask-1:
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word = word[0:lower] + old_word[lower:upper+1]
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elif bit == 0:
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word = old_word[lower:upper+1] + word [upper+1:self.word_size]
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else:
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word = word[0:lower] + old_word[lower:upper+1] + word [upper+1:self.word_size]cfusms
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#word = word.replace(word[lower:upper+1],old_word[lower:upper+1],1)
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self.stored_words[addr] = word
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else:
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self.stored_words[addr] = word
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# Read at least once. For multiport, it is important that one read cycle uses all RW and R port to read from the same address simultaniously.
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# This will test the viablilty of the transistor sizing in the bitcell.
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for port in self.all_ports:
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if port in self.write_ports:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port)
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else:
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comment = self.gen_cycle_comment("read", word, addr, port, self.t_current)
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comment = self.gen_cycle_comment("read", word, addr, port, self.wmask, self.t_current)
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self.add_read_one_port(comment, addr, rw_read_din_data, port)
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self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check])
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check += 1
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@ -95,6 +130,7 @@ class functional(simulation):
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self.t_current += self.period
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# Perform a random sequence of writes and reads on random ports, using random addresses and random words
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# and random write masks (if applicable)
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for i in range(self.num_cycles):
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w_addrs = []
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for port in self.all_ports:
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@ -112,11 +148,12 @@ class functional(simulation):
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elif op == "write":
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addr = self.gen_addr()
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word = self.gen_data()
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wmask = self.gen_wmask()
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port)
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else:
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comment = self.gen_cycle_comment("write", word, addr, port, self.t_current)
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comment = self.gen_cycle_comment("write", word, addr, port, wmask, self.t_current)
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self.add_write_one_port(comment, addr, word, port)
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self.stored_words[addr] = word
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w_addrs.append(addr)
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@ -126,7 +163,7 @@ class functional(simulation):
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, port)
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else:
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comment = self.gen_cycle_comment("read", word, addr, port, self.t_current)
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comment = self.gen_cycle_comment("read", word, addr, port, self.wmask, self.t_current)
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self.add_read_one_port(comment, addr, rw_read_din_data, port)
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self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check])
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check += 1
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@ -135,7 +172,7 @@ class functional(simulation):
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self.t_current += self.period
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# Last cycle idle needed to correctly measure the value on the second to last clock edge
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comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, 0, self.t_current)
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comment = self.gen_cycle_comment("noop", "0"*self.word_size, "0"*self.addr_size, 0, self.wmask, self.t_current)
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self.add_noop_all_ports(comment, "0"*self.addr_size, "0"*self.word_size)
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def read_stim_results(self):
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@ -170,7 +207,14 @@ class functional(simulation):
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self.read_check[i][2])
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return(0, error)
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return(1, "SUCCESS")
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def gen_wmask(self):
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wmask_bits = [None]*self.num_wmask
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for bit in range(self.num_wmask):
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rand = random.randint(0, 1)
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wmask_bits[bit] = rand
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return wmask_bits
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def gen_data(self):
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""" Generates a random word to write. """
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rand = random.randint(0,(2**self.word_size)-1)
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@ -34,6 +34,10 @@ class simulation():
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self.readwrite_ports = self.sram.readwrite_ports
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self.read_ports = self.sram.read_ports
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self.write_ports = self.sram.write_ports
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self.num_wmask = int(self.word_size/self.write_size)
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self.wmask_enabled = False
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if self.word_size !=self.write_size:
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self.wmask_enabled = True
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def set_corner(self,corner):
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""" Set the corner values """
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@ -127,7 +131,7 @@ class simulation():
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debug.error("Non-binary address string",1)
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bit -= 1
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def add_write(self, comment, address, data, port):
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def add_write(self, comment, address, data, wmask, port):
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""" Add the control values for a write cycle. """
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debug.check(port in self.write_ports, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_ports))
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debug.info(2, comment)
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@ -223,18 +227,28 @@ class simulation():
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time_spacing,
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comment))
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def gen_cycle_comment(self, op, word, addr, port, t_current):
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def gen_cycle_comment(self, op, word, addr, port, wmask, t_current):
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if op == "noop":
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comment = "\tIdle during cycle {0} ({1}ns - {2}ns)".format(int(t_current/self.period),
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t_current,
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t_current+self.period)
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elif op == "write":
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comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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t_current,
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t_current+self.period)
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if (self.wmask_enabled):
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comment = "\tWriting {0} to address {1} with mask bit {0} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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wmask,
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port,
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int(
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t_current / self.period),
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t_current + self.period)
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else:
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comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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port,
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int(t_current/self.period),
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t_current,
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t_current+self.period)
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else:
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comment = "\tReading {0} from address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
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addr,
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@ -268,7 +282,9 @@ class simulation():
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if (port in read_index) and (port in write_index):
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pin_names.append("WEB{0}".format(port))
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if (self.write_size != self.word_size):
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pin_names.append("WMASK{0}".format(port))
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num_wmask = int(self.word_size/self.write_size)
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for bit in range(num_wmask):
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pin_names.append("WMASK{0}_{1}".format(port,bit))
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for port in range(total_ports):
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pin_names.append("{0}{1}".format(tech.spice["clk"], port))
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@ -759,8 +759,6 @@ class control_logic(design.design):
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def route_dffs(self):
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if self.port_type == "rw":
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#print("hi")
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#if (self.word_size == self.write_size):
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dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"])
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elif self.port_type == "r":
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dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"])
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@ -187,9 +187,15 @@ class multibank(design.design):
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words_per_row=self.words_per_row)
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self.add_mod(self.sense_amp_array)
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self.write_driver_array = self.mod_write_driver_array(columns=self.num_cols,
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word_size=self.word_size)
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self.add_mod(self.write_driver_array)
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if (self.write_size != self.word_size):
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self.write_mask_driver_array = self.mod_write_mask_driver_array(columns=self.num_cols,
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word_size=self.word_size,
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write_size=self.write_size)
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self.add_mod(self.write_mask_driver_array)
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else:
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self.write_driver_array = self.mod_write_driver_array(columns=self.num_cols,
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word_size=self.word_size)
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self.add_mod(self.write_driver_array)
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self.row_decoder = self.mod_decoder(rows=self.num_rows)
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self.add_mod(self.row_decoder)
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@ -21,6 +21,7 @@ class port_data(design.design):
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sram_config.set_local_config(self)
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self.port = port
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self.num_wmask = int(self.word_size/self.write_size)
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if name == "":
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name = "port_data_{0}".format(self.port)
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@ -53,6 +54,8 @@ class port_data(design.design):
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if self.write_driver_array:
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self.create_write_driver_array()
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if (self.word_size != self.write_size):
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self.create_write_mask_array()
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else:
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self.write_driver_array_inst = None
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@ -164,6 +167,12 @@ class port_data(design.design):
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columns=self.num_cols,
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word_size=self.word_size)
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self.add_mod(self.write_driver_array)
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if (self.word_size != self.write_size):
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self.write_mask_array = factory.create(module_type="write_mask_array",
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columns=self.num_cols,
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word_size=self.word_size,
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write_size=self.write_size)
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self.add_mod(self.write_driver_array)
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else:
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self.write_driver_array = None
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@ -279,6 +288,18 @@ class port_data(design.design):
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temp.extend(["w_en", "vdd", "gnd"])
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self.connect_inst(temp)
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def create_write_mask_array(self):
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""" Creating Write Masks """
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self.write_mask_array_inst = self.add_inst(name="write_mask_array{}".format(self.port),
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mod=self.write_mask_array)
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temp = []
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for bit in range(self.num_wmask):
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temp.append("write_mask_".format(bit))
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temp.extend(["w_en", "vdd", "gnd"])
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self.connect_inst(temp)
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def place_write_driver_array(self, offset):
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""" Placing Write Driver """
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@ -0,0 +1,158 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log
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import design
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from tech import drc
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import debug
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class write_mask_array(design.design):
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"""
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Array of tristate drivers to write to the bitlines through the column mux.
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Dynamically generated write driver array of all bitlines.
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"""
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def __init__(self, name, columns, word_size, write_size):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("columns: {0}".format(columns))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("write_size {0}".format(write_size))
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self.columns = columns
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self.word_size = word_size
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self.write_size = write_size
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self.words_per_row = int(columns / word_size)
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self.num_wmask = int(word_size / write_size)
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self.create_netlist()
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# if not OPTS.netlist_only:
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# self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_write_mask_array()
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self.create_and2_array()
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# def create_layout(self):
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#
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# if self.bitcell.width > self.driver.width:
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# self.width = self.columns * self.bitcell.width
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# else:
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# self.width = self.columns * self.driver.width
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#
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# self.height = self.driver.height
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#
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# self.place_write_array()
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# self.add_layout_pins()
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# self.add_boundary()
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# self.DRC_LVS()
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def add_pins(self):
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for bit in range(self.num_wmask):
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self.add_pin("wdriver_sel_{}".format(bit))
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self.add_pin("en")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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self.wmask = factory.create(module_type="dff_buf")
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self.add_mod(self.wmask)
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dff_height = self.wmask.height
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self.and2 = factory.create(module_type="pand2",
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size=4,
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height=dff_height)
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self.add_mod(self.and2)
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def create_write_mask_array(self):
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self.wmask_insts = {}
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for bit in range(self.num_wmask):
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name = "write_mask_{}".format(bit)
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self.wmask_insts[bit] = self.add_inst(name=name,
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mod=self.wmask)
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self.connect_inst(["wmask_{}".format(bit),
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"bank_wmask_{}".format(bit),
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"bank_wmask_bar_{}".format(bit),
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"clk", "vdd", "gnd"])
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def create_and2_array(self):
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self.and2_insts = {}
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for bit in range(self.num_wmask):
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name = "and2_{}".format(bit)
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self.and2_insts[bit] = self.add_inst(name=name,
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mod=self.and2)
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self.connect_inst(["bank_wmask_{}".format(bit),
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"en",
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"wdriver_sel_{}".format(bit),
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"vdd", "gnd"])
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# def place_write_array(self):
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# if self.bitcell.width > self.driver.width:
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# driver_spacing = self.bitcell.width
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# else:
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# driver_spacing = self.driver.width
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#
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# for i in range(0, self.columns, self.words_per_row):
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# index = int(i / self.words_per_row)
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# base = vector(i * driver_spacing, 0)
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# self.driver_insts[index].place(base)
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# def add_layout_pins(self):
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# for i in range(self.word_size):
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# din_pin = self.driver_insts[i].get_pin("din")
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# self.add_layout_pin(text="data_{0}".format(i),
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# layer="metal2",
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# offset=din_pin.ll(),
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# width=din_pin.width(),
|
||||
# height=din_pin.height())
|
||||
# bl_pin = self.driver_insts[i].get_pin("bl")
|
||||
# self.add_layout_pin(text="bl_{0}".format(i),
|
||||
# layer="metal2",
|
||||
# offset=bl_pin.ll(),
|
||||
# width=bl_pin.width(),
|
||||
# height=bl_pin.height())
|
||||
#
|
||||
# br_pin = self.driver_insts[i].get_pin("br")
|
||||
# self.add_layout_pin(text="br_{0}".format(i),
|
||||
# layer="metal2",
|
||||
# offset=br_pin.ll(),
|
||||
# width=br_pin.width(),
|
||||
# height=br_pin.height())
|
||||
#
|
||||
# for n in ["vdd", "gnd"]:
|
||||
# pin_list = self.driver_insts[i].get_pins(n)
|
||||
# for pin in pin_list:
|
||||
# pin_pos = pin.center()
|
||||
# # Add the M2->M3 stack
|
||||
# self.add_via_center(layers=("metal2", "via2", "metal3"),
|
||||
# offset=pin_pos)
|
||||
# self.add_layout_pin_rect_center(text=n,
|
||||
# layer="metal3",
|
||||
# offset=pin_pos)
|
||||
#
|
||||
# self.add_layout_pin(text="en",
|
||||
# layer="metal1",
|
||||
# offset=self.driver_insts[0].get_pin("en").ll().scale(0, 1),
|
||||
# width=self.width,
|
||||
# height=drc('minwidth_metal1'))
|
||||
|
||||
# def get_w_en_cin(self):
|
||||
# """Get the relative capacitance of all the enable connections in the bank"""
|
||||
# # The enable is connected to a nand2 for every row.
|
||||
# return self.driver.get_w_en_cin() * len(self.driver_insts)
|
||||
|
||||
|
||||
|
|
@ -128,9 +128,9 @@ class sram_1bank(sram_base):
|
|||
# Add the write mask flops to the left of the din flops.
|
||||
if (self.write_size != self.word_size):
|
||||
if port in self.write_ports:
|
||||
wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
|
||||
self.bank.height + max_gap_size + self.data_dff_insts[port].height)
|
||||
self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX")
|
||||
wmask_pos[port] = vector(self.bank.bank_array_ll.x - self.control_logic_insts[port].width,
|
||||
-max_gap_size - self.wmask_dff_insts[port].height)
|
||||
self.wmask_dff_insts[port].place(wmask_pos[port])
|
||||
|
||||
|
||||
if len(self.all_ports)>1:
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@ class sram_base(design, verilog, lef):
|
|||
|
||||
def add_pins(self):
|
||||
""" Add pins for entire SRAM. """
|
||||
self.num_masks = int(self.word_size/self.write_size)
|
||||
for port in self.write_ports:
|
||||
for bit in range(self.word_size):
|
||||
self.add_pin("DIN{0}[{1}]".format(port,bit),"INPUT")
|
||||
|
|
@ -71,7 +72,8 @@ class sram_base(design, verilog, lef):
|
|||
# add the optional write mask pins
|
||||
if self.word_size != self.write_size:
|
||||
for port in self.write_ports:
|
||||
self.add_pin("wmask{}".format(port),"INPUT")
|
||||
for bit in range(self.num_masks):
|
||||
self.add_pin("wmask{0}[{1}]".format(port,bit),"INPUT")
|
||||
for port in self.read_ports:
|
||||
for bit in range(self.word_size):
|
||||
self.add_pin("DOUT{0}[{1}]".format(port,bit),"OUTPUT")
|
||||
|
|
@ -149,7 +151,7 @@ class sram_base(design, verilog, lef):
|
|||
elif "metal3" in tech.layer:
|
||||
from supply_tree_router import supply_tree_router as router
|
||||
rtr=router(("metal3",), self)
|
||||
|
||||
|
||||
rtr.route()
|
||||
|
||||
|
||||
|
|
@ -278,8 +280,10 @@ class sram_base(design, verilog, lef):
|
|||
self.data_dff = dff_array(name="data_dff", rows=1, columns=self.word_size)
|
||||
self.add_mod(self.data_dff)
|
||||
|
||||
self.wmask_dff = dff_array(name="wmask_dff", rows=1, columns=int(self.word_size/self.write_size))
|
||||
self.add_mod(self.wmask_dff)
|
||||
if (self.write_size != self.word_size):
|
||||
num_wmask = int(self.word_size/self.write_size)
|
||||
self.wmask_dff = dff_array(name="wmask_dff", rows=1, columns=num_wmask)
|
||||
self.add_mod(self.wmask_dff)
|
||||
|
||||
|
||||
# Create the bank module (up to four are instantiated)
|
||||
|
|
@ -469,7 +473,7 @@ class sram_base(design, verilog, lef):
|
|||
outputs = []
|
||||
for bit in range(num_wmask):
|
||||
inputs.append("wmask{}[{}]".format(port, bit))
|
||||
outputs.append("BANK_WMASK{}[{}]".format(port, bit))
|
||||
outputs.append("bank_wmask{}[{}]".format(port, bit))
|
||||
|
||||
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2019 Regents of the University of California and The Board
|
||||
# of Regents for the Oklahoma Agricultural and Mechanical College
|
||||
# (acting for and on behalf of Oklahoma State University)
|
||||
# All rights reserved.
|
||||
#
|
||||
import unittest
|
||||
from testutils import *
|
||||
import sys,os
|
||||
sys.path.append(os.getenv("OPENRAM_HOME"))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
from sram_factory import factory
|
||||
import debug
|
||||
|
||||
#@unittest.skip("SKIPPING sram_wmask_func_test")
|
||||
class sram_wmask_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_{0}".format(OPTS.tech_name))
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
||||
# This is a hack to reload the characterizer __init__ with the spice version
|
||||
from importlib import reload
|
||||
import characterizer
|
||||
reload(characterizer)
|
||||
from characterizer import functional, delay
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=8,
|
||||
num_words=16,
|
||||
write_size=4,
|
||||
num_banks=1)
|
||||
c.words_per_row=4
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} bit writes, {} banks".format(c.word_size,
|
||||
c.num_words,
|
||||
c.words_per_row,
|
||||
c.write_size,
|
||||
c.num_banks))
|
||||
s = factory.create(module_type="sram", sram_config=c)
|
||||
tempspice = OPTS.openram_temp + "temp.sp"
|
||||
s.sp_write(tempspice)
|
||||
|
||||
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
|
||||
|
||||
f = functional(s.s, tempspice, corner)
|
||||
f.num_cycles = 10
|
||||
(fail, error) = f.run()
|
||||
self.assertTrue(fail, error)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
# run the test from the command line
|
||||
if __name__ == "__main__":
|
||||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
Loading…
Reference in New Issue