mirror of https://github.com/VLSIDA/OpenRAM.git
Fix replica array pin names
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mrg
parent
8815ddf7f1
commit
2271946eef
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@ -32,11 +32,7 @@ class replica_bitcell_array(design.design):
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self.left_rbl = left_rbl
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self.right_rbl = right_rbl
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# FIXME: If we want more than 2 ports of RBL, we also need to modify
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# replica_column to support this. Right now, it only supports a single
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# RBL and is used for both the left and right column (right is flipped).
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#debug.check(self.left_rbl<=1,"Only one RBL supported now.")
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#debug.check(self.right_rbl<=1,"Only one RBL supported now.")
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debug.check(left_rbl+right_rbl==len(self.read_ports),"Invalid number of RBLs for port configuration.")
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# Two dummy rows/cols plus replica for each port
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self.extra_rows = 2 + left_rbl + right_rbl
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@ -122,50 +118,69 @@ class replica_bitcell_array(design.design):
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def add_pins(self):
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self.wl_names = [x for x in self.bitcell_array.pins if x.startswith("w")]
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self.bl_names = [x for x in self.bitcell_array.pins if x.startswith("b")]
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self.bitcell_array_wl_names = [x for x in self.bitcell_array.pins if x.startswith("w")]
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self.bitcell_array_bl_names = [x for x in self.bitcell_array.pins if x.startswith("b")]
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# These are the non-indexed names
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self.replica_cell_wl_names = ["rbl_"+x for x in self.cell.list_all_wl_names()]
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self.dummy_cell_wl_names = ["dummy_"+x for x in self.cell.list_all_wl_names()]
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self.dummy_cell_bl_names = ["dummy_"+x for x in self.cell.list_all_bitline_names()]
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self.dummy_row_bl_names = self.bl_names
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self.dummy_row_bl_names = self.bitcell_array_bl_names
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self.rbl_bl_names = []
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self.rbl_wl_names = []
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for port in range(self.left_rbl+self.right_rbl):
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self.rbl_bl_names.append("rbl_bl{}".format(port))
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self.rbl_wl_names.append("rbl_wl{}".format(port))
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# Create the full WL names include dummy, replica, and regular bit cells
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self.replica_col_wl_names = []
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self.replica_col_wl_names.extend(["{0}_bot".format(x) for x in self.dummy_cell_wl_names])
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# Left port WLs (one dummy for each port when we allow >1 port)
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for bit in range(self.left_rbl):
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self.replica_col_wl_names.extend(["rbl_{0}_{1}".format(x,bit) for x in self.cell.list_all_wl_names()])
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for port in range(self.left_rbl):
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# Make names for all RBLs
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wl_names = ["rbl_{0}_{1}".format(x,port) for x in self.cell.list_all_wl_names()]
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# Rename the one we will use
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wl_names[port] = self.rbl_wl_names[port]
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self.replica_col_wl_names.extend(wl_names)
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# Regular WLs
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self.replica_col_wl_names.extend(self.wl_names)
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self.replica_col_wl_names.extend(self.bitcell_array_wl_names)
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# Right port WLs (one dummy for each port when we allow >1 port)
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for bit in range(self.left_rbl,self.left_rbl+self.right_rbl):
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self.replica_col_wl_names.extend(["rbl_{0}_{1}".format(x,bit) for x in self.cell.list_all_wl_names()])
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for port in range(self.left_rbl,self.left_rbl+self.right_rbl):
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# Make names for all RBLs
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wl_names = ["rbl_{0}_{1}".format(x,port) for x in self.cell.list_all_wl_names()]
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# Rename the one we will use
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wl_names[port] = self.rbl_wl_names[port]
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self.replica_col_wl_names.extend(wl_names)
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self.replica_col_wl_names.extend(["{0}_top".format(x) for x in self.dummy_cell_wl_names])
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# Left/right dummy columns are connected identically to the replica column
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self.dummy_col_wl_names = self.replica_col_wl_names
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# Per bit bitline names
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self.replica_bl_names_list = {}
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self.replica_wl_names_list = {}
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# Array of all bitline names
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self.replica_bl_names = []
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self.replica_wl_names = []
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for bit in range(self.left_rbl+self.right_rbl):
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self.replica_bl_names_list[bit] = ["rbl_{0}_{1}".format(x,bit) for x in self.cell.list_all_bitline_names()]
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self.replica_bl_names.extend(self.replica_bl_names_list[bit])
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# Per port bitline names
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self.replica_bl_names = {}
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self.replica_wl_names = {}
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# Array of all port bitline names
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for port in range(self.left_rbl+self.right_rbl):
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left_names = ["rbl_{0}_{1}".format(x,port) for x in self.cell.list_all_bl_names()]
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right_names = ["rbl_{0}_{1}".format(x,port) for x in self.cell.list_all_br_names()]
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left_names[port] = self.rbl_bl_names[port]
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# Interleave the left and right lists
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bl_names = [x for t in zip(left_names, right_names) for x in t]
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self.replica_bl_names[port] = bl_names
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self.replica_wl_names_list[bit] = ["{0}_{1}".format(x,bit) for x in self.replica_cell_wl_names]
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self.replica_wl_names.extend(self.replica_wl_names_list[bit])
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wl_names = ["rbl_{0}_{1}".format(x,port) for x in self.cell.list_all_wl_names()]
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wl_names[port] = "rbl_wl{}".format(port)
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self.replica_wl_names[port] = wl_names
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self.add_pin_list(self.bl_names)
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self.add_pin_list(self.replica_bl_names)
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self.add_pin_list(self.wl_names)
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self.add_pin_list(self.replica_wl_names)
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# External pins
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self.add_pin_list(self.bitcell_array_bl_names, "INOUT")
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for port in range(self.left_rbl+self.right_rbl):
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self.add_pin("rbl_bl{}".format(port),"INPUT")
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self.add_pin_list(self.bitcell_array_wl_names, "INPUT")
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for port in range(self.left_rbl+self.right_rbl):
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self.add_pin("rbl_wl{}".format(port),"OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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@ -182,27 +197,22 @@ class replica_bitcell_array(design.design):
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.bitcell_array.pins)
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self.connect_inst(self.bitcell_array_bl_names + self.bitcell_array_wl_names + supplies)
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# Replica columns
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self.replica_col_inst = {}
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for bit in range(self.left_rbl):
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self.replica_col_inst[bit]=self.add_inst(name="replica_col_left_{}".format(bit),
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mod=self.replica_columns[bit])
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self.connect_inst(self.replica_bl_names_list[bit] + self.replica_col_wl_names + supplies)
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for bit in range(self.left_rbl,self.left_rbl+self.right_rbl):
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self.replica_col_inst[bit]=self.add_inst(name="replica_col_right_{}".format(bit),
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mod=self.replica_columns[bit])
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self.connect_inst(self.replica_bl_names_list[bit] + self.replica_col_wl_names + supplies)
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for port in range(self.left_rbl+self.right_rbl):
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self.replica_col_inst[port]=self.add_inst(name="replica_col_{}".format(port),
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mod=self.replica_columns[port])
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self.connect_inst(self.replica_bl_names[port] + self.replica_col_wl_names + supplies)
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# Replica rows with replica bitcell
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# Dummy rows under the bitcell array (connected with with the replica cell wl)
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self.dummy_row_replica_inst = {}
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for bit in range(self.left_rbl+self.right_rbl):
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self.dummy_row_replica_inst[bit]=self.add_inst(name="dummy_row_{}".format(bit),
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mod=self.dummy_row)
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self.connect_inst(self.dummy_row_bl_names + self.replica_wl_names_list[bit] + supplies)
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for port in range(self.left_rbl+self.right_rbl):
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self.dummy_row_replica_inst[port]=self.add_inst(name="dummy_row_{}".format(port),
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mod=self.dummy_row)
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self.connect_inst(self.dummy_row_bl_names + self.replica_wl_names[port] + supplies)
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# Top/bottom dummy rows
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@ -298,34 +308,37 @@ class replica_bitcell_array(design.design):
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# Replica wordlines
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for bit in range(self.left_rbl+self.right_rbl):
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inst = self.replica_col_inst[bit]
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for (pin_name,wl_name) in zip(self.cell.list_all_wl_names(),self.replica_wl_names_list[bit]):
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for port in range(self.left_rbl+self.right_rbl):
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inst = self.replica_col_inst[port]
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for (pin_name,wl_name) in zip(self.cell.list_all_wl_names(),self.replica_wl_names[port]):
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# +1 for dummy row
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pin_bit = bit+1
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pin_bit = port+1
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# +row_size if above the array
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if bit>=self.left_rbl:
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if port>=self.left_rbl:
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pin_bit += self.row_size
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pin_name += "_{}".format(pin_bit)
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pin = inst.get_pin(pin_name)
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self.add_layout_pin(text=wl_name,
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layer=pin.layer,
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offset=pin.ll().scale(0,1),
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width=self.width,
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height=pin.height())
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if wl_name in self.rbl_wl_names:
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self.add_layout_pin(text=wl_name,
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layer=pin.layer,
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offset=pin.ll().scale(0,1),
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width=self.width,
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height=pin.height())
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# Replica bitlines
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for bit in range(self.left_rbl+self.right_rbl):
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inst = self.replica_col_inst[bit]
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for (pin_name, bl_name) in zip(self.cell.list_all_bitline_names(),self.replica_bl_names_list[bit]):
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for port in range(self.left_rbl+self.right_rbl):
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inst = self.replica_col_inst[port]
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for (pin_name, bl_name) in zip(self.cell.list_all_bitline_names(),self.replica_bl_names[port]):
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pin = inst.get_pin(pin_name)
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name = "rbl_{0}_{1}".format(pin_name,bit)
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self.add_layout_pin(text=name,
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layer=pin.layer,
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offset=pin.ll().scale(1,0),
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width=pin.width(),
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height=self.height)
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name = "rbl_{0}_{1}".format(pin_name,port)
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if bl_name in self.rbl_bl_names:
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self.add_layout_pin(text=name,
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layer=pin.layer,
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offset=pin.ll().scale(1,0),
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width=pin.width(),
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height=self.height)
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for pin_name in ["vdd","gnd"]:
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@ -335,32 +348,7 @@ class replica_bitcell_array(design.design):
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self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer)
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# Non-pins
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for side in ["bot", "top"]:
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inst = getattr(self, "dummy_row_{}_inst".format(side))
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pin_names = inst.mod.get_pin_names()
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for pin_name in pin_names:
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if pin_name.startswith("wl"):
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pin_list = inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_rect(layer=pin.layer,
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offset=pin.ll().scale(0,1),
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width=self.width,
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height=pin.height())
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for side in ["left", "right"]:
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inst = getattr(self, "dummy_col_{}_inst".format(side))
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pin_names = inst.mod.get_pin_names()
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for pin_name in pin_names:
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if pin_name.startswith("b"):
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pin_list = inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_rect(layer=pin.layer,
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offset=pin.ll().scale(1,0),
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width=pin.width(),
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height=self.height)
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