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OpenRAM
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Clean up multiport test options to be consistent.

This commit is contained in:
mrg 2019-07-12 10:39:55 -07:00
parent aa552f8e96
commit 17d144b5b5
14 changed files with 37 additions and 17 deletions
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3
compiler/modules/control_logic.py
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@ -365,9 +365,8 @@ class control_logic(design.design):
self.create_wlen_row()
if (self.port_type == "rw") or (self.port_type == "w"):
self.create_wen_row()
if self.port_type == "rw":
self.create_rbl_row()
if (self.port_type == "rw") or (self.port_type == "r"):
self.create_rbl_row()
self.create_pen_row()
self.create_sen_row()
self.create_delay()

9
compiler/tests/05_bitcell_1rw_1r_array_test.py
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@ -21,13 +21,16 @@ class bitcell_1rw_1r_array_test(openram_test):
def runTest(self):
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)

7
compiler/tests/05_replica_bitcell_1rw_1r_array_test.py
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@ -16,12 +16,15 @@ import debug
class replica_bitcell_array_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=1)
self.local_check(a)

9
compiler/tests/19_single_bank_1rw_1r_test.py
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@ -18,13 +18,16 @@ import debug
class single_bank_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=16)

9
compiler/tests/19_single_bank_1w_1r_test.py
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@ -18,13 +18,16 @@ import debug
class single_bank_1w_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "bitcell_1w_1r"
OPTS.replica_bitcell = "replica_bitcell_1w_1r"
OPTS.dummy_bitcell="dummy_bitcell_1w_1r"
OPTS.num_rw_ports = 0
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=16)

3
compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
View File

@ -21,9 +21,10 @@ class psram_1bank_2mux_1rw_1w_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 1
OPTS.num_r_ports = 0

3
compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
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@ -21,9 +21,10 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1

1
compiler/tests/20_psram_1bank_2mux_test.py
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@ -23,6 +23,7 @@ class psram_1bank_2mux_test(openram_test):
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
# testing layout of sram using pbitcell with 1 RW port (a 6T-cell equivalent)
OPTS.num_rw_ports = 1

3
compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
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@ -20,9 +20,10 @@ class psram_1bank_4mux_1rw_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1

1
compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
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@ -23,6 +23,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0

3
compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
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@ -21,9 +21,10 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from sram_config import sram_config
OPTS.bitcell = "bitcell_1w_1r"
OPTS.replica_bitcell="replica_bitcell_1w_1r"
OPTS.dummy_bitcell="dummy_bitcell_1w_1r"
OPTS.num_rw_ports = 0
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1

1
compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
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@ -23,6 +23,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0

1
compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
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@ -23,6 +23,7 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.dummy_bitcell = "dummy_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0

1
compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py
View File

@ -25,6 +25,7 @@ class psram_1bank_nomux_func_test(openram_test):
OPTS.trim_netlist = False
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.dummy_bitcell="dummy_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1