mirror of https://github.com/VLSIDA/OpenRAM.git
Fix SCN3ME_SUBM stuff.
Update cells to be DRC clean with rule 5.5.b Allow magic for FreePDK45 but not debugged. Revert to older Magic tech file for SCN3ME_SUBM
This commit is contained in:
parent
9bb5041d93
commit
26146b6838
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@ -33,9 +33,6 @@ else:
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OPTS.lvs_exe = get_tool("LVS", ["calibre","assura","netgen"], OPTS.lvs_name)
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OPTS.pex_exe = get_tool("PEX", ["calibre","magic"], OPTS.pex_name)
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if OPTS.check_lvsdrc and OPTS.tech_name == "freepdk45":
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debug.check(OPTS.drc_exe[0]!="magic","Magic does not support FreePDK45 for DRC.")
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if OPTS.drc_exe == None:
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from .none import run_drc,print_drc_stats
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elif "calibre"==OPTS.drc_exe[0]:
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@ -1,6 +1,6 @@
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magic
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tech scmos
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timestamp 1558915277
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timestamp 1558933786
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<< nwell >>
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rect 0 48 54 77
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<< pwell >>
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@ -22,8 +22,10 @@ rect 13 34 14 38
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rect 16 34 17 38
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rect 21 34 22 38
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rect 17 30 22 34
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rect 24 30 25 38
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rect 29 30 30 38
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rect 24 36 30 38
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rect 24 32 25 36
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rect 29 32 30 36
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rect 24 30 30 32
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rect 32 34 33 38
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rect 37 34 38 38
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rect 40 34 41 38
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@ -31,8 +33,10 @@ rect 32 30 37 34
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rect 9 21 14 23
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rect 13 17 14 21
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rect 16 17 22 23
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rect 24 17 25 23
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rect 29 17 30 23
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rect 24 22 30 23
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rect 24 18 25 22
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rect 29 18 30 22
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rect 24 17 30 18
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rect 32 17 38 23
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rect 40 21 45 23
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rect 40 17 41 21
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@ -44,11 +48,11 @@ rect 32 56 33 59
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<< ndcontact >>
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rect 9 34 13 38
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rect 17 34 21 38
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rect 25 30 29 38
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rect 25 32 29 36
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rect 33 34 37 38
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rect 41 34 45 38
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rect 9 17 13 21
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rect 25 17 29 23
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rect 25 18 29 22
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rect 41 17 45 21
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<< pdcontact >>
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rect 17 56 21 60
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@ -57,17 +61,17 @@ rect 33 56 37 60
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<< psubstratepcontact >>
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rect 25 9 29 13
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<< nsubstratencontact >>
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rect 25 70 29 74
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rect 37 70 41 74
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<< polysilicon >>
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rect 22 59 24 62
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rect 30 59 32 62
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rect 22 45 24 56
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rect 30 53 32 56
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rect 13 41 16 45
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rect 13 41 16 43
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rect 14 38 16 41
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rect 22 38 24 41
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rect 30 38 32 49
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rect 38 41 41 45
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rect 38 41 41 43
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rect 38 38 40 41
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rect 14 32 16 34
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rect 38 32 40 34
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@ -88,26 +92,26 @@ rect 12 24 16 28
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rect 38 24 42 28
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<< metal1 >>
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rect 0 70 25 74
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rect 29 70 54 74
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rect 29 70 37 74
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rect 41 70 54 74
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rect 0 63 54 67
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rect 6 45 10 63
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rect 9 45 13 63
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rect 16 56 17 60
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rect 37 56 38 60
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rect 16 53 20 56
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rect 16 49 28 53
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rect 6 41 9 45
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rect 16 38 19 49
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rect 35 45 38 56
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rect 44 45 48 63
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rect 26 41 38 45
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rect 45 41 48 45
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rect 41 45 45 63
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rect 35 38 38 41
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rect 6 34 9 38
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rect 16 34 17 38
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rect 25 36 29 38
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rect 37 34 38 38
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rect 45 34 48 38
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rect 25 23 29 30
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rect 25 13 29 17
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rect 25 22 29 32
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rect 25 13 29 18
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rect 0 9 25 13
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rect 29 9 54 13
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rect 0 2 16 6
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@ -139,12 +143,14 @@ rect 48 0 52 34
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<< comment >>
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rect 0 0 54 72
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<< labels >>
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rlabel metal1 27 4 27 4 1 wl1
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rlabel psubstratepcontact 27 11 27 11 1 gnd
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rlabel metal2 4 7 4 7 2 bl0
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rlabel metal2 11 7 11 7 1 bl1
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rlabel metal2 43 7 43 7 1 br1
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rlabel metal2 50 7 50 7 8 br0
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rlabel metal1 19 72 19 72 5 vdd
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rlabel metal1 19 65 19 65 1 wl0
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rlabel metal1 27 4 27 4 4 wl1
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rlabel psubstratepcontact 27 11 27 11 4 gnd
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rlabel metal2 4 7 4 7 4 bl0
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rlabel metal2 50 7 50 7 4 br0
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rlabel metal1 19 65 19 65 4 wl0
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rlabel metal2 11 7 11 7 4 bl1
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rlabel metal2 43 7 43 7 4 br1
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rlabel metal1 18 72 18 72 1 vdd
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<< properties >>
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string path 0.000 0.000 243.000 0.000 243.000 324.000 0.000 324.000 0.000 0.000
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<< end >>
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@ -1,6 +1,6 @@
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magic
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tech scmos
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timestamp 1558915277
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timestamp 1558933786
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<< nwell >>
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rect 0 48 54 77
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<< pwell >>
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@ -22,8 +22,10 @@ rect 13 34 14 38
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rect 16 34 17 38
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rect 21 34 22 38
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rect 17 30 22 34
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rect 24 30 25 38
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rect 29 30 30 38
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rect 24 36 30 38
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rect 24 32 25 36
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rect 29 32 30 36
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rect 24 30 30 32
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rect 32 34 33 38
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rect 37 34 38 38
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rect 40 34 41 38
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@ -31,8 +33,10 @@ rect 32 30 37 34
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rect 9 21 14 23
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rect 13 17 14 21
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rect 16 17 22 23
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rect 24 17 25 23
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rect 29 17 30 23
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rect 24 22 30 23
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rect 24 18 25 22
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rect 29 18 30 22
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rect 24 17 30 18
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rect 32 17 38 23
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rect 40 21 45 23
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rect 40 17 41 21
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@ -44,11 +48,11 @@ rect 32 56 33 59
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<< ndcontact >>
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rect 9 34 13 38
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rect 17 34 21 38
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rect 25 30 29 38
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rect 25 32 29 36
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rect 33 34 37 38
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rect 41 34 45 38
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rect 9 17 13 21
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rect 25 17 29 23
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rect 25 18 29 22
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rect 41 17 45 21
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<< pdcontact >>
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rect 17 56 21 60
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@ -57,17 +61,17 @@ rect 33 56 37 60
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<< psubstratepcontact >>
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rect 25 9 29 13
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<< nsubstratencontact >>
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rect 25 70 29 74
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rect 37 70 41 74
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<< polysilicon >>
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rect 22 59 24 62
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rect 30 59 32 62
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rect 22 45 24 56
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rect 30 53 32 56
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rect 13 41 16 45
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rect 13 41 16 43
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rect 14 38 16 41
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rect 22 38 24 41
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rect 30 38 32 49
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rect 38 41 41 45
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rect 38 41 41 43
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rect 38 38 40 41
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rect 14 32 16 34
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rect 38 32 40 34
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@ -88,26 +92,26 @@ rect 12 24 16 28
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rect 38 24 42 28
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<< metal1 >>
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rect 0 70 25 74
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rect 29 70 54 74
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rect 29 70 37 74
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rect 41 70 54 74
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rect 0 63 54 67
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rect 6 45 10 63
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rect 9 45 13 63
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rect 16 56 17 60
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rect 37 56 38 60
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rect 16 53 20 56
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rect 16 49 28 53
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rect 6 41 9 45
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rect 16 38 19 49
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rect 35 45 38 56
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rect 44 45 48 63
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rect 26 41 38 45
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rect 45 41 48 45
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rect 41 45 45 63
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rect 35 38 38 41
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rect 6 34 9 38
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rect 16 34 17 38
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rect 25 36 29 38
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rect 37 34 38 38
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rect 45 34 48 38
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rect 25 23 29 30
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rect 25 13 29 17
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rect 25 22 29 32
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rect 25 13 29 18
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rect 0 9 25 13
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rect 29 9 54 13
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rect 0 2 16 6
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@ -139,12 +143,14 @@ rect 48 0 52 34
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<< comment >>
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rect 0 0 54 72
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<< labels >>
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rlabel metal1 27 4 27 4 1 wl1
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rlabel psubstratepcontact 27 11 27 11 1 gnd
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rlabel metal2 4 7 4 7 2 bl0
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rlabel metal2 11 7 11 7 1 bl1
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rlabel metal2 43 7 43 7 1 br1
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rlabel metal2 50 7 50 7 8 br0
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rlabel metal1 19 72 19 72 5 vdd
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rlabel metal1 19 65 19 65 1 wl0
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rlabel metal1 27 4 27 4 4 wl1
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rlabel psubstratepcontact 27 11 27 11 4 gnd
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rlabel metal2 4 7 4 7 4 bl0
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rlabel metal2 50 7 50 7 4 br0
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rlabel metal1 19 65 19 65 4 wl0
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rlabel metal2 11 7 11 7 4 bl1
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rlabel metal2 43 7 43 7 4 br1
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rlabel metal1 18 72 18 72 1 vdd
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<< properties >>
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string path 0.000 0.000 243.000 0.000 243.000 324.000 0.000 324.000 0.000 0.000
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<< end >>
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@ -1,6 +1,6 @@
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magic
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tech scmos
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timestamp 1558915332
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timestamp 1558933826
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<< nwell >>
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rect 0 48 54 77
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<< pwell >>
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@ -22,8 +22,10 @@ rect 13 34 14 38
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rect 16 34 17 38
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rect 21 34 22 38
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rect 17 30 22 34
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rect 24 30 25 38
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rect 29 30 30 38
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rect 24 36 30 38
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rect 24 32 25 36
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rect 29 32 30 36
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rect 24 30 30 32
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rect 32 34 33 38
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rect 37 34 38 38
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rect 40 34 41 38
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@ -31,8 +33,10 @@ rect 32 30 37 34
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rect 9 21 14 23
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rect 13 17 14 21
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rect 16 17 22 23
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rect 24 17 25 23
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rect 29 17 30 23
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rect 24 22 30 23
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rect 24 18 25 22
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rect 29 18 30 22
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rect 24 17 30 18
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rect 32 17 38 23
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rect 40 21 45 23
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rect 40 17 41 21
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@ -44,11 +48,11 @@ rect 32 56 33 59
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<< ndcontact >>
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rect 9 34 13 38
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rect 17 34 21 38
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rect 25 30 29 38
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rect 25 32 29 36
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rect 33 34 37 38
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rect 41 34 45 38
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rect 9 17 13 21
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rect 25 17 29 23
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rect 25 18 29 22
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rect 41 17 45 21
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<< pdcontact >>
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rect 17 56 21 60
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@ -57,17 +61,17 @@ rect 33 56 37 60
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<< psubstratepcontact >>
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rect 25 9 29 13
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<< nsubstratencontact >>
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rect 25 70 29 74
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rect 37 70 41 74
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<< polysilicon >>
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rect 22 59 24 62
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rect 30 59 32 62
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rect 22 45 24 56
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rect 30 53 32 56
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rect 13 41 16 45
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rect 13 41 16 43
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rect 14 38 16 41
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rect 22 38 24 41
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rect 30 38 32 49
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rect 38 41 41 45
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rect 38 41 41 43
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rect 38 38 40 41
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rect 14 32 16 34
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rect 38 32 40 34
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@ -88,27 +92,27 @@ rect 12 24 16 28
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rect 38 24 42 28
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<< metal1 >>
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rect 0 70 25 74
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rect 29 70 54 74
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rect 29 70 37 74
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rect 41 70 54 74
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rect 0 63 54 67
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rect 6 45 10 63
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rect 9 45 13 63
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rect 16 56 17 60
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rect 29 56 33 60
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rect 37 56 38 60
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rect 16 53 20 56
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rect 16 49 28 53
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rect 6 41 9 45
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rect 16 38 19 49
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rect 35 45 38 56
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rect 44 45 48 63
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rect 26 41 38 45
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rect 45 41 48 45
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rect 41 45 45 63
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rect 35 38 38 41
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rect 6 34 9 38
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rect 16 34 17 38
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rect 25 36 29 38
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rect 37 34 38 38
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rect 45 34 48 38
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rect 25 23 29 30
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rect 25 13 29 17
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rect 25 22 29 32
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rect 25 13 29 18
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rect 0 9 25 13
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rect 29 9 54 13
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rect 0 2 16 6
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@ -140,12 +144,14 @@ rect 48 0 52 34
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<< comment >>
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rect 0 0 54 72
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<< labels >>
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rlabel metal1 27 4 27 4 1 wl1
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rlabel psubstratepcontact 27 11 27 11 1 gnd
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rlabel metal2 4 7 4 7 2 bl0
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rlabel metal2 11 7 11 7 1 bl1
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rlabel metal2 43 7 43 7 1 br1
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rlabel metal2 50 7 50 7 8 br0
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rlabel metal1 19 72 19 72 5 vdd
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rlabel metal1 19 65 19 65 1 wl0
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rlabel metal1 27 4 27 4 4 wl1
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rlabel psubstratepcontact 27 11 27 11 4 gnd
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rlabel metal2 4 7 4 7 4 bl0
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rlabel metal2 50 7 50 7 4 br0
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rlabel metal1 19 65 19 65 4 wl0
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rlabel metal2 11 7 11 7 4 bl1
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rlabel metal2 43 7 43 7 4 br1
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rlabel metal1 18 72 18 72 1 vdd
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<< properties >>
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string path 0.000 0.000 243.000 0.000 243.000 324.000 0.000 324.000 0.000 0.000
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<< end >>
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@ -1,6 +1,6 @@
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magic
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tech scmos
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timestamp 1558915332
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timestamp 1558933826
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<< nwell >>
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rect 0 48 54 77
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<< pwell >>
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@ -22,8 +22,10 @@ rect 13 34 14 38
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rect 16 34 17 38
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rect 21 34 22 38
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rect 17 30 22 34
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rect 24 30 25 38
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rect 29 30 30 38
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rect 24 36 30 38
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rect 24 32 25 36
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rect 29 32 30 36
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rect 24 30 30 32
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rect 32 34 33 38
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rect 37 34 38 38
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rect 40 34 41 38
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@ -31,8 +33,10 @@ rect 32 30 37 34
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rect 9 21 14 23
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rect 13 17 14 21
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rect 16 17 22 23
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rect 24 17 25 23
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rect 29 17 30 23
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rect 24 22 30 23
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rect 24 18 25 22
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rect 29 18 30 22
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rect 24 17 30 18
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rect 32 17 38 23
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rect 40 21 45 23
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rect 40 17 41 21
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@ -44,11 +48,11 @@ rect 32 56 33 59
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<< ndcontact >>
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rect 9 34 13 38
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rect 17 34 21 38
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rect 25 30 29 38
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rect 25 32 29 36
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rect 33 34 37 38
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rect 41 34 45 38
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rect 9 17 13 21
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rect 25 17 29 23
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rect 25 18 29 22
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rect 41 17 45 21
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<< pdcontact >>
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rect 17 56 21 60
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@ -57,17 +61,17 @@ rect 33 56 37 60
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<< psubstratepcontact >>
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rect 25 9 29 13
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<< nsubstratencontact >>
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rect 25 70 29 74
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rect 37 70 41 74
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<< polysilicon >>
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rect 22 59 24 62
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rect 30 59 32 62
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rect 22 45 24 56
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rect 30 53 32 56
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rect 13 41 16 45
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rect 13 41 16 43
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rect 14 38 16 41
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rect 22 38 24 41
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rect 30 38 32 49
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rect 38 41 41 45
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rect 38 41 41 43
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rect 38 38 40 41
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rect 14 32 16 34
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rect 38 32 40 34
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@ -88,27 +92,27 @@ rect 12 24 16 28
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rect 38 24 42 28
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<< metal1 >>
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rect 0 70 25 74
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rect 29 70 54 74
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rect 29 70 37 74
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rect 41 70 54 74
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rect 0 63 54 67
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rect 6 45 10 63
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rect 9 45 13 63
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rect 16 56 17 60
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rect 29 56 33 60
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rect 37 56 38 60
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rect 16 53 20 56
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rect 16 49 28 53
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rect 6 41 9 45
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rect 16 38 19 49
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rect 35 45 38 56
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rect 44 45 48 63
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rect 26 41 38 45
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rect 45 41 48 45
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rect 41 45 45 63
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rect 35 38 38 41
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rect 6 34 9 38
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rect 16 34 17 38
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rect 25 36 29 38
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rect 37 34 38 38
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rect 45 34 48 38
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rect 25 23 29 30
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rect 25 13 29 17
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rect 25 22 29 32
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rect 25 13 29 18
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rect 0 9 25 13
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rect 29 9 54 13
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rect 0 2 16 6
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@ -140,12 +144,14 @@ rect 48 0 52 34
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<< comment >>
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rect 0 0 54 72
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<< labels >>
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rlabel metal1 27 4 27 4 1 wl1
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rlabel psubstratepcontact 27 11 27 11 1 gnd
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rlabel metal2 4 7 4 7 2 bl0
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rlabel metal2 11 7 11 7 1 bl1
|
||||
rlabel metal2 43 7 43 7 1 br1
|
||||
rlabel metal2 50 7 50 7 8 br0
|
||||
rlabel metal1 19 72 19 72 5 vdd
|
||||
rlabel metal1 19 65 19 65 1 wl0
|
||||
rlabel metal1 27 4 27 4 4 wl1
|
||||
rlabel psubstratepcontact 27 11 27 11 4 gnd
|
||||
rlabel metal2 4 7 4 7 4 bl0
|
||||
rlabel metal2 50 7 50 7 4 br0
|
||||
rlabel metal1 19 65 19 65 4 wl0
|
||||
rlabel metal2 11 7 11 7 4 bl1
|
||||
rlabel metal2 43 7 43 7 4 br1
|
||||
rlabel metal1 18 72 18 72 1 vdd
|
||||
<< properties >>
|
||||
string path 0.000 0.000 243.000 0.000 243.000 324.000 0.000 324.000 0.000 0.000
|
||||
<< end >>
|
||||
|
|
|
|||
|
|
@ -4,10 +4,12 @@ equate class {-circuit1 nfet} {-circuit2 n}
|
|||
equate class {-circuit1 pfet} {-circuit2 p}
|
||||
# This circuit has symmetries and needs to be flattened to resolve them
|
||||
# or the banks won't pass
|
||||
flatten class {-circuit1 precharge_array_1}
|
||||
flatten class {-circuit1 precharge_array_2}
|
||||
flatten class {-circuit1 precharge_array_3}
|
||||
flatten class {-circuit1 precharge_array_4}
|
||||
flatten class {-circuit1 bitcell_array_0}
|
||||
flatten class {-circuit1 bitcell_array_1}
|
||||
#flatten class {-circuit1 precharge_array_0}
|
||||
#flatten class {-circuit1 precharge_array_1}
|
||||
#flatten class {-circuit1 precharge_array_2}
|
||||
#flatten class {-circuit1 precharge_array_3}
|
||||
property {-circuit1 nfet} remove as ad ps pd
|
||||
property {-circuit1 pfet} remove as ad ps pd
|
||||
property {-circuit2 n} remove as ad ps pd
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
.SUBCKT cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
|
||||
MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
|
||||
MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
|
||||
MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u
|
||||
MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
|
||||
MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
|
||||
MM4 Q_bar wl0 br0 gnd n w=0.8u l=0.4u
|
||||
MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u
|
||||
MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u
|
||||
MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u
|
||||
MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u
|
||||
MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u
|
||||
MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u
|
||||
MM7 RA_to_R_left Q_bar gnd gnd n w=1.8u l=0.6u
|
||||
MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u
|
||||
MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u
|
||||
MM4 Q_bar wl0 br0 gnd n w=1.2u l=0.6u
|
||||
MM1 Q Q_bar gnd gnd n w=2.4u l=0.6u
|
||||
MM0 Q_bar Q gnd gnd n w=2.4u l=0.6u
|
||||
MM3 Q Q_bar vdd vdd p w=0.9u l=0.6u
|
||||
MM2 Q_bar Q vdd vdd p w=0.9u l=0.6u
|
||||
.ENDS
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
.SUBCKT cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
|
||||
MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
|
||||
MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
|
||||
MM7 RA_to_R_left Q_bar gnd gnd n w=1.2u l=0.4u
|
||||
MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
|
||||
MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
|
||||
MM4 Q_bar wl0 br0 gnd n w=0.8u l=0.4u
|
||||
MM1 Q Q_bar gnd gnd n w=1.6u l=0.4u
|
||||
MM0 Q_bar Q gnd gnd n w=1.6u l=0.4u
|
||||
MM3 Q Q_bar vdd vdd p w=0.6u l=0.4u
|
||||
MM2 Q_bar Q vdd vdd p w=0.6u l=0.4u
|
||||
MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u
|
||||
MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u
|
||||
MM7 RA_to_R_left Q_bar gnd gnd n w=1.8u l=0.6u
|
||||
MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u
|
||||
MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u
|
||||
MM4 Q_bar wl0 br0 gnd n w=1.2u l=0.6u
|
||||
MM1 Q Q_bar gnd gnd n w=2.4u l=0.6u
|
||||
MM0 Q_bar Q gnd gnd n w=2.4u l=0.6u
|
||||
MM3 Q Q_bar vdd vdd p w=0.9u l=0.6u
|
||||
MM2 Q_bar Q vdd vdd p w=0.9u l=0.6u
|
||||
.ENDS
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
.SUBCKT replica_cell_1rw_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
|
||||
MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
|
||||
MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
|
||||
MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u
|
||||
MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
|
||||
MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
|
||||
MM4 vdd wl0 br0 gnd n w=0.8u l=0.4u
|
||||
MM1 Q vdd gnd gnd n w=1.6u l=0.4u
|
||||
MM0 vdd Q gnd gnd n w=1.6u l=0.4u
|
||||
MM3 Q vdd vdd vdd p w=0.6u l=0.4u
|
||||
MM2 vdd Q vdd vdd p w=0.6u l=0.4u
|
||||
MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u
|
||||
MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u
|
||||
MM7 RA_to_R_left vdd gnd gnd n w=1.8u l=0.6u
|
||||
MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u
|
||||
MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u
|
||||
MM4 vdd wl0 br0 gnd n w=1.2u l=0.6u
|
||||
MM1 Q vdd gnd gnd n w=2.4u l=0.6u
|
||||
MM0 vdd Q gnd gnd n w=2.4u l=0.6u
|
||||
MM3 Q vdd vdd vdd p w=0.9u l=0.6u
|
||||
MM2 vdd Q vdd vdd p w=0.9u l=0.6u
|
||||
.ENDS
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
|
||||
.SUBCKT replica_cell_1w_1r bl0 br0 bl1 br1 wl0 wl1 vdd gnd
|
||||
MM9 RA_to_R_right wl1 br1 gnd n w=1.2u l=0.4u
|
||||
MM8 RA_to_R_right Q gnd gnd n w=1.2u l=0.4u
|
||||
MM7 RA_to_R_left vdd gnd gnd n w=1.2u l=0.4u
|
||||
MM6 RA_to_R_left wl1 bl1 gnd n w=1.2u l=0.4u
|
||||
MM5 Q wl0 bl0 gnd n w=0.8u l=0.4u
|
||||
MM4 vdd wl0 br0 gnd n w=0.8u l=0.4u
|
||||
MM1 Q vdd gnd gnd n w=1.6u l=0.4u
|
||||
MM0 vdd Q gnd gnd n w=1.6u l=0.4u
|
||||
MM3 Q vdd vdd vdd p w=0.6u l=0.4u
|
||||
MM2 vdd Q vdd vdd p w=0.6u l=0.4u
|
||||
MM9 RA_to_R_right wl1 br1 gnd n w=1.8u l=0.6u
|
||||
MM8 RA_to_R_right Q gnd gnd n w=1.8u l=0.6u
|
||||
MM7 RA_to_R_left vdd gnd gnd n w=1.8u l=0.6u
|
||||
MM6 RA_to_R_left wl1 bl1 gnd n w=1.8u l=0.6u
|
||||
MM5 Q wl0 bl0 gnd n w=1.2u l=0.6u
|
||||
MM4 vdd wl0 br0 gnd n w=1.2u l=0.6u
|
||||
MM1 Q vdd gnd gnd n w=2.4u l=0.6u
|
||||
MM0 vdd Q gnd gnd n w=2.4u l=0.6u
|
||||
MM3 Q vdd vdd vdd p w=0.9u l=0.6u
|
||||
MM2 vdd Q vdd vdd p w=0.9u l=0.6u
|
||||
.ENDS
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1764,6 +1764,11 @@ cifinput
|
|||
style lambda=0.20(p)
|
||||
scalefactor 20
|
||||
|
||||
# This is a custom section to add bounding boxes in OpenRAM
|
||||
layer bb BB
|
||||
labels BB
|
||||
calma BB 63 0
|
||||
|
||||
layer nwell CWN
|
||||
and-not CWNR
|
||||
and-not CTA
|
||||
|
|
@ -2450,10 +2455,6 @@ style lambda=0.20(p)
|
|||
and-not CBA
|
||||
calma CAA 43 *
|
||||
|
||||
layer comment CX
|
||||
labels CX
|
||||
calma CX 63 *
|
||||
|
||||
calma CTA 60 *
|
||||
|
||||
calma CRW 65 *
|
||||
|
|
@ -2470,6 +2471,11 @@ style lambda=0.20(p)
|
|||
style lambda=0.20(s)
|
||||
scalefactor 20
|
||||
|
||||
# This is a custom section to add bounding boxes in OpenRAM
|
||||
layer bb BB
|
||||
labels BB
|
||||
calma BB 63 0
|
||||
|
||||
layer nwell CWN
|
||||
and-not CWNR
|
||||
and-not CTA
|
||||
|
|
@ -3158,10 +3164,6 @@ style lambda=0.20(s)
|
|||
and-not CBA
|
||||
calma CAA 43 *
|
||||
|
||||
layer comment CX
|
||||
labels CX
|
||||
calma CX 63 *
|
||||
|
||||
calma CTA 60 *
|
||||
|
||||
calma CRW 65 *
|
||||
|
|
@ -3178,6 +3180,11 @@ style lambda=0.20(s)
|
|||
style lambda=0.20(ps)
|
||||
scalefactor 20
|
||||
|
||||
# This is a custom section to add bounding boxes in OpenRAM
|
||||
layer bb BB
|
||||
labels BB
|
||||
calma BB 63 0
|
||||
|
||||
layer nwell CWN
|
||||
and-not CWNR
|
||||
and-not CTA
|
||||
|
|
@ -3810,10 +3817,6 @@ style lambda=0.20(ps)
|
|||
and-not CBA
|
||||
calma CAA 43 *
|
||||
|
||||
layer comment CX
|
||||
labels CX
|
||||
calma CX 63 *
|
||||
|
||||
calma CTA 60 *
|
||||
|
||||
calma CRW 65 *
|
||||
|
|
@ -3830,6 +3833,11 @@ style lambda=0.20(ps)
|
|||
style lambda=0.20()
|
||||
scalefactor 20
|
||||
|
||||
# This is a custom section to add bounding boxes in OpenRAM
|
||||
layer bb BB
|
||||
labels BB
|
||||
calma BB 63 0
|
||||
|
||||
layer nwell CWN
|
||||
and-not CWNR
|
||||
and-not CTA
|
||||
|
|
@ -4516,10 +4524,6 @@ style lambda=0.20()
|
|||
and-not CBA
|
||||
calma CAA 43 *
|
||||
|
||||
layer comment CX
|
||||
labels CX
|
||||
calma CX 63 *
|
||||
|
||||
calma CTA 60 *
|
||||
|
||||
calma CRW 65 *
|
||||
|
|
@ -4536,6 +4540,11 @@ style lambda=0.20()
|
|||
style lambda=0.20(c)
|
||||
scalefactor 20
|
||||
|
||||
# This is a custom section to add bounding boxes in OpenRAM
|
||||
layer bb BB
|
||||
labels BB
|
||||
calma BB 63 0
|
||||
|
||||
layer nwell CWN
|
||||
and-not CWNR
|
||||
and-not CTA
|
||||
|
|
@ -4989,10 +4998,6 @@ style lambda=0.20(c)
|
|||
and-not CBA
|
||||
calma CAA 43 *
|
||||
|
||||
layer comment CX
|
||||
labels CX
|
||||
calma CX 63 *
|
||||
|
||||
calma CTA 60 *
|
||||
|
||||
calma CRW 65 *
|
||||
|
|
@ -5009,6 +5014,11 @@ style lambda=0.20(c)
|
|||
style lambda=0.20(cs)
|
||||
scalefactor 20
|
||||
|
||||
# This is a custom section to add bounding boxes in OpenRAM
|
||||
layer bb BB
|
||||
labels BB
|
||||
calma BB 63 0
|
||||
|
||||
layer nwell CWN
|
||||
and-not CWNR
|
||||
and-not CTA
|
||||
|
|
@ -5464,10 +5474,6 @@ style lambda=0.20(cs)
|
|||
and-not CBA
|
||||
calma CAA 43 *
|
||||
|
||||
layer comment CX
|
||||
labels CX
|
||||
calma CX 63 *
|
||||
|
||||
calma CTA 60 *
|
||||
|
||||
calma CRW 65 *
|
||||
|
|
@ -5484,6 +5490,11 @@ style lambda=0.20(cs)
|
|||
style lambda=0.20(cps)
|
||||
scalefactor 20
|
||||
|
||||
# This is a custom section to add bounding boxes in OpenRAM
|
||||
layer bb BB
|
||||
labels BB
|
||||
calma BB 63 0
|
||||
|
||||
layer nwell CWN
|
||||
and-not CWNR
|
||||
and-not CTA
|
||||
|
|
@ -5940,10 +5951,6 @@ style lambda=0.20(cps)
|
|||
and-not CBA
|
||||
calma CAA 43 *
|
||||
|
||||
layer comment CX
|
||||
labels CX
|
||||
calma CX 63 *
|
||||
|
||||
calma CTA 60 *
|
||||
|
||||
calma CRW 65 *
|
||||
|
|
@ -5960,6 +5967,11 @@ style lambda=0.20(cps)
|
|||
style lambda=0.20(cp)
|
||||
scalefactor 20
|
||||
|
||||
# This is a custom section to add bounding boxes in OpenRAM
|
||||
layer bb BB
|
||||
labels BB
|
||||
calma BB 63 0
|
||||
|
||||
layer nwell CWN
|
||||
and-not CWNR
|
||||
and-not CTA
|
||||
|
|
@ -6414,10 +6426,6 @@ style lambda=0.20(cp)
|
|||
and-not CBA
|
||||
calma CAA 43 *
|
||||
|
||||
layer comment CX
|
||||
labels CX
|
||||
calma CX 63 *
|
||||
|
||||
calma CTA 60 *
|
||||
|
||||
calma CRW 65 *
|
||||
|
|
|
|||
|
|
@ -86,8 +86,8 @@ drc["has_nwell"] = True
|
|||
drc["grid"]=0.5*_lambda_
|
||||
|
||||
#DRC/LVS test set_up
|
||||
drc["drc_rules"]=drclvs_home+"/calibreDRC_scn3me_subm.rul"
|
||||
drc["lvs_rules"]=drclvs_home+"/calibreLVS_scn3me_subm.rul"
|
||||
drc["drc_rules"]=None #drclvs_home+"/calibreDRC_scn3me_subm.rul"
|
||||
drc["lvs_rules"]=None #drclvs_home+"/calibreLVS_scn3me_subm.rul"
|
||||
drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
|
||||
|
||||
# minwidth_tx with contact (no dog bone transistors)
|
||||
|
|
|
|||
Loading…
Reference in New Issue