mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' into scn3me_subm
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commit
3fa8c5543a
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@ -28,7 +28,8 @@ class design(hierarchy_design):
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self.m1_pitch = max(contact.m1m2.width,contact.m1m2.height) + max(self.m1_space, self.m2_space)
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self.m2_pitch = max(contact.m2m3.width,contact.m2m3.height) + max(self.m2_space, self.m3_space)
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self.m3_pitch = max(contact.m3m4.width,contact.m3m4.height) + max(self.m3_space, self.m4_space)
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if contact.m3m4:
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self.m3_pitch = max(contact.m3m4.width,contact.m3m4.height) + max(self.m3_space, self.m4_space)
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def setup_drc_constants(self):
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""" These are some DRC constants used in many places in the compiler."""
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@ -42,8 +43,9 @@ class design(hierarchy_design):
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self.m2_space = drc("metal2_to_metal2")
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self.m3_width = drc("minwidth_metal3")
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self.m3_space = drc("metal3_to_metal3")
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self.m4_width = drc("minwidth_metal4")
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self.m4_space = drc("metal4_to_metal4")
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if contact.m3m4:
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self.m4_width = drc("minwidth_metal4")
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self.m4_space = drc("metal4_to_metal4")
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self.active_width = drc("minwidth_active")
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self.active_space = drc("active_to_body_active")
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self.contact_width = drc("minwidth_contact")
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