mirror of https://github.com/VLSIDA/OpenRAM.git
Removed some debug measurements that were causing failures.
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parent
ad229b1504
commit
36214792eb
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@ -149,31 +149,18 @@ class delay(simulation):
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def create_debug_measurement_objects(self):
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"""Create debug measurement to help identify failures."""
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self.debug_delay_meas = []
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self.debug_volt_meas = []
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for meas in self.delay_meas:
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debug_meas = copy.deepcopy(meas)
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debug_meas.name = debug_meas.name+'_debug'
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#This particular debugs check if output value is flipped, so TARG_DIR is flipped
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if meas.targ_dir_str == 'FALL':
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debug_meas.targ_dir_str = 'RISE'
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else:
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debug_meas.targ_dir_str = 'FALL'
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#inserting debug member variable
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debug_meas.parent = meas.name
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self.debug_delay_meas.append(debug_meas)
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#Output voltage measures
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self.debug_volt_meas.append(voltage_at_measure("v_{}".format(debug_meas.name),
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debug_meas.targ_name_no_port))
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self.debug_volt_meas[-1].meta_str = debug_meas.meta_str
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self.debug_volt_meas.append(voltage_at_measure("v_{}".format(meas.name),
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meas.targ_name_no_port))
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self.debug_volt_meas[-1].meta_str = meas.meta_str
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self.sen_meas = delay_measure("delay_sen", self.clk_frmt, self.sen_name, "FALL", "RISE", measure_scale=1e9)
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self.sen_meas.meta_str = sram_op.READ_ZERO
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self.sen_meas.meta_add_delay = True
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return self.debug_delay_meas+self.debug_volt_meas+[self.sen_meas]
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return self.debug_volt_meas+[self.sen_meas]
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def create_read_bit_measures(self):
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"""Adds bit measurements for read0 and read1 cycles"""
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@ -694,7 +681,7 @@ class delay(simulation):
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#Check sen timing, then bitlines, then general measurements.
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if not self.check_sen_measure(port):
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return (False,{})
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success = self.check_debug_measures(port, read_port_dict)
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success = self.check_debug_measures(port)
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success = success and self.check_bit_measures()
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#Check timing for read ports. Power is only checked if it was read correctly
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if not self.check_valid_delays(read_port_dict) or not success:
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@ -727,30 +714,11 @@ class delay(simulation):
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max_delay = self.period
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return not (type(sen_val) != float or sen_val > max_delay)
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def check_debug_measures(self, port, read_measures):
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def check_debug_measures(self, port):
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"""Debug measures that indicate special conditions."""
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#Currently, only check if the opposite than intended value was read during
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# the read cycles i.e. neither of these measurements should pass.
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success = True
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for meas in self.debug_delay_meas:
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val = meas.retrieve_measure(port=port)
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debug.info(2,"{}={}".format(meas.name, val))
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if type(val) != float:
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continue
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if meas.meta_add_delay:
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max_delay = self.period/2
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else:
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max_delay = self.period
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#If the debug measurement occurs after the original (and passes other conditions)
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#then it fails i.e. the debug value represents the final (but failing) state of the output
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parent_compare = type(read_measures[meas.parent]) != float or val > read_measures[meas.parent]
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if 0 < val < max_delay and parent_compare:
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success = False
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debug.info(1, "Debug measurement failed. Incorrect Value found on output.")
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break
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success = True
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#FIXME: these checks need to be re-done to be more robust against possible errors
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bl_vals = {}
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br_vals = {}
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