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Fixed error where word_size was compared to num_words and added write_size to control_logic.py

This commit is contained in:
jsowash 2019-07-01 15:51:40 -07:00
parent 242771f710
commit 67c6cdf3bb
4 changed files with 13 additions and 8 deletions
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9
compiler/modules/control_logic.py
View File

@ -21,7 +21,7 @@ class control_logic(design.design):
Dynamically generated Control logic for the total SRAM circuit.
"""
def __init__(self, num_rows, words_per_row, word_size, sram=None, port_type="rw", name=""):
def __init__(self, num_rows, words_per_row, word_size, write_size, sram=None, port_type="rw", name=""):
""" Constructor """
name = "control_logic_" + port_type
design.design.__init__(self, name)
@ -35,6 +35,7 @@ class control_logic(design.design):
self.words_per_row = words_per_row
self.word_size = word_size
self.port_type = port_type
self.write_size = write_size
self.num_cols = word_size*words_per_row
self.num_words = num_rows*words_per_row
@ -314,7 +315,11 @@ class control_logic(design.design):
self.input_list = ["csb", "web"]
else:
self.input_list = ["csb"]
if self.word_size != self.write_size:
print(self.word_size, self.write_size)
self.input_list = ["wmask"]
if self.port_type == "rw":
self.dff_output_list = ["cs_bar", "cs", "we_bar", "we"]
else:

5
compiler/sram/sram.py
View File

@ -34,7 +34,6 @@ class sram():
start_time = datetime.datetime.now()
self.name = name
if self.num_banks == 1:
from sram_1bank import sram_1bank as sram
@ -84,8 +83,6 @@ class sram():
self.gds_write(gdsname)
print_time("GDS", datetime.datetime.now(), start_time)
# Save the spice file
start_time = datetime.datetime.now()
spname = OPTS.output_path + self.s.name + ".sp"
@ -133,4 +130,4 @@ class sram():
vname = OPTS.output_path + self.s.name + ".v"
debug.print_raw("Verilog: Writing to {0}".format(vname))
self.verilog_write(vname)
print_time("Verilog", datetime.datetime.now(), start_time)
print_time("Verilog", datetime.datetime.now(), start_time)

3
compiler/sram/sram_base.py
View File

@ -303,6 +303,7 @@ class sram_base(design, verilog, lef):
self.control_logic_rw = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
word_size=self.word_size,
write_size = self.write_size,
sram=self,
port_type="rw")
self.add_mod(self.control_logic_rw)
@ -310,6 +311,7 @@ class sram_base(design, verilog, lef):
self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
word_size=self.word_size,
write_size=self.write_size,
sram=self,
port_type="w")
self.add_mod(self.control_logic_w)
@ -317,6 +319,7 @@ class sram_base(design, verilog, lef):
self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
word_size=self.word_size,
write_size=self.write_size,
sram=self,
port_type="r")
self.add_mod(self.control_logic_r)

4
compiler/sram/sram_config.py
View File

@ -23,8 +23,8 @@ class sram_config:
# This will get over-written when we determine the organization
self.words_per_row = words_per_row
if OPTS.write_size == None:
OPTS.write_size = OPTS.word_size
if self.write_size == None:
self.write_size = self.word_size
self.compute_sizes()