Removed wmask from addwrite()

compiler/characterizer/functional.py

@@ -91,7 +91,7 @@ class functional(simulation):
         addr = self.gen_addr()
         word = self.gen_data()
         comment = self.gen_cycle_comment("write", word, addr, 0, self.wmask, self.t_current)
-        self.add_write(comment, addr, word, self.wmask, 0)
+        self.add_write(comment, addr, word, 0)
         if self.wmask_enabled:
             old_word = ""
             if self.stored_words.get(addr) == None:

compiler/characterizer/simulation.py

@@ -131,7 +131,7 @@ class simulation():
                 debug.error("Non-binary address string",1)
             bit -= 1
                 
-    def add_write(self, comment, address, data, wmask, port):
+    def add_write(self, comment, address, data, port):
         """ Add the control values for a write cycle. """
         debug.check(port in self.write_ports, "Cannot add write cycle to a read port. Port {0}, Write Ports {1}".format(port, self.write_ports))
         debug.info(2, comment)

compiler/sram/sram_config.py

@@ -64,7 +64,26 @@ class sram_config:
             self.words_per_row = self.amend_words_per_row(self.tentative_num_rows, self.words_per_row)
 
         debug.info(1,"Words per row: {}".format(self.words_per_row))
-        self.recompute_sizes()
+        self.recompute_sizes_once()
+
+    def recompute_sizes_once(self):
+        """
+        Calculate the auxiliary values assuming fixed number of words per row.
+        """
+
+        # If the banks changed
+        self.num_words_per_bank = self.num_words / self.num_banks
+        self.num_bits_per_bank = self.word_size * self.num_words_per_bank
+
+        # Fix the number of columns and rows
+        self.num_cols = int(self.words_per_row * self.word_size)
+        self.num_rows = int(self.num_words_per_bank / self.words_per_row)
+
+        # Compute the address and bank sizes
+        self.row_addr_size = int(log(self.num_rows, 2))
+        self.col_addr_size = int(log(self.words_per_row, 2))
+        self.bank_addr_size = self.col_addr_size + self.row_addr_size
+        self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
 
     def recompute_sizes(self):
         """ 

compiler/tests/22_sram_wmask_func_test.py

@@ -34,8 +34,6 @@ class sram_wmask_func_test(openram_test):
                         num_words=16,
                         write_size=4,
                         num_banks=1)
-        c.words_per_row=4
-        c.recompute_sizes()
         debug.info(1, "Functional test for sram with {} bit words, {} words, {} words per row, {} bit writes, {} banks".format(c.word_size,
                                                                                                                 c.num_words,
                                                                                                                 c.words_per_row,