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OpenRAM
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3724 Commits

Author SHA1 Message Date
Eren Dogan 16490e9928 Merge branch 'conda' into dev 2023-03-13 16:10:35 -07:00
Eren Dogan 650b6e513c Remove the hack used for unit tests running on docker 2023-03-10 16:35:22 -08:00
mrg c9bf3c1261 Remove factory.reset from all unit tests as we no longer use regress.py. 2023-03-10 10:44:54 -08:00
Sam Crow e20f28580f support no rbls in local array 2023-03-09 14:44:05 -08:00
Sam Crow 710f0fbae5 update local/global tests for no rbls 2023-03-09 14:37:07 -08:00
Sam Crow 41344a980b change array modules to allow rbl=[0, 0] 2023-03-09 10:23:28 -08:00
Sam Crow 7abaf0463e create no rbl no dummy tests 2023-03-09 10:05:17 -08:00
mrg 5c173551ec Remove regress.py and skip_tests for Makefile option instead. 2023-03-02 12:44:52 -08:00
mrg 1f3bdd598a Add scn4m_subm global array test to skip test until issue is fixed. 2023-03-01 14:23:31 -08:00
mrg 49dbbb33bc Add skip tests until inverters added to sense amps. 2023-03-01 14:15:07 -08:00
mrg 58f1b55e08 Over-ride build_graph in row/col caps to remove incorrect graph error. 2023-03-01 09:25:56 -08:00
samuelkcrow e90964fbda update copyright 2023-02-21 14:04:31 -08:00
samuelkcrow ad4b4f66dc use capped array to create banks 2023-02-21 09:58:46 -08:00
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
samuelkcrow 52dcd81a08 use left_rbl instead of rbl to calculate replica column mirroring (column offset) 2023-02-20 17:28:24 -08:00
Eren Dogan b37711e643 Merge branch 'dev' into deploy_pip 2023-02-20 14:08:20 -08:00
mrg c07268d297 Disable power routing on some freepdk45 tests for issue 36 2023-02-17 17:00:04 -08:00
Eren Dogan d8a169e79f Reenable tests 2023-02-17 14:56:52 -08:00
Eren Dogan d3da632dc1 Fix typo in model delay test 2023-02-17 13:34:02 -08:00
Eren Dogan a7582c05dc Disable failing tests 2023-02-17 10:42:31 -08:00
samuelkcrow 51a7161cd7 fix mirroring of cap cells in cap rows 2023-02-14 10:59:00 -08:00
samuelkcrow 2565305158 fix positional getters 2023-02-13 18:45:21 -08:00
samuelkcrow 8d6d8f2f8c revert variable names to those inherited from bitcell base array 2023-02-13 18:45:21 -08:00
Eren Dogan 78e84ee8df Add version file 2023-02-07 10:30:48 -08:00
samuelkcrow 2948b08e66 copy rbl default values logic from lower array modules 2023-02-06 20:04:54 -08:00
samuelkcrow 796b1913cf fix typo in wordline var 2023-02-06 20:01:49 -08:00
samuelkcrow c256a5eb44 fix coppied functions from replica array to work correctly in capped array 2023-02-06 19:57:42 -08:00
samuelkcrow 4a22c5c56f add instance offset to capped array offset getters 2023-02-06 19:40:37 -08:00
samuelkcrow 92a9a1729e untested update to get_cell_name function used by characterizer 2023-02-06 19:19:02 -08:00
samuelkcrow 3dac89d041 fixing named variables passed between array modules 2023-02-04 21:06:41 -08:00
Eren Dogan dce324fc94 Fix newline for scripts 2023-01-28 22:59:08 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
samuelkcrow 2f795f8068 fix height calculation bug for replica array 2023-01-26 17:38:24 -08:00
samuelkcrow cc408447b1 standardize names and content of tests in the 14_* group 2023-01-26 14:14:25 -08:00
samuelkcrow 03adf94b6a fix offsets to match original replica array, and make array translation statically sized 2023-01-26 12:31:14 -08:00
samuelkcrow 8fc93bc91a point local array to new capped array module 2023-01-24 11:09:57 -08:00
samuelkcrow ebe163c57e fix placement bug for cap cells including wrong height from replica array 2023-01-24 11:07:52 -08:00
Eren Dogan c613693399 Don't use Docker for unit tests 2023-01-22 18:19:56 -08:00
Eren Dogan efba4d785e Fix other commands to use conda as well 2023-01-22 18:15:38 -08:00
Eren Dogan 0c08d5da5f Search for tools in conda first 2023-01-22 18:14:48 -08:00
Eren Dogan ca03da8d95 Use conda to install the tools needed 2023-01-20 15:34:45 -08:00
samuelkcrow 5573c6b241 fix pin shape issue 2023-01-18 22:44:32 -08:00
samuelkcrow d460eacfcc standardize rbl arguments interface 2023-01-18 22:43:37 -08:00
samuelkcrow 78c4ba5fc0 clean up comments 2023-01-18 21:01:30 -08:00
samuelkcrow 7021b80506 remove unused side argument from side routing functions 2023-01-18 20:36:36 -08:00
samuelkcrow 8522f32e43 radically simplify unused wordline routing code... bit of a facepalm tbh 2023-01-18 20:32:40 -08:00
samuelkcrow 78cabf9ca3 make capped array name more descriptive and add x mode to tests 2023-01-17 10:20:16 -08:00
samuelkcrow b5cddb9394 fix remaining lvs issues by adding an offset to pins gotten from subinstances and appropriately grounding wls in cap cells 2023-01-16 17:54:17 -08:00
samuelkcrow 29c79abaf8 move layout pins when copying them 2023-01-15 20:33:38 -08:00
samuelkcrow d8e0f4275d fix capped array after merge with dev 2022-12-14 14:20:54 -08:00
samuelkcrow f651b484c5 fix capped array tests after dev merge 2022-12-14 08:48:12 -08:00
samuelkcrow 6a8a76dd23 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl 2022-12-14 08:13:08 -08:00
samuelkcrow 119bcb9197 route unused wordlines (still failing lvs) 2022-12-14 08:12:55 -08:00
mrg 7ddb1a39dc Line wrap output spice subckt and instance lines at 80 characters. 2022-12-12 13:58:30 -08:00
samuelkcrow d224c06b25 placement positions problem fixed, incorrect w,h calculations were the problem 2022-12-10 19:03:55 -08:00
Eren Dogan fe81bbfd7e Fix paths in library usage tests 2022-12-02 20:28:14 -08:00
Eren Dogan 529dbb48c4 Fix sram creation in factory 2022-12-02 20:27:55 -08:00
Eren Dogan 6a4f6cbbed Move sram and sram_config to openram namespace 2022-12-02 15:28:06 -08:00
Eren Dogan fe0826d07c Add unit tests for library usage 2022-12-02 13:04:54 -08:00
Eren Dogan b40a17f4a5 Fix log file for sram_compiler tests 2022-12-02 13:00:12 -08:00
Eren Dogan 7396899769 Add empty build_graph() for dummy bitcells 2022-12-02 12:14:40 -08:00
samuelkcrow 68fb4e3c63 introduced some other bugs but scmos tiling is correct 2022-12-02 09:42:33 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan 175e95dd86 Delete unused scripts 2022-11-30 14:48:51 -08:00
Eren Dogan e15454ebb9 Make sram_config optional for sram 2022-11-29 10:33:32 -08:00
Eren Dogan a37d41b406 Fix typo 2022-11-27 16:41:28 -08:00
Eren Dogan 316f75861b Fix unit tests running on docker with a hack for now 2022-11-27 14:32:55 -08:00
Eren Dogan 2e7206343e Remove unnecessary imports 2022-11-27 13:11:10 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
samuelkcrow ac8a15acc0 fix get_replica_top and get_replica_left return values 2022-11-21 17:42:50 -08:00
Eren Dogan e718106d87 Change is_unit_test to False by default 2022-11-21 14:52:57 -08:00
Eren Dogan e821b4a75e Print info regarding which directories are being used 2022-11-10 22:24:41 -08:00
Eren Dogan f95ff3c694 Fix library path in globals.setup_paths() 2022-11-10 21:50:31 -08:00
Eren Dogan 845f32805f Change compiler name for unit tests 2022-11-06 14:05:08 -08:00
Eren Dogan 62700e4d2b Fix OPENRAM_HOME path for library 2022-11-04 15:47:38 -07:00
Eren Dogan 557b2e7459 Reorganize library files to include everything 2022-11-04 15:10:44 -07:00
Eren Dogan 740cff985a Inform user when library's tech is used 2022-11-03 22:02:05 -07:00
mrg a213d3b0f6 Merge branch 'dev' into library 2022-11-02 16:20:56 -07:00
mrg b1a88d8c8a Remove variable reference in ifdef 2022-11-02 08:02:22 -07:00
Eren Dogan dacc0acd4d Fix paths while initializing 2022-10-25 13:01:02 -07:00
Eren Dogan 92460d2080 Move the compiler script to the root 2022-10-25 12:22:57 -07:00
Eren Dogan dc9d1e00d8 Add setup files for package 2022-10-25 12:22:18 -07:00
samuelkcrow 5a82c45a33 Change how lists of BLs and WLs are named and organized for proper connection between these modules 2022-10-24 20:08:13 -07:00
mrg 9b6eb4a120 Fix whitespace 2022-10-20 16:38:23 -07:00
mrg 8fd08916a1 Move is_non_inverting graph code to bitcell_base class to work with pbitcell too. 2022-10-20 15:16:10 -07:00
mrg aeca2c6b88 Allow any definition of KEEP to keep temp files 2022-10-20 14:31:26 -07:00
samuelkcrow 55d89fbae8 copy supply pins to top level in replica array, now passing tests 2022-10-19 17:13:54 -07:00
samuelkcrow f9419e8ff7 fix self.rbls and fix handling of rbl WLs (kinda) 2022-10-17 20:51:42 -07:00
samuelkcrow a1ca7c312d remove grounded WLs from replica array 2022-10-11 11:43:26 -07:00
samuelkcrow cfd52a6065 fix offsets so array ends up at 0,0 2022-09-26 14:24:16 -07:00
samuelkcrow 8bc3903a04 remove end caps from replica column (will not pass sky130 drc) 2022-09-26 14:23:09 -07:00
samuelkcrow 37dee02161 Merge branch 'dev' into no_rbl 2022-09-13 12:34:57 -07:00
Jesse Cirimelli-Low 3b02a8846d sky130 rba passing :) 2022-09-12 16:07:00 -07:00
samuelkcrow 004ee3748d add option to keep tmp files when running tests with make 2022-09-08 13:40:48 -07:00
samuelkcrow f1f18b3b54 replica code working but failing lvs 2022-09-07 19:32:25 -07:00
samuelkcrow 3ef52789be first pass splitting replica array into capped and replica array modules 2022-09-07 12:39:35 -07:00
samuelkcrow fe0cfac6c8 tests for new capped array module 2022-09-07 12:39:01 -07:00
Bugra Onal 57d7a78421 Merge branch 'multibank' into dev 2022-08-30 09:19:19 -07:00
Bugra Onal 1a214a7309 Fixed utest 25 golden 2022-08-30 09:17:51 -07:00
Jesse Cirimelli-Low 11fa0777e8 add flatglob to tech file; sky130 replica col lvs working 2022-08-22 15:30:11 -07:00
Bugra Onal c0c15537d9 Added golden files for freepdk test 25 2022-08-18 11:04:53 -07:00
Bugra Onal 25cc08db80 Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
Bugra Onal a7c6406d0d Changed verilog file naming convention 2022-08-18 10:36:54 -07:00
Bugra Onal 1a23d156c0 remove references to bank_sel 2022-08-18 10:33:46 -07:00
Bugra Onal 242d90f543 Code format fixes 2022-08-13 13:58:53 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal b33c2ab96c Fixed test 25 golden files 2022-08-12 21:33:40 -07:00
Bugra Onal 6ba2a9bca7 Make sure num_wmasks is 0 when no wmask is generated 2022-08-10 16:35:39 -07:00
Bugra Onal f743b1f068 Convert to new modules format 2022-08-10 16:34:49 -07:00
Bugra Onal 623c1ac02f Convert unit test 25 to new modules convert 2022-08-10 16:33:50 -07:00
Bugra Onal dc1626879e Characterizer wmask check for write_size 2022-08-10 16:11:19 -07:00
Bugra Onal 2d849aef39 Write size updated in recompute_sizes 2022-08-10 15:36:41 -07:00
Bugra Onal 48fce6485d write_size None initialization fixed 2022-08-04 16:37:21 -07:00
Bugra Onal 2ed107f9ff Fix the total addr_size 2022-08-04 16:36:26 -07:00
Bugra Onal 0ca14a3662 Fix typo on w_en 2022-08-04 16:35:09 -07:00
samuelkcrow 1177df6193 move most of place_instances to base 2022-08-01 10:33:48 -07:00
Bugra Onal 7fe0f647ef fix 2022-07-28 17:00:16 -07:00
Bugra Onal 8f955207d3 Fixed write_size checks for characterizer 2022-07-28 16:47:29 -07:00
Bugra Onal a361d9f7bb Fixed write_size checks for None 2022-07-28 16:45:58 -07:00
Bugra Onal 6efe974d7b Delete sram_base form rebase 2022-07-28 16:02:39 -07:00
Bugra Onal 9771bb7056 Don't generate wmask and if word per line is 1 2022-07-28 15:59:28 -07:00
Bugra Onal 02d8eca640 Fix indentation 2022-07-28 15:07:19 -07:00
Bugra Onal 36e23dc80f Moved template module to new modules folder 2022-07-28 15:05:34 -07:00
Bugra Onal bac40fa630 Removed SRAM directory 2022-07-28 15:04:53 -07:00
Bugra Onal caac39c88b Added 1bank module check to the multibank test 2022-07-28 15:03:41 -07:00
Bugra Onal 3f1a5a2051 Shrunk address register in multibank verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 6b5fe8a096 Changed test name for multibank verilog test 2022-07-28 15:03:41 -07:00
Bugra Onal 8f00e396cd Added unit test for multibank 2022-07-28 15:03:41 -07:00
Bugra Onal d36f74a514 Not mathcing whitespace bug fixed 2022-07-28 15:03:41 -07:00
Bugra Onal 5f45f7db15 Fixed the bad commas with post-process regex 2022-07-28 15:03:41 -07:00
Bugra Onal 9bd3f1b45a None check syntax fix 2022-07-28 15:03:41 -07:00
Bugra Onal a75951b5b1 write_size init in sram_config 2022-07-28 15:03:41 -07:00
Bugra Onal e130ba736c Fixed indent error on write_size init 2022-07-28 15:03:41 -07:00
Bugra Onal 898a1f07f5 Fixed verilog filename double extension 2022-07-28 15:03:41 -07:00
Bugra Onal a87b40e1cb Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal c1e891b2fb Multibank file generation (messy) 2022-07-28 15:03:41 -07:00
Bugra Onal 846dfc79dc modified template engine & sram multibank class 2022-07-28 15:03:41 -07:00
Bugra Onal bbcbddd934 Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal bde4a389aa Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal 9158e92a71 TEmplate rework 2022-07-28 15:03:41 -07:00
Bugra Onal a5728cdecc Base-verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 769633a459 Base template additions 2022-07-28 15:03:41 -07:00
Bugra Onal cda3822526 Verilog Template additions 2022-07-28 15:03:41 -07:00
Bugra Onal 28c5406075 Base verilog template init 2022-07-28 15:03:41 -07:00
Bugra Onal 2b1d0bd9f7 Template module done 2022-07-28 15:03:41 -07:00
Bugra Onal 0970095415 Bank select 2022-07-28 15:03:41 -07:00
Bugra Onal 859548f19f Templatable verilog file 2022-07-28 15:03:41 -07:00
Bugra Onal f08da6acc5 Fixed globals conflict 2022-07-28 15:03:41 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Bugra Onal a0c6a0ad03 Set write_size default to word_size 2022-07-28 15:03:41 -07:00
Bugra Onal 29079bd6ac Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal 24bb6f8c11 Multibank file generation (messy) 2022-07-28 15:03:37 -07:00
samuelkcrow 1c8aeaa68a fix imports 2022-07-27 11:09:10 -07:00
samuelkcrow 2ff9ea4f78 move generic functions from control_logic module to new control_logic_base module 2022-07-26 23:22:02 -07:00
mrg 5db470155e Fix print errors in code format unit test. 2022-07-26 12:20:15 -07:00
mrg 69d5731d67 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2022-07-22 13:47:19 -07:00
samuelkcrow f01e73328d remove superfluous imports from multiport test 2022-07-22 13:12:03 -07:00
samuelkcrow b82213caff use packages for imports in modules 2022-07-22 12:56:47 -07:00
samuelkcrow 480862c765 remove sys.path.append calls from tests 2022-07-22 11:24:54 -07:00
Eren Dogan 03422be48c Fix carriage return 2022-07-22 19:54:35 +03:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
Eren Dogan 2a778dca82 Add whitespace check to code format test 2022-07-22 18:22:40 +03:00
Eren Dogan 64c72ee19d Fix typo 2022-07-22 18:15:27 +03:00
Eren Dogan 449c68ccae Fix file setup in code format test 2022-07-22 18:11:14 +03:00
samuelkcrow 75efc476f7 add remaining tests 2022-07-21 19:35:02 -07:00
samuelkcrow 5fa0689c02 fix drc error in wlen_row 2022-07-21 19:35:02 -07:00
samuelkcrow 08ac1c176a connect in pin via m2 instead of m3, passes lvs now 2022-07-21 19:35:02 -07:00
samuelkcrow 12c58b0457 use spice names for delay chain output pins in layout 2022-07-21 19:35:02 -07:00
samuelkcrow 73021be8eb copy vertical bus spacing from control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 2611468dd7 replace route_supply with route supplies from control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 9182ad7c61 add m4 spacing for route_rails same as control_logic.py 2022-07-21 19:35:02 -07:00
samuelkcrow 7f52e63aca route glitch3 to inverter on wen row 2022-07-21 19:35:02 -07:00
samuelkcrow 231dca5b51 route w_en A and B inputs via M3, fix delay chain outputs connection to vertical bus 2022-07-21 19:35:02 -07:00
samuelkcrow 74bf3770d9 move pins to m3, route in pin down to avoid m3 collision 2022-07-21 19:35:02 -07:00
samuelkcrow 7567db6fe9 add rw port unit test for delay control 2022-07-21 19:35:02 -07:00
samuelkcrow fd7a7c2564 routing mistake in route_wlen 2022-07-21 19:35:02 -07:00
samuelkcrow 1e1ec54275 fix indentation errors, typos, and missing iterator 2022-07-21 19:35:02 -07:00
samuelkcrow 3526a57864 don't route rbl to conrol logic 2022-07-21 19:35:02 -07:00
samuelkcrow 1d6bd78612 multi-delay layout pins and routing for them in control logic 2022-07-21 19:35:01 -07:00
samuelkcrow d7b1368115 all route functions except for delay 2022-07-21 19:35:01 -07:00
samuelkcrow 63ea1588c1 more consise glitch names, remove pre_sen from vertical bus, typo in glitch2 placement 2022-07-21 19:35:01 -07:00
samuelkcrow 0a3c1dd9b8 remove pre_sen entirely, move inverter to wl_en row, complete placement functions 2022-07-21 19:35:01 -07:00
samuelkcrow 7b4af87fda remove the cs_buf function call... smh 2022-07-21 19:35:01 -07:00
samuelkcrow 5edb511dab try it without pre_sen 2022-07-21 19:35:01 -07:00
samuelkcrow 71f241f660 remove remaining cs_buf functions 2022-07-21 19:35:01 -07:00
samuelkcrow 67c1560df0 forgot other place with cs_buf 2022-07-21 19:35:01 -07:00
samuelkcrow fede082b80 cs instead of cs_buf now that everything else is working 2022-07-21 19:35:01 -07:00
samuelkcrow 30b9c2fc25 remove glitch inverters from placement functions, move glitch1 to pen row 2022-07-21 19:35:01 -07:00
samuelkcrow 606260dd68 use odd number inverter chains from delay chain for delay instead of external inverters 2022-07-21 19:35:01 -07:00
samuelkcrow b9b57ab6b3 double length of delay chain as well 2022-07-21 19:35:01 -07:00
samuelkcrow 06254fae72 forgot to multiply all delay chain pinouts by 2 because of previous design that only exposed pins for even numbered inverters in delay chain... oops 2022-07-21 19:35:01 -07:00
samuelkcrow 1d0741baa4 temporariliy commenting out path code that's making simulation fail. 2022-07-21 19:35:01 -07:00
samuelkcrow ef2c9fe296 exclude rbl connection in sram base for delay control logic 2022-07-21 19:35:01 -07:00
samuelkcrow 7d4b718344 add most functions needed for delay control logic, fix multi-delay pin order issue 2022-07-21 19:35:01 -07:00
samuelkcrow 45239ca2a9 use cs_buf for sense amp on r ports instead of cs 2022-07-21 19:35:01 -07:00
samuelkcrow c4138c9f9b typo in cs buf netlist function 2022-07-21 19:35:01 -07:00
samuelkcrow 2b72fbee4e bug fix list vs set 2022-07-21 19:35:01 -07:00
samuelkcrow 11ea82e782 check delay chain pinout list, add cs_buf to control logic 2022-07-21 19:35:01 -07:00
samuelkcrow 78013d32b7 hard-code multi-delay stages 2022-07-21 19:35:01 -07:00
samuelkcrow 62a65f8053 all remaining spice for delay control 2022-07-21 19:35:01 -07:00